1 /* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12 #ifndef __ROCKCHIP_SIP_H
13 #define __ROCKCHIP_SIP_H
14
15 #include <linux/arm-smccc.h>
16 #include <linux/io.h>
17
18 /* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */
19 #define SIP_ATF_VERSION 0x82000001
20 #define SIP_ACCESS_REG 0x82000002
21 #define SIP_SUSPEND_MODE 0x82000003
22 #define SIP_PENDING_CPUS 0x82000004
23 #define SIP_UARTDBG_CFG 0x82000005
24 #define SIP_UARTDBG_CFG64 0xc2000005
25 #define SIP_MCU_EL3FIQ_CFG 0x82000006
26 #define SIP_ACCESS_CHIP_STATE64 0xc2000006
27 #define SIP_SECURE_MEM_CONFIG 0x82000007
28 #define SIP_ACCESS_CHIP_EXTRA_STATE64 0xc2000007
29 #define SIP_DRAM_CONFIG 0x82000008
30 #define SIP_SHARE_MEM 0x82000009
31 #define SIP_SIP_VERSION 0x8200000a
32 #define SIP_REMOTECTL_CFG 0x8200000b
33 #define PSCI_SIP_VPU_RESET 0x8200000c
34 #define SIP_BUS_CFG 0x8200000d
35 #define SIP_LAST_LOG 0x8200000e
36 #define SIP_SCMI_AGENT0 0x82000010
37 #define SIP_SCMI_AGENT1 0x82000011
38 #define SIP_SCMI_AGENT2 0x82000012
39 #define SIP_SCMI_AGENT3 0x82000013
40 #define SIP_SCMI_AGENT4 0x82000014
41 #define SIP_SCMI_AGENT5 0x82000015
42 #define SIP_SCMI_AGENT6 0x82000016
43 #define SIP_SCMI_AGENT7 0x82000017
44 #define SIP_SCMI_AGENT8 0x82000018
45 #define SIP_SCMI_AGENT9 0x82000019
46 #define SIP_SCMI_AGENT10 0x8200001a
47 #define SIP_SCMI_AGENT11 0x8200001b
48 #define SIP_SCMI_AGENT12 0x8200001c
49 #define SIP_SCMI_AGENT13 0x8200001d
50 #define SIP_SCMI_AGENT14 0x8200001e
51 #define SIP_SCMI_AGENT15 0x8200001f
52 #define SIP_SDEI_FIQ_DBG_SWITCH_CPU 0x82000020
53 #define SIP_SDEI_FIQ_DBG_GET_EVENT_ID 0x82000021
54 #define RK_SIP_AMP_CFG 0x82000022
55 #define RK_SIP_FIQ_CTRL 0x82000024
56 #define SIP_HDCP_CONFIG 0x82000025
57 #define SIP_WDT_CFG 0x82000026
58 #define SIP_HDMIRX_CFG 0x82000027
59 #define SIP_MCU_CFG 0x82000028
60
61 #define TRUSTED_OS_HDCPKEY_INIT 0xB7000003
62
63 /* Rockchip Sip version */
64 #define SIP_IMPLEMENT_V1 (1)
65 #define SIP_IMPLEMENT_V2 (2)
66
67 /* Trust firmware version */
68 #define ATF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
69 #define ATF_VER_MINOR(ver) (((ver) >> 0) & 0xffff)
70
71 /* SIP_ACCESS_REG: read or write */
72 #define SECURE_REG_RD 0x0
73 #define SECURE_REG_WR 0x1
74
75 /* Fiq debugger share memory: 8KB enough */
76 #define FIQ_UARTDBG_PAGE_NUMS 2
77 #define FIQ_UARTDBG_SHARE_MEM_SIZE ((FIQ_UARTDBG_PAGE_NUMS) * 4096)
78
79 /* Error return code */
80 #define IS_SIP_ERROR(x) (!!(x))
81
82 #define SIP_RET_SUCCESS 0
83 #define SIP_RET_SMC_UNKNOWN -1
84 #define SIP_RET_NOT_SUPPORTED -2
85 #define SIP_RET_INVALID_PARAMS -3
86 #define SIP_RET_INVALID_ADDRESS -4
87 #define SIP_RET_DENIED -5
88 #define SIP_RET_SET_RATE_TIMEOUT -6
89
90 /* SIP_UARTDBG_CFG64 call types */
91 #define UARTDBG_CFG_INIT 0xf0
92 #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
93 #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
94 #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
95 #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
96 #define UARTDBG_CFG_PRINT_PORT 0xf7
97 #define UARTDBG_CFG_FIQ_ENABEL 0xf8
98 #define UARTDBG_CFG_FIQ_DISABEL 0xf9
99
100 /* SIP_SUSPEND_MODE32 call types */
101 #define SUSPEND_MODE_CONFIG 0x01
102 #define WKUP_SOURCE_CONFIG 0x02
103 #define PWM_REGULATOR_CONFIG 0x03
104 #define GPIO_POWER_CONFIG 0x04
105 #define SUSPEND_DEBUG_ENABLE 0x05
106 #define APIOS_SUSPEND_CONFIG 0x06
107 #define VIRTUAL_POWEROFF 0x07
108 #define SUSPEND_WFI_TIME_MS 0x08
109 #define LINUX_PM_STATE 0x09
110 #define SUSPEND_IO_RET_CONFIG 0x0a
111 #define SLEEP_PIN_CONFIG 0x0b
112
113 /* SIP_REMOTECTL_CFG call types */
114 #define REMOTECTL_SET_IRQ 0xf0
115 #define REMOTECTL_SET_PWM_CH 0xf1
116 #define REMOTECTL_SET_PWRKEY 0xf2
117 #define REMOTECTL_GET_WAKEUP_STATE 0xf3
118 #define REMOTECTL_ENABLE 0xf4
119 /* wakeup state */
120 #define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf
121
122 /* SIP_MCU_CFG child configs, MCU ID */
123 enum {
124 RK_BUS_MCU,
125 RK_PMU_MCU,
126 RK_DDR_MCU,
127 RK_NPU_MCU,
128 };
129
130 #define RK_SIP_MCU_ID(type, id) ((type) << 8 | id)
131
132 #define RK_SIP_CFG_BUSMCU_0_ID RK_SIP_MCU_ID(RK_BUS_MCU, 0)
133 #define RK_SIP_CFG_BUSMCU_1_ID RK_SIP_MCU_ID(RK_BUS_MCU, 1)
134 #define RK_SIP_CFG_PMUMCU_0_ID RK_SIP_MCU_ID(RK_PMU_MCU, 0)
135 #define RK_SIP_CFG_DDRMCU_0_ID RK_SIP_MCU_ID(RK_DDR_MCU, 0)
136 #define RK_SIP_CFG_NPUMCU_0_ID RK_SIP_MCU_ID(RK_NPU_MCU, 0)
137
138 /* SIP_MCU_CFG child configs */
139 #define CONFIG_MCU_CODE_START_ADDR 0x01
140 #define CONFIG_MCU_EXPERI_START_ADDR 0x02
141 #define CONFIG_MCU_SRAM_START_ADDR 0x03
142 #define CONFIG_MCU_EXSRAM_START_ADDR 0x04
143
144 struct dram_addrmap_info {
145 u64 ch_mask[2];
146 u64 bk_mask[4];
147 u64 bg_mask[2];
148 u64 cs_mask[2];
149 u32 reserved[20];
150 u32 bank_bit_first;
151 u32 bank_bit_mask;
152 };
153
154 /* AMP Ctrl */
155 enum {
156 RK_AMP_SUB_FUNC_CFG_MODE = 0,
157 RK_AMP_SUB_FUNC_BOOT_ARG01,
158 RK_AMP_SUB_FUNC_BOOT_ARG23,
159 RK_AMP_SUB_FUNC_REQ_CPU_OFF,
160 RK_AMP_SUB_FUNC_GET_CPU_STATUS,
161 RK_AMP_SUB_FUNC_RSV, /* for RTOS */
162 RK_AMP_SUB_FUNC_CPU_ON,
163 RK_AMP_SUB_FUNC_END,
164 };
165
166 enum {
167 FIRMWARE_NONE,
168 FIRMWARE_TEE_32BIT,
169 FIRMWARE_ATF_32BIT,
170 FIRMWARE_ATF_64BIT,
171 FIRMWARE_END,
172 };
173
174 /* Share mem page types */
175 typedef enum {
176 SHARE_PAGE_TYPE_INVALID = 0,
177 SHARE_PAGE_TYPE_UARTDBG,
178 SHARE_PAGE_TYPE_DDR,
179 SHARE_PAGE_TYPE_DDRDBG,
180 SHARE_PAGE_TYPE_DDRECC,
181 SHARE_PAGE_TYPE_DDRFSP,
182 SHARE_PAGE_TYPE_DDR_ADDRMAP,
183 SHARE_PAGE_TYPE_LAST_LOG,
184 SHARE_PAGE_TYPE_HDCP,
185 SHARE_PAGE_TYPE_MAX,
186 } share_page_type_t;
187
188 /* fiq control sub func */
189 enum {
190 RK_SIP_FIQ_CTRL_FIQ_EN = 1,
191 RK_SIP_FIQ_CTRL_FIQ_DIS,
192 RK_SIP_FIQ_CTRL_SET_AFF
193 };
194
195 /* hdcp function types */
196 enum {
197 HDCP_FUNC_STORAGE_INCRYPT = 1,
198 HDCP_FUNC_KEY_LOAD,
199 HDCP_FUNC_ENCRYPT_MODE
200 };
201
202 /* support hdcp device list */
203 enum {
204 DP_TX0,
205 DP_TX1,
206 EDP_TX0,
207 EDP_TX1,
208 HDMI_TX0,
209 HDMI_TX1,
210 HDMI_RX,
211 MAX_DEVICE,
212 };
213
214 /* SIP_WDT_CONFIG call types */
215 enum {
216 WDT_START = 0,
217 WDT_STOP = 1,
218 WDT_PING = 2,
219 };
220
221 /* SIP_HDMIRX_CONFIG child configs */
222 enum {
223 HDMIRX_AUTO_TOUCH_EN = 0,
224 HDMIRX_REG_PRE_FETCH = 1,
225 HDMIRX_INFO_NOTIFY = 2,
226 };
227
228 struct pt_regs;
229 typedef void (*sip_fiq_debugger_uart_irq_tf_cb_t)(struct pt_regs *_pt_regs, unsigned long cpu);
230
231 /*
232 * Rules: struct arm_smccc_res contains result and data, details:
233 *
234 * a0: error code(0: success, !0: error);
235 * a1~a3: data
236 */
237 #if IS_REACHABLE(CONFIG_ROCKCHIP_SIP)
238 struct arm_smccc_res sip_smc_get_atf_version(void);
239 struct arm_smccc_res sip_smc_get_sip_version(void);
240 struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2);
241 struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
242 share_page_type_t page_type);
243 struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2);
244 struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2);
245 struct arm_smccc_res sip_smc_get_suspend_info(u32 info);
246 struct arm_smccc_res sip_smc_lastlog_request(void);
247
248 int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2);
249 int sip_smc_virtual_poweroff(void);
250 int sip_smc_remotectl_config(u32 func, u32 data);
251
252 int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
253 u32 sip_smc_secure_reg_read(u32 addr_phy);
254 struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2);
255 struct dram_addrmap_info *sip_smc_get_dram_map(void);
256 int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3);
257 struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id, u32 arg1);
258
259 void __iomem *sip_hdcp_request_share_memory(int id);
260 struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2);
261 ulong sip_cpu_logical_map_mpidr(u32 cpu);
262 /***************************fiq debugger **************************************/
263 void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu);
264 void sip_fiq_debugger_enable_debug(bool enable);
265 int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, sip_fiq_debugger_uart_irq_tf_cb_t callback_fn);
266 int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate);
267 int sip_fiq_debugger_request_share_memory(void);
268 int sip_fiq_debugger_get_target_cpu(void);
269 int sip_fiq_debugger_switch_cpu(u32 cpu);
270 int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu, u32 flag);
271 int sip_fiq_debugger_is_enabled(void);
272 int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag);
273 int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data);
274 int sip_wdt_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3);
275 int sip_hdmirx_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3);
276 int sip_hdcpkey_init(u32 hdcp_id);
277 int sip_smc_mcu_config(unsigned long mcu_id, unsigned long func, unsigned long arg2);
278 #else
sip_smc_get_atf_version(void)279 static inline struct arm_smccc_res sip_smc_get_atf_version(void)
280 {
281 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
282 return tmp;
283 }
284
sip_smc_get_sip_version(void)285 static inline struct arm_smccc_res sip_smc_get_sip_version(void)
286 {
287 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
288 return tmp;
289 }
290
sip_smc_dram(u32 arg0,u32 arg1,u32 arg2)291 static inline struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2)
292 {
293 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
294 return tmp;
295 }
296
sip_smc_request_share_mem(u32 page_num,share_page_type_t page_type)297 static inline struct arm_smccc_res sip_smc_request_share_mem
298 (u32 page_num, share_page_type_t page_type)
299 {
300 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
301 return tmp;
302 }
303
sip_smc_mcu_el3fiq(u32 arg0,u32 arg1,u32 arg2)304 static inline struct arm_smccc_res sip_smc_mcu_el3fiq
305 (u32 arg0, u32 arg1, u32 arg2)
306 {
307 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
308 return tmp;
309 }
310
311 static inline struct arm_smccc_res
sip_smc_vpu_reset(u32 arg0,u32 arg1,u32 arg2)312 sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
313 {
314 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
315 return tmp;
316 }
317
sip_smc_get_suspend_info(u32 info)318 static inline struct arm_smccc_res sip_smc_get_suspend_info(u32 info)
319 {
320 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
321 return tmp;
322 }
323
sip_smc_lastlog_request(void)324 static inline struct arm_smccc_res sip_smc_lastlog_request(void)
325 {
326 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
327 return tmp;
328 }
329
sip_smc_set_suspend_mode(u32 ctrl,u32 config1,u32 config2)330 static inline int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
331 {
332 return 0;
333 }
334
sip_smc_virtual_poweroff(void)335 static inline int sip_smc_virtual_poweroff(void) { return 0; }
sip_smc_remotectl_config(u32 func,u32 data)336 static inline int sip_smc_remotectl_config(u32 func, u32 data) { return 0; }
sip_smc_secure_reg_write(u32 addr_phy,u32 val)337 static inline int sip_smc_secure_reg_write(u32 addr_phy, u32 val) { return 0; }
sip_smc_secure_reg_read(u32 addr_phy)338 static inline u32 sip_smc_secure_reg_read(u32 addr_phy) { return 0; }
339
sip_smc_bus_config(u32 arg0,u32 arg1,u32 arg2)340 static inline struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2)
341 {
342 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
343 return tmp;
344 }
345
sip_smc_get_dram_map(void)346 static inline struct dram_addrmap_info *sip_smc_get_dram_map(void)
347 {
348 return NULL;
349 }
350
sip_smc_amp_config(u32 sub_func_id,u32 arg1,u32 arg2,u32 arg3)351 static inline int sip_smc_amp_config(u32 sub_func_id,
352 u32 arg1,
353 u32 arg2,
354 u32 arg3)
355 {
356 return 0;
357 }
358
sip_smc_get_amp_info(u32 sub_func_id,u32 arg1)359 static inline struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id,
360 u32 arg1)
361 {
362 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED, };
363
364 return tmp;
365 }
366
sip_hdcp_request_share_memory(int id)367 static inline void __iomem *sip_hdcp_request_share_memory(int id)
368 {
369 return NULL;
370 }
371
sip_hdcp_config(u32 arg0,u32 arg1,u32 arg2)372 static inline struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2)
373 {
374 struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
375
376 return tmp;
377 }
378
sip_cpu_logical_map_mpidr(u32 cpu)379 static inline ulong sip_cpu_logical_map_mpidr(u32 cpu) { return 0; }
380
381 /***************************fiq debugger **************************************/
sip_fiq_debugger_enable_fiq(bool enable,uint32_t tgt_cpu)382 static inline void sip_fiq_debugger_enable_fiq
383 (bool enable, uint32_t tgt_cpu) { return; }
384
sip_fiq_debugger_enable_debug(bool enable)385 static inline void sip_fiq_debugger_enable_debug(bool enable) { return; }
sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,sip_fiq_debugger_uart_irq_tf_cb_t callback_fn)386 static inline int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,
387 sip_fiq_debugger_uart_irq_tf_cb_t callback_fn)
388 {
389 return 0;
390 }
391
sip_fiq_debugger_set_print_port(u32 port_phyaddr,u32 baudrate)392 static inline int sip_fiq_debugger_set_print_port(u32 port_phyaddr,
393 u32 baudrate)
394 {
395 return 0;
396 }
397
sip_fiq_debugger_request_share_memory(void)398 static inline int sip_fiq_debugger_request_share_memory(void) { return 0; }
sip_fiq_debugger_get_target_cpu(void)399 static inline int sip_fiq_debugger_get_target_cpu(void) { return 0; }
sip_fiq_debugger_switch_cpu(u32 cpu)400 static inline int sip_fiq_debugger_switch_cpu(u32 cpu) { return 0; }
sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu,u32 target_cpu,u32 flag)401 static inline int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu,
402 u32 flag) { return 0; }
sip_fiq_debugger_is_enabled(void)403 static inline int sip_fiq_debugger_is_enabled(void) { return 0; }
sip_fiq_debugger_sdei_get_event_id(u32 * fiq,u32 * sw_cpu,u32 * flag)404 static inline int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag)
405 {
406 return SIP_RET_NOT_SUPPORTED;
407 }
408
sip_fiq_control(u32 sub_func,u32 irq,unsigned long data)409 static inline int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data)
410 {
411 return 0;
412 }
413
sip_wdt_config(u32 sub_func,u32 arg1,u32 arg2,u32 arg3)414 static inline int sip_wdt_config(u32 sub_func,
415 u32 arg1,
416 u32 arg2,
417 u32 arg3)
418 {
419 return 0;
420 }
421
sip_hdmirx_config(u32 sub_func,u32 arg1,u32 arg2,u32 arg3)422 static inline int sip_hdmirx_config(u32 sub_func,
423 u32 arg1,
424 u32 arg2,
425 u32 arg3)
426 {
427 return SIP_RET_NOT_SUPPORTED;
428 }
429
sip_hdcpkey_init(u32 hdcp_id)430 static inline int sip_hdcpkey_init(u32 hdcp_id)
431 {
432 return 0;
433 }
434
sip_smc_mcu_config(unsigned long mcu_id,unsigned long func,unsigned long arg2)435 static inline int sip_smc_mcu_config(unsigned long mcu_id,
436 unsigned long func,
437 unsigned long arg2)
438 {
439 return SIP_RET_NOT_SUPPORTED;
440 }
441 #endif
442
443 /* 32-bit OP-TEE context, never change order of members! */
444 struct sm_nsec_ctx {
445 u32 usr_sp;
446 u32 usr_lr;
447 u32 irq_spsr;
448 u32 irq_sp;
449 u32 irq_lr;
450 u32 fiq_spsr;
451 u32 fiq_sp;
452 u32 fiq_lr;
453 u32 svc_spsr;
454 u32 svc_sp;
455 u32 svc_lr;
456 u32 abt_spsr;
457 u32 abt_sp;
458 u32 abt_lr;
459 u32 und_spsr;
460 u32 und_sp;
461 u32 und_lr;
462 u32 mon_lr;
463 u32 mon_spsr;
464 u32 r4;
465 u32 r5;
466 u32 r6;
467 u32 r7;
468 u32 r8;
469 u32 r9;
470 u32 r10;
471 u32 r11;
472 u32 r12;
473 u32 r0;
474 u32 r1;
475 u32 r2;
476 u32 r3;
477 };
478
479 /* 64-bit ATF context, never change order of members! */
480 struct gp_regs_ctx {
481 u64 x0;
482 u64 x1;
483 u64 x2;
484 u64 x3;
485 u64 x4;
486 u64 x5;
487 u64 x6;
488 u64 x7;
489 u64 x8;
490 u64 x9;
491 u64 x10;
492 u64 x11;
493 u64 x12;
494 u64 x13;
495 u64 x14;
496 u64 x15;
497 u64 x16;
498 u64 x17;
499 u64 x18;
500 u64 x19;
501 u64 x20;
502 u64 x21;
503 u64 x22;
504 u64 x23;
505 u64 x24;
506 u64 x25;
507 u64 x26;
508 u64 x27;
509 u64 x28;
510 u64 x29;
511 u64 lr;
512 u64 sp_el0;
513 u64 scr_el3;
514 u64 runtime_sp;
515 u64 spsr_el3;
516 u64 elr_el3;
517 };
518
519 #endif
520