1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #define CONFIG_CPU_SH7757 1 13 #define CONFIG_SH7757LCR 1 14 #define CONFIG_SH7757LCR_DDR_ECC 1 15 16 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 #undef CONFIG_SHOW_BOOT_PROGRESS 20 21 /* MEMORY */ 22 #define SH7757LCR_SDRAM_BASE (0x80000000) 23 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 24 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 25 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 26 27 #define CONFIG_SYS_LONGHELP 28 #define CONFIG_SYS_PBSIZE 256 29 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 30 31 /* SCIF */ 32 #define CONFIG_CONS_SCIF2 1 33 34 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 35 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 36 224 * 1024 * 1024) 37 #undef CONFIG_SYS_ALT_MEMTEST 38 #undef CONFIG_SYS_MEMTEST_SCRATCH 39 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 40 41 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 42 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 43 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 44 (128 + 16) * 1024 * 1024) 45 46 #define CONFIG_SYS_MONITOR_BASE 0x00000000 47 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 48 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 49 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 50 51 /* Ether */ 52 #define CONFIG_SH_ETHER 1 53 #define CONFIG_SH_ETHER_USE_PORT 0 54 #define CONFIG_SH_ETHER_PHY_ADDR 1 55 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 56 #define CONFIG_BITBANGMII 57 #define CONFIG_BITBANGMII_MULTI 58 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 59 60 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 61 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 62 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 63 #define SH7757LCR_ETHERNET_MAC_SIZE 17 64 #define SH7757LCR_ETHERNET_NUM_CH 2 65 66 /* Gigabit Ether */ 67 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 68 69 /* SPI */ 70 #define CONFIG_SH_SPI_BASE 0xfe002000 71 72 /* MMCIF */ 73 #define CONFIG_SH_MMCIF 1 74 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 75 #define CONFIG_SH_MMCIF_CLK 48000000 76 77 /* SH7757 board */ 78 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 79 #define SH7757LCR_GRA_OFFSET 0x1f000000 80 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 81 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 82 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 83 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 84 85 /* ENV setting */ 86 #define CONFIG_ENV_IS_EMBEDDED 87 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 88 #define CONFIG_ENV_ADDR (0x00080000) 89 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 90 #define CONFIG_ENV_OVERWRITE 1 91 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 92 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 93 #define CONFIG_EXTRA_ENV_SETTINGS \ 94 "netboot=bootp; bootm\0" 95 96 /* Board Clock */ 97 #define CONFIG_SYS_CLK_FREQ 48000000 98 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 99 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 100 #define CONFIG_SYS_TMU_CLK_DIV 4 101 #endif /* __SH7757LCR_H */ 102