1 /* 2 * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/rotpk/rotpk_def.h> 14 #include <plat/arm/board/common/v2m_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/common/smccc_def.h> 17 #include <plat/common/common_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 20 /* Special value used to verify platform parameters from BL2 to BL31 */ 21 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 22 23 /* PL011 UART related constants */ 24 #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ 25 #undef V2M_IOFPGA_UART0_CLK_IN_HZ 26 #endif 27 28 #ifdef V2M_IOFPGA_UART1_CLK_IN_HZ 29 #undef V2M_IOFPGA_UART1_CLK_IN_HZ 30 #endif 31 32 #define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 33 #define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 34 35 /* Core/Cluster/Thread counts for corstone1000 */ 36 #define CORSTONE1000_CLUSTER_COUNT U(1) 37 #define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4) 38 #define CORSTONE1000_MAX_PE_PER_CPU U(1) 39 #define CORSTONE1000_PRIMARY_CPU U(0) 40 41 #define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT 42 43 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 44 CORSTONE1000_MAX_CPUS_PER_CLUSTER * \ 45 CORSTONE1000_MAX_PE_PER_CPU) 46 47 /* UART related constants */ 48 #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 49 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 50 #define PLAT_ARM_RUN_UART_BASE 0x1a520000 51 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 52 #define ARM_CONSOLE_BAUDRATE 115200 53 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 54 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 55 56 /* Memory related constants */ 57 58 /* Memory mappings of where the BLs in the FIP are copied to 59 * 60 * <ARM_TRUSTED_SRAM_BASE> = 0x02000000 61 * partition size: sizeof(meminfo_t) = 16 bytes 62 * content: memory info area used by the next BL 63 * 64 * <ARM_FW_CONFIG_BASE> = 0x02000010 65 * partition size: 4080 bytes 66 * 67 * <ARM_BL2_MEM_DESC_BASE> = 0x02001000 68 * partition size: 4 KB 69 * content: Area where BL2 copies the images descriptors 70 * 71 * <ARM_BL_RAM_BASE> = <BL32_BASE> = 0x02002000 72 * partition size: 3752 KB 73 * content: BL32 (optee-os) 74 * 75 * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x023AC000 76 * partition size: 8 KB 77 * content: BL32 config (TOS_FW_CONFIG) 78 * 79 * <BL31_BASE> = 0x023AE000 80 * partition size: 140 KB 81 * content: BL31 82 * 83 * <BL2_SIGNATURE_BASE> = 0x023D1000 84 * partition size: 4 KB 85 * content: MCUBOOT data needed to verify TF-A BL2 86 * 87 * <BL2_BASE> = 0x023D2000 88 * partition size: 176 KB 89 * content: BL2 90 * 91 * <BL33_BASE> = 0x80000000 92 * partition size: 12 MB 93 * content: BL33 (U-Boot) 94 */ 95 96 /* DDR memory */ 97 #define ARM_DRAM1_BASE UL(0x80000000) 98 #define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/ 99 #define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1) 100 101 /* DRAM1 and DRAM2 are the same for corstone1000 */ 102 #define ARM_DRAM2_BASE ARM_DRAM1_BASE 103 #define ARM_DRAM2_SIZE ARM_DRAM1_SIZE 104 #define ARM_DRAM2_END ARM_DRAM1_END 105 106 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 107 #define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE 108 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1) 109 110 /* The first 8 KB of Trusted SRAM are used as shared memory */ 111 #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) 112 #define ARM_SHARED_RAM_SIZE (SZ_8K) /* 8 KB */ 113 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 114 115 /* The remaining Trusted SRAM is used to load the BL images */ 116 #define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */ 117 118 119 #define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \ 120 ARM_SHARED_RAM_SIZE) 121 122 #define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */ 123 124 #define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */ 125 126 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) 127 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 128 ARM_SHARED_RAM_SIZE) 129 130 #define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */ 131 132 #define BL2_SIGNATURE_BASE (BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE) 133 #define BL2_BASE (BL2_LIMIT - \ 134 PLAT_ARM_MAX_BL2_SIZE + \ 135 BL2_SIGNATURE_SIZE) 136 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 137 138 #define BL31_BASE (BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE) 139 #define BL31_LIMIT BL2_SIGNATURE_BASE 140 141 #define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \ 142 CORSTONE1000_TOS_FW_CONFIG_SIZE) 143 #define CORSTONE1000_TOS_FW_CONFIG_SIZE (SZ_8K) /* 8 KB */ 144 #define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE 145 146 #define BL32_BASE ARM_BL_RAM_BASE 147 #define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE) 148 149 #define BL32_LIMIT (BL32_BASE + PLAT_ARM_MAX_BL32_SIZE) 150 151 /* SPD_spmd settings */ 152 153 #define PLAT_ARM_SPMC_BASE BL32_BASE 154 #define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE 155 156 /* NS memory */ 157 158 #define BL33_BASE ARM_DRAM1_BASE 159 #define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/ 160 #define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE) 161 162 /* end of the definition of SRAM memory layout */ 163 164 /* NOR Flash */ 165 166 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 167 #define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ 168 #define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ 169 #define PLAT_ARM_FLASH_IMAGE_BASE UL(0x08000000) 170 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE 171 172 /* FIP Information */ 173 #define FIP_SIGNATURE_AREA_SIZE (0x1000) /* 4 KB */ 174 175 /* 176 * Some data must be aligned on the biggest cache line size in the platform. 177 * This is known only to the platform as it might have a combination of 178 * integrated and external caches. 179 */ 180 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 181 #define ARM_CACHE_WRITEBACK_SHIFT 6 182 183 /* 184 * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. 185 * FW_CONFIG is intended to host the device tree. Currently, This area is not 186 * used because corstone1000 platform doesn't use a device tree at TF-A level. 187 */ 188 #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t)) 189 #define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \ 190 (ARM_SHARED_RAM_SIZE >> 1)) 191 192 /* 193 * Boot parameters passed from BL2 to BL31/BL32 are stored here 194 */ 195 #define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT 196 #define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE 197 198 /* 199 * The max number of regions like RO(code), coherent and data required by 200 * different BL stages which need to be mapped in the MMU. 201 */ 202 #define ARM_BL_REGIONS 3 203 #define PLAT_ARM_MMAP_ENTRIES 8 204 #define MAX_XLAT_TABLES 5 205 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) 206 #define MAX_IO_DEVICES 2 207 #define MAX_IO_HANDLES 3 208 #define MAX_IO_BLOCK_DEVICES 1 209 210 /* GIC related constants */ 211 #define PLAT_ARM_GICD_BASE 0x1C010000 212 #define PLAT_ARM_GICC_BASE 0x1C02F000 213 214 /* MHUv2 Secure Channel receiver and sender */ 215 #define PLAT_SDK700_MHU0_SEND 0x1B800000 216 #define PLAT_SDK700_MHU0_RECV 0x1B810000 217 218 /* Timer/watchdog related constants */ 219 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) 220 #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) 221 #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) 222 223 #define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000 224 #define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008 225 #define SECURE_WATCHDOG_MASK_ENABLE 0x01 226 #define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000 227 228 #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ 229 230 #define CORSTONE1000_IRQ_TZ_WDOG 32 231 #define CORSTONE1000_IRQ_SEC_SYS_TIMER 34 232 233 #define PLAT_MAX_PWR_LVL 2 234 /* 235 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 236 * power levels have a 1:1 mapping with the MPIDR affinity levels. 237 */ 238 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 239 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 240 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 241 242 /* 243 * Macros for local power states in ARM platforms encoded by State-ID field 244 * within the power-state parameter. 245 */ 246 /* Local power state for power domains in Run state. */ 247 #define ARM_LOCAL_STATE_RUN U(0) 248 /* Local power state for retention. Valid only for CPU power domains */ 249 #define ARM_LOCAL_STATE_RET U(1) 250 /* Local power state for OFF/power-down. Valid for CPU and cluster 251 * power domains 252 */ 253 #define ARM_LOCAL_STATE_OFF U(2) 254 255 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 256 257 #if defined(CORSTONE1000_FVP_MULTICORE) 258 /* The secondary core entrypoint address points to bl31_warm_entrypoint 259 * and the address size is 8 bytes */ 260 #define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8) 261 262 #define CORSTONE1000_SECONDARY_CORE_HOLD_BASE (PLAT_ARM_TRUSTED_MAILBOX_BASE + \ 263 CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE) 264 #define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0) 265 #define CORSTONE1000_SECONDARY_CORE_STATE_GO ULL(1) 266 #define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3) 267 #endif 268 269 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 270 271 #define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE) 272 273 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 274 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 275 276 /* 277 * This macro defines the deepest retention state possible. A higher state 278 * ID will represent an invalid or a power down state. 279 */ 280 #define PLAT_MAX_RET_STATE 1 281 282 /* 283 * This macro defines the deepest power down states possible. Any state ID 284 * higher than this is invalid. 285 */ 286 #define PLAT_MAX_OFF_STATE 2 287 288 #define PLATFORM_STACK_SIZE UL(0x440) 289 290 #define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \ 291 PLAT_ARM_NVM_BASE, \ 292 PLAT_ARM_NVM_SIZE, \ 293 MT_DEVICE | MT_RO | MT_SECURE) 294 295 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 296 ARM_SHARED_RAM_BASE, \ 297 ARM_SHARED_RAM_SIZE, \ 298 MT_MEMORY | MT_RW | MT_SECURE) 299 300 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 301 ARM_NS_DRAM1_BASE, \ 302 ARM_NS_DRAM1_SIZE, \ 303 MT_MEMORY | MT_RW | MT_NS) 304 305 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 306 BL_CODE_BASE, \ 307 (BL_CODE_END - BL_CODE_BASE), \ 308 MT_CODE | MT_SECURE), \ 309 MAP_REGION_FLAT( \ 310 BL_RO_DATA_BASE, \ 311 (BL_RO_DATA_END - BL_RO_DATA_BASE), \ 312 MT_RO_DATA | MT_SECURE) 313 #if USE_COHERENT_MEM 314 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 315 BL_COHERENT_RAM_BASE, \ 316 (BL_COHERENT_RAM_END \ 317 - BL_COHERENT_RAM_BASE), \ 318 MT_DEVICE | MT_RW | MT_SECURE) 319 #endif 320 321 /* 322 * Map the region for the optional device tree configuration with read and 323 * write permissions 324 */ 325 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ 326 ARM_FW_CONFIG_BASE, \ 327 (ARM_FW_CONFIG_LIMIT \ 328 - ARM_FW_CONFIG_BASE), \ 329 MT_MEMORY | MT_RW | MT_SECURE) 330 331 #define CORSTONE1000_DEVICE_BASE (0x1A000000) 332 #define CORSTONE1000_DEVICE_SIZE (0x26000000) 333 #define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \ 334 CORSTONE1000_DEVICE_BASE, \ 335 CORSTONE1000_DEVICE_SIZE, \ 336 MT_DEVICE | MT_RW | MT_SECURE) 337 338 #define ARM_IRQ_SEC_PHY_TIMER 29 339 340 #define ARM_IRQ_SEC_SGI_0 8 341 #define ARM_IRQ_SEC_SGI_1 9 342 #define ARM_IRQ_SEC_SGI_2 10 343 #define ARM_IRQ_SEC_SGI_3 11 344 #define ARM_IRQ_SEC_SGI_4 12 345 #define ARM_IRQ_SEC_SGI_5 13 346 #define ARM_IRQ_SEC_SGI_6 14 347 #define ARM_IRQ_SEC_SGI_7 15 348 349 /* 350 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 351 * terminology. On a GICv2 system or mode, the lists will be merged and treated 352 * as Group 0 interrupts. 353 */ 354 #define ARM_G1S_IRQ_PROPS(grp) \ 355 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 356 (grp), GIC_INTR_CFG_LEVEL), \ 357 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 358 (grp), GIC_INTR_CFG_EDGE), \ 359 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 360 (grp), GIC_INTR_CFG_EDGE), \ 361 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 362 (grp), GIC_INTR_CFG_EDGE), \ 363 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 364 (grp), GIC_INTR_CFG_EDGE), \ 365 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 366 (grp), GIC_INTR_CFG_EDGE), \ 367 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 368 (grp), GIC_INTR_CFG_EDGE) 369 370 #define ARM_G0_IRQ_PROPS(grp) \ 371 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 372 GIC_INTR_CFG_EDGE) 373 374 /* 375 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 376 * terminology. On a GICv2 system or mode, the lists will be merged and treated 377 * as Group 0 interrupts. 378 */ 379 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 380 ARM_G1S_IRQ_PROPS(grp), \ 381 INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, \ 382 GIC_HIGHEST_SEC_PRIORITY, \ 383 (grp), GIC_INTR_CFG_LEVEL), \ 384 INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \ 385 GIC_HIGHEST_SEC_PRIORITY, \ 386 (grp), GIC_INTR_CFG_LEVEL) 387 388 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 389 390 #endif /* PLATFORM_DEF_H */ 391