1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2026, BayLibre SAS 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/tbbr/tbbr_img_def.h> 13 #include <lib/utils_def.h> 14 #include <plat/common/common_def.h> 15 16 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 17 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 18 19 #define PLATFORM_STACK_SIZE 0x1000 20 21 #if ARM_ARCH_MAJOR == 7 22 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 23 #define PLATFORM_CLUSTER_COUNT U(1) 24 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 25 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 26 #else 27 /* 28 * Define the number of cores per cluster used in calculating core position. 29 * The cluster number is shifted by this value and added to the core ID, 30 * so its value represents log2(cores/cluster). 31 * Default is 2**(4) = 16 cores per cluster. 32 */ 33 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(4) 34 #define PLATFORM_MAX_CPUS_PER_CLUSTER (U(1) << PLATFORM_CPU_PER_CLUSTER_SHIFT) 35 #define PLATFORM_CLUSTER_COUNT U(2) 36 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 37 #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 38 #endif 39 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 40 PLATFORM_CLUSTER1_CORE_COUNT) 41 42 #define QEMU_PRIMARY_CPU U(0) 43 44 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 45 PLATFORM_CORE_COUNT) 46 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 47 48 #define PLAT_MAX_RET_STATE U(1) 49 #define PLAT_MAX_OFF_STATE U(2) 50 51 /* Local power state for power domains in Run state. */ 52 #define PLAT_LOCAL_STATE_RUN U(0) 53 /* Local power state for retention. Valid only for CPU power domains */ 54 #define PLAT_LOCAL_STATE_RET U(1) 55 /* 56 * Local power state for OFF/power-down. Valid for CPU and cluster power 57 * domains. 58 */ 59 #define PLAT_LOCAL_STATE_OFF 2 60 61 /* 62 * Macros used to parse state information from State-ID if it is using the 63 * recommended encoding for State-ID. 64 */ 65 #define PLAT_LOCAL_PSTATE_WIDTH 4 66 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 67 68 /* 69 * Some data must be aligned on the biggest cache line size in the platform. 70 * This is known only to the platform as it might have a combination of 71 * integrated and external caches. 72 */ 73 #define CACHE_WRITEBACK_SHIFT 6 74 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 75 76 /* 77 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 78 * and secure DRAM. 79 */ 80 #define SEC_ROM_BASE 0x00000000 81 #define SEC_ROM_SIZE 0x00020000 82 83 #define NS_DRAM0_BASE ULL(0x40000000) 84 #define NS_DRAM0_SIZE ULL(0xc0000000) 85 86 #define SEC_SRAM_BASE 0x0e000000 87 #define SEC_SRAM_SIZE 0x00100000 88 89 #define SEC_DRAM_BASE 0x0e100000 90 #define SEC_DRAM_SIZE 0x00f00000 91 92 #define SECURE_GPIO_BASE 0x090b0000 93 #define SECURE_GPIO_SIZE 0x00001000 94 #define SECURE_GPIO_POWEROFF 0 95 #define SECURE_GPIO_RESET 1 96 97 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 98 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 99 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 100 101 /* 102 * ARM-TF lives in SRAM, partition it here 103 */ 104 105 #define SHARED_RAM_BASE SEC_SRAM_BASE 106 #define SHARED_RAM_SIZE 0x00001000 107 108 #define PLAT_QEMU_HOLD_BASE SHARED_RAM_BASE 109 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * HOLD_SLOT_SIZE) 110 111 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 112 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 113 114 #define TB_FW_CONFIG_BASE BL_RAM_BASE 115 #define TB_FW_CONFIG_LIMIT (TB_FW_CONFIG_BASE + PAGE_SIZE) 116 #define TOS_FW_CONFIG_BASE TB_FW_CONFIG_LIMIT 117 #define TOS_FW_CONFIG_LIMIT (TOS_FW_CONFIG_BASE + PAGE_SIZE) 118 119 /* 120 * BL1 specific defines. 121 * 122 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 123 * addresses. 124 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 125 * the current BL1 RW debug size plus a little space for growth. 126 */ 127 #define BL1_RO_BASE SEC_ROM_BASE 128 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 129 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) 130 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 131 132 /* 133 * BL2 specific defines. 134 * 135 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 136 * size plus a little space for growth. 137 */ 138 #define BL2_BASE (BL31_BASE - 0x35000) 139 #define BL2_LIMIT BL31_BASE 140 141 /* 142 * BL3-1 specific defines. 143 * 144 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 145 * current BL3-1 debug size plus a little space for growth. 146 */ 147 #define BL31_BASE (BL31_LIMIT - 0x70000) 148 #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - FW_HANDOFF_SIZE) 149 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 150 151 #if TRANSFER_LIST 152 #define FW_HANDOFF_BASE BL31_LIMIT 153 #define FW_HANDOFF_LIMIT (FW_HANDOFF_BASE + FW_HANDOFF_SIZE) 154 #define FW_HANDOFF_SIZE 0x8000 155 #else 156 #define FW_HANDOFF_SIZE 0 157 #endif 158 159 160 /* 161 * BL3-2 specific defines. 162 * 163 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 164 */ 165 #define BL32_SRAM_BASE BL_RAM_BASE 166 #define BL32_SRAM_LIMIT BL31_BASE 167 #define BL32_DRAM_BASE SEC_DRAM_BASE 168 #define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE - \ 169 RME_GPT_DRAM_SIZE) 170 171 #define SEC_SRAM_ID 0 172 #define SEC_DRAM_ID 1 173 174 #if BL32_RAM_LOCATION_ID == SEC_SRAM_ID 175 # define BL32_MEM_BASE BL_RAM_BASE 176 # define BL32_MEM_SIZE BL_RAM_SIZE 177 # define BL32_BASE BL32_SRAM_BASE 178 # define BL32_LIMIT (BL32_SRAM_LIMIT - FW_HANDOFF_SIZE) 179 #elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID 180 # define BL32_MEM_BASE SEC_DRAM_BASE 181 # define BL32_MEM_SIZE (SEC_DRAM_SIZE - RME_GPT_DRAM_SIZE) 182 # define BL32_BASE BL32_DRAM_BASE 183 # define BL32_LIMIT (BL32_DRAM_LIMIT - FW_HANDOFF_SIZE) 184 #else 185 # error "Unsupported BL32_RAM_LOCATION_ID value" 186 #endif 187 188 #if TRANSFER_LIST 189 #define FW_NS_HANDOFF_BASE (NS_IMAGE_OFFSET - FW_HANDOFF_SIZE) 190 #endif 191 192 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 193 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 194 195 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 196 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 197 #define MAX_MMAP_REGIONS (13 + MAX_MMAP_REGIONS_SPMC) 198 #define MAX_XLAT_TABLES (6 + MAX_XLAT_TABLES_SPMC) 199 #define MAX_IO_DEVICES 4 200 #define MAX_IO_HANDLES 4 201 202 /* 203 * PL011 related constants 204 */ 205 #define UART0_BASE 0x09000000 206 #define UART1_BASE 0x09040000 207 #define UART0_CLK_IN_HZ 1 208 #define UART1_CLK_IN_HZ 1 209 210 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 211 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 212 213 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 214 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 215 216 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 217 218 #define QEMU_FLASH0_BASE 0x00000000 219 #define QEMU_FLASH0_SIZE 0x04000000 220 #define QEMU_FLASH1_BASE 0x04000000 221 #define QEMU_FLASH1_SIZE 0x04000000 222 223 #define PLAT_QEMU_FIP_BASE 0x00040000 224 #define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - PLAT_QEMU_FIP_BASE) 225 226 #define DEVICE0_BASE 0x08000000 227 #define DEVICE0_SIZE 0x01000000 228 #define DEVICE1_BASE 0x09000000 229 #define DEVICE1_SIZE 0x00c00000 230 231 /* 232 * GIC related constants 233 */ 234 235 #define GICD_BASE 0x8000000 236 #define GICC_BASE 0x8010000 237 #define GICR_BASE 0x80A0000 238 239 240 #define QEMU_IRQ_SEC_SGI_0 8 241 #define QEMU_IRQ_SEC_SGI_1 9 242 #define QEMU_IRQ_SEC_SGI_2 10 243 #define QEMU_IRQ_SEC_SGI_3 11 244 #define QEMU_IRQ_SEC_SGI_4 12 245 #define QEMU_IRQ_SEC_SGI_5 13 246 #define QEMU_IRQ_SEC_SGI_6 14 247 #define QEMU_IRQ_SEC_SGI_7 15 248 249 /****************************************************************************** 250 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 251 * interrupts. 252 *****************************************************************************/ 253 #define PLATFORM_G1S_PROPS(grp) \ 254 DESC_G1S_IRQ_SEC_SGI_0(grp) \ 255 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 256 grp, GIC_INTR_CFG_EDGE), \ 257 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 258 grp, GIC_INTR_CFG_EDGE), \ 259 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 260 grp, GIC_INTR_CFG_EDGE), \ 261 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 262 grp, GIC_INTR_CFG_EDGE), \ 263 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 264 grp, GIC_INTR_CFG_EDGE), \ 265 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 266 grp, GIC_INTR_CFG_EDGE), \ 267 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 268 grp, GIC_INTR_CFG_EDGE) 269 270 #if SDEI_SUPPORT 271 #define DESC_G0_IRQ_SEC_SGI(grp) \ 272 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 273 GIC_INTR_CFG_EDGE) 274 #define DESC_G1S_IRQ_SEC_SGI_0(grp) 275 #else 276 #define DESC_G0_IRQ_SEC_SGI(grp) 277 #define DESC_G1S_IRQ_SEC_SGI_0(grp) \ 278 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 279 GIC_INTR_CFG_EDGE), 280 #endif 281 282 #define PLATFORM_G0_PROPS(grp) DESC_G0_IRQ_SEC_SGI(grp) 283 284 /* 285 * DT related constants 286 */ 287 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 288 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 289 290 /* 291 * Platforms macros to support SDEI 292 */ 293 #define PLAT_PRI_BITS U(3) 294 #define PLAT_SDEI_CRITICAL_PRI 0x60 295 #define PLAT_SDEI_NORMAL_PRI 0x70 296 #define PLAT_SDEI_SGI_PRIVATE QEMU_IRQ_SEC_SGI_0 297 298 /* 299 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 300 */ 301 #define PLAT_EVENT_LOG_MAX_SIZE UL(0x800) 302 303 #if SPMC_AT_EL3 304 /* 305 * Number of Secure Partitions supported. 306 * SPMC at EL3, uses this count to configure the maximum number of 307 * supported secure partitions. 308 */ 309 #define SECURE_PARTITION_COUNT 1 310 311 /* 312 * Number of Logical Partitions supported. 313 * SPMC at EL3, uses this count to configure the maximum number of 314 * supported logical partitions. 315 */ 316 #define MAX_EL3_LP_DESCS_COUNT 0 317 318 /* 319 * Number of Normal World Partitions supported. 320 * SPMC at EL3, uses this count to configure the maximum number of 321 * supported normal world partitions. 322 */ 323 #define NS_PARTITION_COUNT 1 324 325 #define MAX_MMAP_REGIONS_SPMC 2 326 #define MAX_XLAT_TABLES_SPMC 4 327 #else 328 #define MAX_MMAP_REGIONS_SPMC 0 329 #define MAX_XLAT_TABLES_SPMC 0 330 #endif 331 332 #if ENABLE_FEAT_RME 333 334 /* 335 * Reserve some space at the end of secure DRAM for the Granule Protection 336 * Tables 337 */ 338 #define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \ 339 PLAT_QEMU_L0_GPT_SIZE) 340 #define PLAT_QEMU_L0_GPT_SIZE SZ_8K 341 342 #define PLAT_QEMU_L1_GPT_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \ 343 PLAT_QEMU_L1_GPT_SIZE) 344 #define PLAT_QEMU_L1_GPT_SIZE SZ_1M 345 346 #define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE 347 #define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \ 348 PLAT_QEMU_L0_GPT_SIZE) 349 350 #ifndef __ASSEMBLER__ 351 /* L0 table greater than 4KB must be naturally aligned */ 352 CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0, 353 assert_l0_gpt_naturally_aligned); 354 #endif 355 356 /* Reserved some DRAM space for RMM (24MB) */ 357 #if ENABLE_RMM 358 #define REALM_DRAM_BASE (NS_DRAM0_BASE + PLAT_QEMU_DT_MAX_SIZE) 359 #define REALM_DRAM_SIZE 0x01800000 360 361 #define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE) 362 #define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 363 364 #define RMM_BASE (REALM_DRAM_BASE) 365 #define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE) 366 #define RMM_SHARED_BASE (RMM_LIMIT) 367 #define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE 368 369 /* 370 * We add the RMM_SHARED size to RMM mapping to map the region as a block. 371 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 372 */ 373 #define MAP_RMM_DRAM MAP_REGION_FLAT( \ 374 RMM_BASE, \ 375 (PLAT_QEMU_RMM_SIZE + \ 376 RMM_SHARED_SIZE), \ 377 MT_MEMORY | MT_RW | MT_REALM) 378 379 #define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \ 380 RMM_SHARED_BASE, \ 381 RMM_SHARED_SIZE, \ 382 MT_MEMORY | MT_RW | MT_REALM) 383 #endif /* ENABLE_RMM */ 384 385 #define MAP_GPT_L0_REGION MAP_REGION_FLAT( \ 386 PLAT_QEMU_L0_GPT_BASE, \ 387 PLAT_QEMU_L0_GPT_SIZE, \ 388 MT_MEMORY | MT_RW | EL3_PAS) 389 390 #define MAP_GPT_L1_REGION MAP_REGION_FLAT( \ 391 PLAT_QEMU_L1_GPT_BASE, \ 392 PLAT_QEMU_L1_GPT_SIZE, \ 393 MT_MEMORY | MT_RW | EL3_PAS) 394 #else /* !ENABLE_FEAT_RME */ 395 396 #define RME_GPT_DRAM_SIZE 0 397 398 #endif /* ENABLE_FEAT_RME */ 399 400 #endif /* PLATFORM_DEF_H */ 401