1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Joseph Chen <chenjh@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3528_H 8 #define _ASM_ARCH_CRU_RK3528_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define CPU_PVTPLL_HZ (1200 * MHz) 15 #define APLL_HZ (600 * MHz) 16 #define GPLL_HZ (1188 * MHz) 17 #define CPLL_HZ (996 * MHz) 18 #define PPLL_HZ (1000 * MHz) 19 20 /* RK3528 pll id */ 21 enum rk3528_pll_id { 22 APLL, 23 CPLL, 24 GPLL, 25 PPLL, 26 DPLL, 27 PLL_COUNT, 28 }; 29 30 struct rk3528_clk_info { 31 unsigned long id; 32 char *name; 33 }; 34 35 struct rk3528_clk_priv { 36 struct rk3528_cru *cru; 37 struct rk3528_sysgrf *grf; 38 ulong ppll_hz; 39 ulong gpll_hz; 40 ulong cpll_hz; 41 ulong armclk_hz; 42 ulong armclk_enter_hz; 43 ulong armclk_init_hz; 44 bool sync_kernel; 45 bool set_armclk_rate; 46 }; 47 48 struct rk3528_pll { 49 unsigned int con0; 50 unsigned int con1; 51 unsigned int con2; 52 unsigned int con3; 53 unsigned int con4; 54 unsigned int reserved0[3]; 55 }; 56 57 struct rk3528_cru { 58 uint32_t apll_con[5]; 59 uint32_t reserved0014[3]; 60 uint32_t cpll_con[5]; 61 uint32_t reserved0034[11]; 62 uint32_t gpll_con[5]; 63 uint32_t reserved0074[51+32]; 64 uint32_t reserved01c0[48]; 65 uint32_t mode_con[1]; 66 uint32_t reserved0284[31]; 67 uint32_t clksel_con[91]; 68 uint32_t reserved046c[229]; 69 uint32_t gate_con[46]; 70 uint32_t reserved08b8[82]; 71 uint32_t softrst_con[47]; 72 uint32_t reserved0abc[81]; 73 uint32_t glb_cnt_th; 74 uint32_t glb_rst_st; 75 uint32_t glb_srst_fst; 76 uint32_t glb_srst_snd; 77 uint32_t glb_rst_con; 78 uint32_t reserved0c14[6]; 79 uint32_t corewfi_con; 80 uint32_t reserved0c30[15604]; 81 82 /* pmucru */ 83 uint32_t reserved10000[192]; 84 uint32_t pmuclksel_con[3]; 85 uint32_t reserved1030c[317]; 86 uint32_t pmugate_con[3]; 87 uint32_t reserved1080c[125]; 88 uint32_t pmusoftrst_con[3]; 89 uint32_t reserved10a08[7550+8191]; 90 91 /* pciecru */ 92 uint32_t reserved20000[32]; 93 uint32_t ppll_con[5]; 94 uint32_t reserved20094[155]; 95 uint32_t pcieclksel_con[2]; 96 uint32_t reserved20308[318]; 97 uint32_t pciegate_con; 98 }; 99 check_member(rk3528_cru, pciegate_con, 0x20800); 100 101 struct rk3528_grf_clk_priv { 102 struct rk3528_grf *grf; 103 }; 104 105 struct pll_rate_table { 106 unsigned long rate; 107 unsigned int fbdiv; 108 unsigned int postdiv1; 109 unsigned int refdiv; 110 unsigned int postdiv2; 111 unsigned int dsmpd; 112 unsigned int frac; 113 }; 114 115 #define RK3528_PMU_CRU_BASE 0x10000 116 #define RK3528_PCIE_CRU_BASE 0x20000 117 #define RK3528_DDRPHY_CRU_BASE 0x28000 118 #define RK3528_PLL_CON(x) ((x) * 0x4) 119 #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) 120 #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) 121 #define RK3528_MODE_CON 0x280 122 #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 123 #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) 124 #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) 125 #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) 126 127 #define RK3528_DIV_ACLK_M_CORE_MASK 0x1f 128 #define RK3528_DIV_ACLK_M_CORE_SHIFT 11 129 #define RK3528_DIV_PCLK_DBG_MASK 0x1f 130 #define RK3528_DIV_PCLK_DBG_SHIFT 1 131 132 enum { 133 /* CRU_CLKSEL_CON00 */ 134 CLK_MATRIX_50M_SRC_DIV_SHIFT = 2, 135 CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT, 136 CLK_MATRIX_100M_SRC_DIV_SHIFT = 7, 137 CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT, 138 139 /* CRU_CLKSEL_CON01 */ 140 CLK_MATRIX_150M_SRC_DIV_SHIFT = 0, 141 CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT, 142 CLK_MATRIX_200M_SRC_DIV_SHIFT = 5, 143 CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT, 144 CLK_MATRIX_250M_SRC_DIV_SHIFT = 10, 145 CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT, 146 CLK_MATRIX_250M_SRC_SEL_SHIFT = 15, 147 CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT, 148 149 /* CRU_CLKSEL_CON02 */ 150 CLK_MATRIX_300M_SRC_DIV_SHIFT = 0, 151 CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT, 152 CLK_MATRIX_339M_SRC_DIV_SHIFT = 5, 153 CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT, 154 CLK_MATRIX_400M_SRC_DIV_SHIFT = 10, 155 CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT, 156 157 /* CRU_CLKSEL_CON03 */ 158 CLK_MATRIX_500M_SRC_DIV_SHIFT = 6, 159 CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT, 160 CLK_MATRIX_500M_SRC_SEL_SHIFT = 11, 161 CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT, 162 163 /* CRU_CLKSEL_CON04 */ 164 CLK_MATRIX_600M_SRC_DIV_SHIFT = 0, 165 CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT, 166 CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U, 167 CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U, 168 CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U, 169 CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U, 170 171 /* PMUCRU_CLKSEL_CON00 */ 172 CLK_I2C2_SEL_SHIFT = 0, 173 CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 174 175 /* PCIE_CRU_CLKSEL_CON01 */ 176 PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7, 177 PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT, 178 PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11, 179 PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT, 180 181 /* CRU_CLKSEL_CON32 */ 182 DCLK_VOP_SRC0_SEL_SHIFT = 10, 183 DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT, 184 DCLK_VOP_SRC0_DIV_SHIFT = 2, 185 DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT, 186 187 /* CRU_CLKSEL_CON33 */ 188 DCLK_VOP_SRC1_SEL_SHIFT = 8, 189 DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT, 190 DCLK_VOP_SRC1_DIV_SHIFT = 0, 191 DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT, 192 193 /* CRU_CLKSEL_CON43 */ 194 CLK_CORE_CRYPTO_SEL_SHIFT = 14, 195 CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 196 ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U, 197 ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT, 198 199 /* CRU_CLKSEL_CON44 */ 200 CLK_PWM0_SEL_SHIFT = 6, 201 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, 202 CLK_PWM1_SEL_SHIFT = 8, 203 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 204 CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U, 205 CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U, 206 CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U, 207 CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U, 208 CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U, 209 CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U, 210 CLK_PKA_CRYPTO_SEL_SHIFT = 0, 211 CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 212 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, 213 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, 214 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, 215 CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, 216 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, 217 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, 218 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, 219 CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, 220 221 /* CRU_CLKSEL_CON60 */ 222 CLK_MATRIX_25M_SRC_DIV_SHIFT = 2, 223 CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT, 224 CLK_MATRIX_125M_SRC_DIV_SHIFT = 10, 225 CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT, 226 227 /* CRU_CLKSEL_CON61 */ 228 SCLK_SFC_DIV_SHIFT = 6, 229 SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT, 230 SCLK_SFC_SEL_SHIFT = 12, 231 SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, 232 SCLK_SFC_SEL_CLK_GPLL_MUX = 0U, 233 SCLK_SFC_SEL_CLK_CPLL_MUX = 1U, 234 SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U, 235 236 /* CRU_CLKSEL_CON62 */ 237 CCLK_SRC_EMMC_DIV_SHIFT = 0, 238 CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT, 239 CCLK_SRC_EMMC_SEL_SHIFT = 6, 240 CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT, 241 BCLK_EMMC_SEL_SHIFT = 8, 242 BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT, 243 244 /* CRU_CLKSEL_CON63 */ 245 CLK_I2C3_SEL_SHIFT = 12, 246 CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, 247 CLK_I2C5_SEL_SHIFT = 14, 248 CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT, 249 CLK_SPI1_SEL_SHIFT = 10, 250 CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 251 252 /* CRU_CLKSEL_CON64 */ 253 CLK_I2C6_SEL_SHIFT = 0, 254 CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT, 255 256 /* CRU_CLKSEL_CON74 */ 257 CLK_SARADC_DIV_SHIFT = 0, 258 CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, 259 CLK_TSADC_DIV_SHIFT = 3, 260 CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, 261 CLK_TSADC_TSEN_DIV_SHIFT = 8, 262 CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, 263 264 /* CRU_CLKSEL_CON79 */ 265 CLK_I2C1_SEL_SHIFT = 9, 266 CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, 267 CLK_I2C0_SEL_SHIFT = 11, 268 CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, 269 CLK_SPI0_SEL_SHIFT = 13, 270 CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 271 272 /* CRU_CLKSEL_CON83 */ 273 ACLK_VOP_ROOT_DIV_SHIFT = 12, 274 ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT, 275 ACLK_VOP_ROOT_SEL_SHIFT = 15, 276 ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT, 277 278 /* CRU_CLKSEL_CON84 */ 279 DCLK_VOP0_SEL_SHIFT = 0, 280 DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT, 281 DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U, 282 DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U, 283 ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U, 284 ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U, 285 DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U, 286 DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U, 287 288 /* CRU_CLKSEL_CON85 */ 289 CLK_I2C4_SEL_SHIFT = 13, 290 CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, 291 CLK_I2C7_SEL_SHIFT = 0, 292 CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT, 293 CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U, 294 CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U, 295 CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U, 296 CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U, 297 CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U, 298 CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U, 299 CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U, 300 CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U, 301 CCLK_SRC_SDMMC0_DIV_SHIFT = 0, 302 CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT, 303 CCLK_SRC_SDMMC0_SEL_SHIFT = 6, 304 CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT, 305 CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U, 306 CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U, 307 CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U, 308 BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U, 309 BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U, 310 BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U, 311 BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U, 312 CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U, 313 CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U, 314 CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U, 315 316 /* CRU_CLKSEL_CON04 */ 317 CLK_UART0_SRC_DIV_SHIFT = 5, 318 CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT, 319 /* CRU_CLKSEL_CON05 */ 320 CLK_UART0_FRAC_DIV_SHIFT = 0, 321 CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT, 322 /* CRU_CLKSEL_CON06 */ 323 SCLK_UART0_SRC_SEL_SHIFT = 0, 324 SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT, 325 CLK_UART1_SRC_DIV_SHIFT = 2, 326 CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT, 327 /* CRU_CLKSEL_CON07 */ 328 CLK_UART1_FRAC_DIV_SHIFT = 0, 329 CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT, 330 /* CRU_CLKSEL_CON08 */ 331 SCLK_UART1_SRC_SEL_SHIFT = 0, 332 SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT, 333 CLK_UART2_SRC_DIV_SHIFT = 2, 334 CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT, 335 /* CRU_CLKSEL_CON09 */ 336 CLK_UART2_FRAC_DIV_SHIFT = 0, 337 CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT, 338 /* CRU_CLKSEL_CON10 */ 339 SCLK_UART2_SRC_SEL_SHIFT = 0, 340 SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT, 341 CLK_UART3_SRC_DIV_SHIFT = 2, 342 CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT, 343 /* CRU_CLKSEL_CON11 */ 344 CLK_UART3_FRAC_DIV_SHIFT = 0, 345 CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT, 346 /* CRU_CLKSEL_CON12 */ 347 SCLK_UART3_SRC_SEL_SHIFT = 0, 348 SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT, 349 CLK_UART4_SRC_DIV_SHIFT = 2, 350 CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT, 351 /* CRU_CLKSEL_CON13 */ 352 CLK_UART4_FRAC_DIV_SHIFT = 0, 353 CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT, 354 /* CRU_CLKSEL_CON14 */ 355 SCLK_UART4_SRC_SEL_SHIFT = 0, 356 SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT, 357 CLK_UART5_SRC_DIV_SHIFT = 2, 358 CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT, 359 /* CRU_CLKSEL_CON15 */ 360 CLK_UART5_FRAC_DIV_SHIFT = 0, 361 CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT, 362 /* CRU_CLKSEL_CON16 */ 363 SCLK_UART5_SRC_SEL_SHIFT = 0, 364 SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT, 365 CLK_UART6_SRC_DIV_SHIFT = 2, 366 CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT, 367 /* CRU_CLKSEL_CON17 */ 368 CLK_UART6_FRAC_DIV_SHIFT = 0, 369 CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT, 370 /* CRU_CLKSEL_CON18 */ 371 SCLK_UART6_SRC_SEL_SHIFT = 0, 372 SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT, 373 CLK_UART7_SRC_DIV_SHIFT = 2, 374 CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT, 375 /* CRU_CLKSEL_CON19 */ 376 CLK_UART7_FRAC_DIV_SHIFT = 0, 377 CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT, 378 /* CRU_CLKSEL_CON20 */ 379 SCLK_UART7_SRC_SEL_SHIFT = 0, 380 SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT, 381 SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U, 382 SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U, 383 SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U, 384 385 /* CRU_CLKSEL_CON60 */ 386 CLK_GMAC1_VPU_25M_DIV_SHIFT = 2, 387 CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT, 388 /* CRU_CLKSEL_CON66 */ 389 CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0, 390 CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT, 391 /* CRU_CLKSEL_CON84 */ 392 CLK_GMAC0_SRC_DIV_SHIFT = 3, 393 CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT, 394 }; 395 396 #endif 397