1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ROCKCHIP_OTP_H_ 7 #define _ROCKCHIP_OTP_H_ 8 9 /* OTP Register Offsets */ 10 #define OTPC_SBPI_CTRL 0x0020 11 #define OTPC_SBPI_CMD_VALID_PRE 0x0024 12 #define OTPC_SBPI_CS_VALID_PRE 0x0028 13 #define OTPC_SBPI_STATUS 0x002C 14 #define OTPC_LOCK_CTRL 0x050 15 #define OTPC_USER_CTRL 0x0100 16 #define OTPC_USER_ADDR 0x0104 17 #define OTPC_USER_ENABLE 0x0108 18 #define OTPC_USER_QP 0x0120 19 #define OTPC_USER_Q 0x0124 20 #define OTPC_INT_STATUS 0x0304 21 #define OTPC_SBPI_CMD0_OFFSET 0x1000 22 #define OTPC_SBPI_CMD1_OFFSET 0x1004 23 24 /* OTP Register bits and masks */ 25 #define OTPC_USER_ADDR_MASK GENMASK(31, 16) 26 #define OTPC_USE_USER BIT(0) 27 #define OTPC_USE_USER_MASK GENMASK(16, 16) 28 #define OTPC_USER_FSM_ENABLE BIT(0) 29 #define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16) 30 #define OTPC_SBPI_DONE BIT(1) 31 #define OTPC_USER_DONE BIT(2) 32 33 #define SBPI_DAP_ADDR 0x02 34 #define SBPI_DAP_ADDR_SHIFT 8 35 #define SBPI_DAP_ADDR_MASK GENMASK(31, 24) 36 #define SBPI_CMD_VALID_MASK GENMASK(31, 16) 37 #define SBPI_DAP_CMD_WRF 0xC0 38 #define SBPI_DAP_REG_ECC 0x3A 39 #define SBPI_ECC_ENABLE 0x00 40 #define SBPI_ECC_DISABLE 0x09 41 #define SBPI_ENABLE BIT(0) 42 #define SBPI_ENABLE_MASK GENMASK(16, 16) 43 44 #define OTPC_TIMEOUT 10000 45 46 #define OTPC_MODE_CTRL 0x2000 47 #define OTPC_IRQ_ST 0x2008 48 #define OTPC_ACCESS_ADDR 0x200c 49 #define OTPC_RD_DATA 0x2010 50 #define OTPC_REPR_RD_TRANS_NUM 0x2020 51 #define OTPC_DEEP_STANDBY 0x0 52 #define OTPC_STANDBY 0x1 53 #define OTPC_ACTIVE 0x2 54 #define OTPC_READ_ACCESS 0x3 55 #define OTPC_TRANS_NUM 0x1 56 #define OTPC_RDM_IRQ_ST BIT(0) 57 #define OTPC_STB2ACT_IRQ_ST BIT(7) 58 #define OTPC_DP2STB_IRQ_ST BIT(8) 59 #define OTPC_ACT2STB_IRQ_ST BIT(9) 60 #define OTPC_STB2DP_IRQ_ST BIT(10) 61 62 #define KEY_READER_CFG 0x0 63 64 #define RK3308BS_NBYTES 4 65 #define RK3308BS_MAX_BYTES 0x80 66 #define RK3308BS_NO_SECURE_OFFSET 224 67 68 #define RK3568_NBYTES 2 69 70 #define RK3576_NO_SECURE_OFFSET 0x1c0 71 72 #define RK3588_OTPC_AUTO_CTRL 0x04 73 #define RK3588_OTPC_AUTO_EN 0x08 74 #define RK3588_OTPC_INT_ST 0x84 75 #define RK3588_OTPC_DOUT0 0x20 76 #define RK3588_NO_SECURE_OFFSET 0x300 77 #define RK3588_NBYTES 4 78 #define RK3588_BURST_NUM 1 79 #define RK3588_BURST_SHIFT 8 80 #define RK3588_ADDR_SHIFT 16 81 #define RK3588_AUTO_EN BIT(0) 82 #define RK3588_RD_DONE BIT(1) 83 84 #define RV1126_OTP_NVM_CEB 0x00 85 #define RV1126_OTP_NVM_RSTB 0x04 86 #define RV1126_OTP_NVM_ST 0x18 87 #define RV1126_OTP_NVM_RADDR 0x1C 88 #define RV1126_OTP_NVM_RSTART 0x20 89 #define RV1126_OTP_NVM_RDATA 0x24 90 #define RV1126_OTP_NVM_TRWH 0x28 91 #define RV1126_OTP_READ_ST 0x30 92 #define RV1126_OTP_NVM_PRADDR 0x34 93 #define RV1126_OTP_NVM_PRLEN 0x38 94 #define RV1126_OTP_NVM_PRDATA 0x3c 95 #define RV1126_OTP_NVM_FAILTIME 0x40 96 #define RV1126_OTP_NVM_PRSTART 0x44 97 #define RV1126_OTP_NVM_PRSTATE 0x48 98 99 struct rockchip_otp_platdata { 100 void __iomem *base; 101 unsigned long secure_conf_base; 102 unsigned long otp_mask_base; 103 unsigned long otp_cru_rst_base; 104 unsigned long key_reader_base; 105 }; 106 107 #endif 108