xref: /OK3568_Linux_fs/kernel/sound/soc/rockchip/rockchip_sai.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * ALSA SoC Audio Layer - Rockchip SAI Controller driver
4  *
5  * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
6  */
7 
8 #ifndef _ROCKCHIP_SAI_H
9 #define _ROCKCHIP_SAI_H
10 
11 /* XCR Transmit / Receive Control Register */
12 #define SAI_XCR_EDGE_SHIFT_MASK		BIT(22)
13 #define SAI_XCR_EDGE_SHIFT_1		BIT(22)
14 #define SAI_XCR_EDGE_SHIFT_0		0
15 #define SAI_XCR_CSR_MASK		GENMASK(21, 20)
16 #define SAI_XCR_CSR(x)			((x - 1) << 20)
17 #define SAI_XCR_CSR_V(v)		((((v) & SAI_XCR_CSR_MASK) >> 20) + 1)
18 #define SAI_XCR_SJM_MASK		BIT(19)
19 #define SAI_XCR_SJM_L			BIT(19)
20 #define SAI_XCR_SJM_R			0
21 #define SAI_XCR_FBM_MASK		BIT(18)
22 #define SAI_XCR_FBM_LSB			BIT(18)
23 #define SAI_XCR_FBM_MSB			0
24 #define SAI_XCR_SNB_MASK		GENMASK(17, 11)
25 #define SAI_XCR_SNB(x)			((x - 1) << 11)
26 #define SAI_XCR_VDJ_MASK		BIT(10)
27 #define SAI_XCR_VDJ_L			BIT(10)
28 #define SAI_XCR_VDJ_R			0
29 #define SAI_XCR_SBW_MASK		GENMASK(9, 5)
30 #define SAI_XCR_SBW(x)			((x - 1) << 5)
31 #define SAI_XCR_SBW_V(v)		((((v) & SAI_XCR_SBW_MASK) >> 5) + 1)
32 #define SAI_XCR_VDW_MASK		GENMASK(4, 0)
33 #define SAI_XCR_VDW(x)			((x - 1) << 0)
34 
35 /* FSCR Frame Sync Control Register */
36 #define SAI_FSCR_EDGE_MASK		BIT(24)
37 #define SAI_FSCR_EDGE_DUAL		BIT(24)
38 #define SAI_FSCR_EDGE_RISING		0
39 #define SAI_FSCR_FPW_MASK		GENMASK(23, 12)
40 #define SAI_FSCR_FPW(x)			((x - 1) << 12)
41 #define SAI_FSCR_FW_MASK		GENMASK(11, 0)
42 #define SAI_FSCR_FW(x)			((x - 1) << 0)
43 
44 /* MONO_CR Mono Control Register */
45 #define SAI_MCR_RX_MONO_SLOT_MASK	GENMASK(8, 2)
46 #define SAI_MCR_RX_MONO_SLOT_SEL(x)	((x - 1) << 2)
47 #define SAI_MCR_RX_MONO_MASK		BIT(1)
48 #define SAI_MCR_RX_MONO_EN		BIT(1)
49 #define SAI_MCR_RX_MONO_DIS		0
50 #define SAI_MCR_TX_MONO_MASK		BIT(0)
51 #define SAI_MCR_TX_MONO_EN		BIT(0)
52 #define SAI_MCR_TX_MONO_DIS		0
53 
54 /* XFER Transfer Start Register */
55 #define SAI_XFER_RX_IDLE		BIT(8)
56 #define SAI_XFER_TX_IDLE		BIT(7)
57 #define SAI_XFER_FS_IDLE		BIT(6)
58 #define SAI_XFER_RX_CNT_MASK		BIT(5)
59 #define SAI_XFER_RX_CNT_EN		BIT(5)
60 #define SAI_XFER_RX_CNT_DIS		0
61 #define SAI_XFER_TX_CNT_MASK		BIT(4)
62 #define SAI_XFER_TX_CNT_EN		BIT(4)
63 #define SAI_XFER_TX_CNT_DIS		0
64 #define SAI_XFER_RXS_MASK		BIT(3)
65 #define SAI_XFER_RXS_EN			BIT(3)
66 #define SAI_XFER_RXS_DIS		0
67 #define SAI_XFER_TXS_MASK		BIT(2)
68 #define SAI_XFER_TXS_EN			BIT(2)
69 #define SAI_XFER_TXS_DIS		0
70 #define SAI_XFER_FSS_MASK		BIT(1)
71 #define SAI_XFER_FSS_EN			BIT(1)
72 #define SAI_XFER_FSS_DIS		0
73 #define SAI_XFER_CLK_MASK		BIT(0)
74 #define SAI_XFER_CLK_EN			BIT(0)
75 #define SAI_XFER_CLK_DIS		0
76 
77 /* CLR Clear Logic Register */
78 #define SAI_CLR_FSC			BIT(2)
79 #define SAI_CLR_RXC			BIT(1)
80 #define SAI_CLR_TXC			BIT(0)
81 
82 /* CKR Clock Generation Register */
83 #define SAI_CKR_MDIV_MASK		GENMASK(14, 3)
84 #define SAI_CKR_MDIV(x)			((x - 1) << 3)
85 #define SAI_CKR_MSS_MASK		BIT(2)
86 #define SAI_CKR_MSS_SLAVE		BIT(2)
87 #define SAI_CKR_MSS_MASTER		0
88 #define SAI_CKR_CKP_MASK		BIT(1)
89 #define SAI_CKR_CKP_INVERTED		BIT(1)
90 #define SAI_CKR_CKP_NORMAL		0
91 #define SAI_CKR_FSP_MASK		BIT(0)
92 #define SAI_CKR_FSP_INVERTED		BIT(0)
93 #define SAI_CKR_FSP_NORMAL		0
94 
95 /* DMACR DMA Control Register */
96 #define SAI_DMACR_RDE_MASK		BIT(24)
97 #define SAI_DMACR_RDE(x)		((x) << 24)
98 #define SAI_DMACR_RDL_MASK		GENMASK(20, 16)
99 #define SAI_DMACR_RDL(x)		((x - 1) << 16)
100 #define SAI_DMACR_TDE_MASK		BIT(8)
101 #define SAI_DMACR_TDE(x)		((x) << 8)
102 #define SAI_DMACR_TDL_MASK		GENMASK(4, 0)
103 #define SAI_DMACR_TDL(x)		((x) << 0)
104 
105 /* INTCR Interrupt Ctrl Register */
106 #define SAI_INTCR_RXOIC			BIT(18)
107 #define SAI_INTCR_RXOIE_MASK		BIT(17)
108 #define SAI_INTCR_RXOIE(x)		((x) << 17)
109 #define SAI_INTCR_TXUIC			BIT(2)
110 #define SAI_INTCR_TXUIE_MASK		BIT(1)
111 #define SAI_INTCR_TXUIE(x)		((x) << 1)
112 
113 /* INTSR Interrupt Status Register */
114 #define SAI_INTSR_RXOI_INA		0
115 #define SAI_INTSR_RXOI_ACT		BIT(17)
116 #define SAI_INTSR_TXUI_INA		0
117 #define SAI_INTSR_TXUI_ACT		BIT(1)
118 
119 /* XSHIFT: Transfer / Receive Frame Sync Shift Register */
120 #define SAI_XSHIFT_SEL_MASK		GENMASK(23, 0)
121 #define SAI_XSHIFT_SEL(x)		(x)
122 
123 /* SAI Registers */
124 #define SAI_TXCR			(0x0000)
125 #define SAI_FSCR			(0x0004)
126 #define SAI_RXCR			(0x0008)
127 #define SAI_MONO_CR			(0x000c)
128 #define SAI_XFER			(0x0010)
129 #define SAI_CLR				(0x0014)
130 #define SAI_CKR				(0x0018)
131 #define SAI_TXFIFOLR			(0x001c)
132 #define SAI_RXFIFOLR			(0x0020)
133 #define SAI_DMACR			(0x0024)
134 #define SAI_INTCR			(0x0028)
135 #define SAI_INTSR			(0x002c)
136 #define SAI_TXDR			(0x0030)
137 #define SAI_RXDR			(0x0034)
138 #define SAI_PATH_SEL			(0x0038)
139 #define SAI_TX_SLOT_MASK0		(0x003c)
140 #define SAI_TX_SLOT_MASK1		(0x0040)
141 #define SAI_TX_SLOT_MASK2		(0x0044)
142 #define SAI_TX_SLOT_MASK3		(0x0048)
143 #define SAI_RX_SLOT_MASK0		(0x004c)
144 #define SAI_RX_SLOT_MASK1		(0x0050)
145 #define SAI_RX_SLOT_MASK2		(0x0054)
146 #define SAI_RX_SLOT_MASK3		(0x0058)
147 #define SAI_TX_DATA_CNT			(0x005c)
148 #define SAI_RX_DATA_CNT			(0x0060)
149 #define SAI_TX_SHIFT			(0x0064)
150 #define SAI_RX_SHIFT			(0x0068)
151 #define SAI_VERSION			(0x0070)
152 
153 #endif /* _ROCKCHIP_SAI_H */
154