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Spec range is [-12,12] 176 }; 177 MS_U16 reg29; 178 }; 179 union { 180 struct { 181 MS_U16 reg_mfe_s_bsp_bit_cnt_low:16; // encoded bit count (one frame) 182 }; 183 MS_U16 reg42; 184 }; 185 union { 186 struct { 187 MS_U16 reg_mfe_s_bsp_bit_cnt_high:BITCOUNT_HI_BITS; // encoded bit count (one frame) 188 }; 189 MS_U16 reg43; 190 }; 191 } RateControl_REG; 192 193 194 195 196 typedef struct _mfe_reg_ { 197 // [GLOBAL SETTING] 198 union { 199 struct { 200 MS_U16 reg_mfe_g_frame_start_sw:1; // frame start (1T clk_mfe) 201 MS_U16 reg_mfe_g_soft_rstz:1; // software reset; 0/1: reset/not reset 202 MS_U16 reg_mfe_g_enc_mode:2; // 0/1/2/3: MPEG4/H263/H264/JPEG 203 MS_U16 reg_mfe_g_frame_type:2; // 0/1/2: I/P/B 204 MS_U16 reg_mfe_g_ref_no:1; // 0/1: 1 frame/2 frames 205 MS_U16 reg_mfe_g_mbr_en:1; // 0/1: disable/enable MB-level Rate control 206 MS_U16 reg_mfe_g_qscale:6; // frame level qscale: [H264]: 1 ~ 51; [MPEG4]: 1 ~ 31 207 MS_U16 reg_mfe_g_rec_en:1; // reconstruct enable 208 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 209 MS_U16 reg_mfe_g_jpe_mst422_mode:1; // YUV422 input buffer format; 0: YUYV, 1: MST422 210 #endif 211 }; 212 MS_U16 reg00; 213 }; 214 union { 215 struct { 216 MS_U16 reg_mfe_g_pic_width:12; // picture width 217 #ifdef _MFE_M1_ 218 MS_U16 reg_mfe_g_ver_minor_idx:4; 219 #endif 220 }; 221 MS_U16 reg01; 222 }; 223 union { 224 struct { 225 MS_U16 reg_mfe_g_pic_height:12; // picture height 226 #ifdef _MFE_M1_ 227 MS_U16 reg_mfe_g_ver_major_idx:4; 228 #endif 229 }; 230 MS_U16 reg02; 231 }; 232 union { 233 struct { 234 MS_U16 reg_mfe_g_er_mode:2; // 0/1/2/3: mby/bs/mby+bs/off 235 MS_U16 reg_mfe_g_er_mby:2; // 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) 236 MS_U16 reg_mfe_g_packed_mode:1; // frame buffer format for 422 packed mode; 0/1: YVYU/YUYV 237 MS_U16 reg_mfe_g_qmode:1; // quantization method; 0/1: h263/mp4 238 MS_U16 reg_mfe_g_tbc_mode:1; // table mode; 0: SW control, 1: HW control 239 MS_U16 reg_mfe_g_fldpic_en:1; //field picture coding 240 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 241 MS_U16 reg_mfe_g_dct_only_en:1; // reg_mfe_g_dct_only_en 242 #endif 243 #if defined(_MFE_AGATE_) 244 MS_U16 reg_mfe_g_mstar_tile:1; // input buffer format; 0: m4ve tiled mode, 1: mstar tiled mode 245 MS_U16 reg_mfe_g_mstar_tile_field_split:1; // input field buffer format; 0: top/bottom fields interlaced, 1: fields split 246 MS_U16 reg_mfe_g_fldpic_idx:1; 247 #endif 248 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_) 249 MS_U16 reg_mfe_g_fldpic_multislice_en:1; // multi-slice of field picture coding 0/1 : off/on 250 MS_U16 reg_mfe_g_cabac_en:1; // entropy encoding mode 0/1: cavlc/cabac 251 MS_U16 reg03_dummy:1; 252 MS_U16 reg_mfe_miu_sel:1; 253 #elif defined(_MFE_EDISON_) 254 MS_U16 reg03_dummy:2; 255 MS_U16 reg_mfe_ns:1; 256 MS_U16 reg_mfe_miu_sel:1; 257 #endif 258 }; 259 MS_U16 reg03; 260 }; 261 union { 262 struct { 263 MS_U16 reg_mfe_g_er_bs_th:16; // er_bs mode threshold 264 }; 265 MS_U16 reg04; 266 }; 267 union { 268 struct { 269 MS_U16 reg_mfe_g_inter_pref:16; // inter prediction preference 270 }; 271 MS_U16 reg05; 272 }; 273 union { 274 struct { 275 MS_U16 reg_mfe_g_cur_y_adr_low:16; // current luma base address 276 }; 277 MS_U16 reg06; 278 }; 279 union { 280 struct { 281 MS_U16 reg_mfe_g_cur_y_adr_high:ADDR_HI_BITS; // current luma base address 282 }; 283 MS_U16 reg07; 284 }; 285 union { 286 struct { 287 MS_U16 reg_mfe_g_cur_c_adr_low:16; // current chroma base address 288 }; 289 MS_U16 reg08; 290 }; 291 union { 292 struct { 293 MS_U16 reg_mfe_g_cur_c_adr_high:ADDR_HI_BITS; // current chroma base address 294 }; 295 MS_U16 reg09; 296 }; 297 union { 298 struct { 299 MS_U16 reg_mfe_g_ref_y_adr0_low:16; // reference luma base address0 300 }; 301 MS_U16 reg0a; 302 }; 303 union { 304 struct { 305 MS_U16 reg_mfe_g_ref_y_adr0_high:ADDR_HI_BITS; // reference luma base address0 306 }; 307 MS_U16 reg0b; 308 }; 309 union { 310 struct { 311 MS_U16 reg_mfe_g_ref_y_adr1_low:16; // reference luma base address1 312 }; 313 MS_U16 reg0c; 314 }; 315 union { 316 struct { 317 MS_U16 reg_mfe_g_ref_y_adr1_high:ADDR_HI_BITS; // reference luma base address0 318 }; 319 MS_U16 reg0d; 320 }; 321 union { 322 struct { 323 MS_U16 reg_mfe_g_ref_c_adr0_low:16; // reference chroma base address0 324 }; 325 MS_U16 reg0e; 326 }; 327 union { 328 struct { 329 MS_U16 reg_mfe_g_ref_c_adr0_high:ADDR_HI_BITS; // reference chroma base address0 330 }; 331 MS_U16 reg0f; 332 }; 333 union { 334 struct { 335 MS_U16 reg_mfe_g_ref_c_adr1_low:16; // reference chroma base address1 336 }; 337 MS_U16 reg10; 338 }; 339 union { 340 struct { 341 MS_U16 reg_mfe_g_ref_c_adr1_high:ADDR_HI_BITS; // reference chroma base address1 342 }; 343 MS_U16 reg11; 344 }; 345 union { 346 struct { 347 MS_U16 reg_mfe_g_rec_y_adr_low:16; // reconstructed luma base address 348 }; 349 MS_U16 reg12; 350 }; 351 union { 352 struct { 353 MS_U16 reg_mfe_g_rec_y_adr_high:ADDR_HI_BITS; // reconstructed luma base address 354 }; 355 MS_U16 reg13; 356 }; 357 union { 358 struct { 359 MS_U16 reg_mfe_g_rec_c_adr_low:16; // reconstructed chroma base address 360 }; 361 MS_U16 reg14; 362 }; 363 union { 364 struct { 365 MS_U16 reg_mfe_g_rec_c_adr_high:ADDR_HI_BITS; // reconstructed chroma base address 366 }; 367 MS_U16 reg15; 368 }; 369 union { 370 struct { // clock gating 371 MS_U16 gate_cry_crc_sram:1; 372 MS_U16 gate_qtab_dbfdc_dbqtb_sram:1; 373 MS_U16 gate_mcy_mcc_sram:1; 374 MS_U16 gate_res0_res1_sram:1; 375 MS_U16 gate_ieap:1; 376 MS_U16 gate_dct_idct:1; 377 MS_U16 gate_dbf:1; 378 }; 379 MS_U16 reg16; 380 }; 381 union { 382 struct { 383 #ifdef _MFE_M1_ 384 MS_U16 reg_mfe_s_auto_rst_wait_cnt:6; // the waiting count for regen_soft_rstz and regen_fs_sw generation 385 MS_U16 reg_mfe_g_sram1p_wp_type:1; // "MFE 1p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" 386 MS_U16 reg_mfe_g_sram2p_wp_type:1; // "MFE 2p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" 387 MS_U16 reg_mfe_g_clk_mfe_en:4; // NOT used now. 388 MS_U16 reg_mfe_g_mreq_sel:1; // "1" D1 MIU clk gating; "0" dynamic MIU clk gating 389 MS_U16 reg_mfe_g_mreq_always_active:1; // "1" mreq always active; "0" make mreq active according to FSM. (let this be default) 390 MS_U16 reg_mfe_g_clk_miu_d2_gate:1; // b1: turn off miu clock of power-domain "dma" and sleep into d2 mode 391 MS_U16 reg_mfe_g_clk_mfe_d2_gate:1; // b1: turn off mfe clock of power-domain "core" and sleep into d2 mode 392 #elif defined(_MFE_AGATE_) 393 MS_U16 reg_mfe_s_auto_rst_wait_cnt:6; // the waiting count for regen_soft_rstz and regen_fs_sw generation 394 MS_U16 reg_mfe_g_clk_mfe_en_dummy:8; // no use 395 MS_U16 reg_mfe_g_clk_miu_d2_gate:1; // b1: turn off miu clock of power-domain "dma" and sleep into d2 mode 396 MS_U16 reg_mfe_g_clk_mfe_d2_gate:1; // b1: turn off mfe clock of power-domain "core" and sleep into d2 mode 397 #else 398 MS_U16 reserved_reg17; 399 #endif 400 }; 401 MS_U16 reg17; 402 }; 403 // [JPEG] 404 union { 405 struct { 406 MS_U16 reg_mfe_g_jpe_enc_mode:2; // JPE encode mode; 2'b00/2'b01/2'b10/2'b11: 420/422/444/gray; current version supports 422 only 407 MS_U16 reg_mfe_g_jpe_buffer_mode:1; // JPE buffer mode; 0/1: double buffer mode/frame buffer mode 408 MS_U16 reg_mfe_g_jpe_multibuf_mode:2; // JPE multi-buffer mode; 0/1/2: 2/4/8 buffers 409 MS_U16 reg_mfe_g_jpe_qfactor:4; // JPE q factor; 0 ~ 15: (1 ~ 16)/4 410 // (M1)JPE fsvs generation mode; 411 // 0: pure sw 412 // 1: sw+hw 413 // 2: hw w/o auto-restart 414 // 3: hw w/i auto-restart 415 MS_U16 reg_mfe_g_jpe_fsvs_mode:2; // (T8)JPE fsvs generation mode; 0/1/2: pure sw/sw+hw/hw 416 MS_U16 reg18_dummy:4; 417 MS_U16 reg_mfe_g_viu_soft_rstz:1; // viu software reset; 0/1: reset/not reset 418 }; 419 MS_U16 reg18; 420 }; 421 // [MPEG4/H263] 422 union { 423 struct { 424 MS_U16 reg_mfe_g_mp4_itlc:1; // 0/1: MPEG4 progressive/interlaced mode 425 MS_U16 reg_mfe_g_mp4_pskip_off:1; // 0/1: MPEG4 enable/disable p skip mode 426 MS_U16 reg_mfe_g_mp4_acp:2; // [0]: 0/1: sw/hw acp selection; [1]: sw default value: 0/1: disable/enable acp; current version off 427 MS_U16 reg_mfe_g_mp4_rounding_ctrl:1; // mp4 rounding control specified as in spec 428 MS_U16 reg_mfe_g_er_hec:1; // 0/1: header extension code off/on 429 MS_U16 reg_mfe_g_er_hec_t:3; // HEC counter reset values 430 MS_U16 reg_mfe_g_er_h263_unit:2; // 0/1/2: unit is 1/2/4, for calculating gob_num. 431 MS_U16 reg_mfe_g_mp4_direct_en:1; // MPEG4 direct enable 432 MS_U16 reg_mfe_g_mp4_direct_mvstore:1; // [M]: enable storing of mv & skip_mb information to DRAM in P(or sometimes I) frame 433 }; 434 MS_U16 reg19; 435 }; 436 union { 437 struct { 438 MS_U16 reg_mfe_g_mp4_direct_pref:8; // used in mp4 only, mp4 direct mode preference value 439 MS_U16 reg_mfe_g_mp4_direct_trb:3; // used in mp4 only, mp4 direct mode trb (P0-B distance) 440 MS_U16 reg_mfe_g_mp4_direct_trd:3; // used in mp4 only, mp4 direct mode trd (P0-P1 distance) 441 #ifdef _MFE_AGATE_ 442 MS_U16 reg1a_dummy:1; 443 MS_U16 reg_mfe_g_mb_pitch_en:1; 444 #endif 445 }; 446 MS_U16 reg1a; 447 }; 448 union { 449 struct { 450 MS_U16 reg_mfe_g_mp4_flddct_diff_thr:8; // used in mp4 only, mp4 field dct difference threshold 451 MS_U16 reg_mfe_g_mp4_flddct_en:1; // used in mp4 only, mp4 field dct enable 452 }; 453 MS_U16 reg1b; 454 }; 455 // [IRQ & important IP status checkings] 456 union { 457 struct { 458 MS_U16 reg_mfe_g_irq_mask:8; // 0/1: irq not-mask/mask 459 MS_U16 reg_mfe_g_irq_force:8; // 0/1: set corresponding interrupt as usual/force corresponding interrupt 460 }; 461 MS_U16 reg1c; 462 }; 463 union { 464 struct { 465 MS_U16 reg_mfe_g_irq_clr0:1; // 0/1: not clear interrupt/clear interrupt 0 466 MS_U16 reg_mfe_g_irq_clr1:1; // 0/1: not clear interrupt/clear interrupt 1 467 MS_U16 reg_mfe_g_irq_clr2:1; // 0/1: not clear interrupt/clear interrupt 2 468 MS_U16 reg_mfe_g_irq_clr3:1; // 0/1: not clear interrupt/clear interrupt 3 469 MS_U16 reg_mfe_g_irq_clr4:1; // 0/1: not clear interrupt/clear interrupt 4 470 MS_U16 reg_mfe_g_irq_clr5:1; // 0/1: not clear interrupt/clear interrupt 5 471 MS_U16 reg_mfe_g_irq_clr6:1; // 0/1: not clear interrupt/clear interrupt 6 472 MS_U16 reg_mfe_g_irq_clr7:1; // 0/1: not clear interrupt/clear interrupt 7 473 MS_U16 reg_mfe_g_swrst_safe:1; // to indicate there're no miu activities that need to pay attention to 474 }; 475 MS_U16 reg1d; 476 }; 477 union { 478 struct { 479 //status of interrupt on CPU side ({1'b0, net_trigger, fs_fail_irq, txip_time_out, early_bspobuf_full_irq/buf1_full, img_buf_full_irq, marb_bspobuf_ful1/buf0_full, frame_done_irq}) 480 //[3] SW mode: early obuf full; HW mode: buf1 full 481 //[1] SW mode: buf full; HW mode: buf0 full 482 MS_U16 reg_mfe_g_irq_cpu:8; 483 //status of interrupt on IP side ({1'b0, net_trigger, fs_fail_irq, txip_time_out, early_bspobuf_full_irq/buf1_full, img_buf_full_irq, marb_bspobuf_ful/buf0_full, frame_done_irq}) 484 //[3] SW mode: early obuf full; HW mode: buf1 full 485 //[1] SW mode: buf full; HW mode: buf0 full 486 MS_U16 reg_mfe_g_irq_ip:8; 487 }; 488 MS_U16 reg1e; 489 }; 490 union { 491 struct { 492 MS_U16 reserved_reg1f; 493 }; 494 MS_U16 reg1f; 495 }; 496 // [ME setting] 497 union { 498 struct { 499 MS_U16 reg_mfe_s_me_4x4_disable:1; // 4x4_disable 500 MS_U16 reg_mfe_s_me_8x4_disable:1; // 8x4_disable 501 MS_U16 reg_mfe_s_me_4x8_disable:1; // 4x8_disable 502 MS_U16 reg_mfe_s_me_16x8_disable:1; // 16x8_disable 503 MS_U16 reg_mfe_s_me_8x16_disable:1; // 8x16_disable 504 MS_U16 reg_mfe_s_me_8x8_disable:1; // 8x8_disable 505 MS_U16 reg_mfe_s_me_16x16_disable:1; // 16x16_disable 506 MS_U16 reg_mfe_s_mesr_adapt:1; // me search range auto-adaptive; 0/1: off/on 507 MS_U16 reg_mfe_s_me_ref_en_mode:2; // ref enable mode: 2'b01/2'b10/2'b11: ref0 enable/ref1 enable/ref0&1 enable 508 }; 509 MS_U16 reg20; 510 }; 511 // [IME PIPELINE] 512 union { 513 struct { 514 MS_U16 reg_mfe_s_ime_sr16:1; // search range limited to (h,v) = (+/-16, +/-16); 0/1: search range 32/16 515 MS_U16 reg_mfe_s_ime_umv_disable:1; // 0/1: UMV enable/disable 516 MS_U16 reg_mfe_s_ime_ime_wait_fme:1; // 0/1: ime wait fme/fme wait ime 517 MS_U16 reg_mfe_s_ime_boundrect_en:1; // ime bounding rectangle enable (needed for level 3.0 and below) 518 MS_U16 reg_mfe_s_ime_h264_p8x8_ctrl_en:1; // ime h264 max p8x8 count control enable 519 MS_U16 reg21_dummy:3; 520 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 521 MS_U16 reg_mfe_s_ime_h264_p8x8_max:8; // ime h264 max p8x8 count; value 0 is prohibited 522 // Max P8x8 MB count = 16 * reg_mfe_s_ime_h264_p8x8_max 523 524 #else 525 MS_U16 reg_mfe_s_ime_h264_p8x8_max:6; // ime h264 max p8x8 count; value 0 is prohibited 526 // Max P8x8 MB count = 16 * reg_mfe_s_ime_h264_p8x8_max 527 #endif 528 }; 529 MS_U16 reg21; 530 }; 531 union { 532 struct { 533 MS_U16 reg_mfe_s_ime_mesr_max_addr:8; // me search range max depth 534 MS_U16 reg_mfe_s_ime_mesr_min_addr:8; // me search range min depth 535 }; 536 MS_U16 reg22; 537 }; 538 union { 539 struct { 540 MS_U16 reg_mfe_s_ime_mvx_min:6; // me mvx min; 0/�K/62 --> -32/�K/30 541 MS_U16 reg24_dummy:2; 542 MS_U16 reg_mfe_s_ime_mvx_max:6; // me mvx max; 0/�K/62 --> -32/�K/30 543 }; 544 MS_U16 reg23; 545 }; 546 union { 547 struct { 548 MS_U16 reg_mfe_s_ime_mvy_min:6; // me mvy min; 0/�K/62 --> -32/�K/30 549 MS_U16 reg25_dummy:2; 550 MS_U16 reg_mfe_s_ime_mvy_max:6; // me mvy max; 0/�K62/ --> -32/�K/30 551 }; 552 MS_U16 reg24; 553 }; 554 // [FME pipeline] 555 union { 556 struct { 557 MS_U16 reg_mfe_s_fme_quarter_disable:1; // 0/1: Quarter fine-tune enable/disable 558 MS_U16 reg_mfe_s_fme_half_disable:1; // 0/1: Half fine-tune enable/disable 559 MS_U16 /*reg_mfe_s_fme_one_mode*/reg26_dummy:1; 560 MS_U16 reg_mfe_s_fme_pmv_enable:1; // 0/1: disable/enable Previous Skip MV mode 561 MS_U16 reg_mfe_s_fme_mode_no:1; // 0: one mode. 1: two mode. 562 MS_U16 reg_mfe_s_fme_mode0_refno:1; // 0: one ref. for mode0 1: two ref. for mode0 563 MS_U16 reg_mfe_s_fme_mode1_refno:1; // 0: one ref. for mode1 1: two ref. for mode1 564 MS_U16 reg_mfe_s_fme_mode2_refno:1; // 0: one ref. for mode2 1: two ref. for mode2 565 MS_U16 reg_mfe_s_fme_skip:1; // fme skip 566 MS_U16 reg_mfe_s_fme_pipeline_on:1; //0/1: FME pipeline off/on 567 }; 568 MS_U16 reg25; 569 }; 570 // MBR 571 union { 572 struct { 573 MS_U16 reg_mfe_s_mbr_pqp_dlimit:2; // previous qp diff limit 574 MS_U16 reg_mfe_s_mbr_uqp_dlimit:2; // upper qp diff limit 575 MS_U16 reg_mfe_s_mbr_tmb_bits:12; // target MB bits 576 }; 577 MS_U16 reg26; 578 }; 579 union { 580 struct { 581 MS_U16 reg_mfe_s_mbr_frame_qstep:13; // frame level qp's qstep 582 }; 583 MS_U16 reg27; 584 }; 585 union { 586 struct { 587 MS_U16 reg_mfe_s_mbr_last_frm_avg_qp_low:16; // last frame average qp (status register) 588 }; 589 MS_U16 reg28; 590 }; 591 union { 592 struct { 593 MS_U16 reg_mfe_s_mbr_last_frm_avg_qp_high:LAST_FRAME_AVGQP_HI_BITS; // last frame average qp (status register) 594 MS_U16 reg_mfe_s_mbr_qp_cidx_offset:5; // [H264] chroma qp index offset (+12). Spec range is [-12,12] 595 }; 596 MS_U16 reg29; 597 }; 598 union { 599 struct { 600 MS_U16 reg_mfe_s_mbr_qp_min:6; // qp min 601 MS_U16 reg_mfe_s_mbr_qp_max:6; // qp max 602 MS_U16 reg_mfe_s_mvdctl_ref0_offset:2; // H264 mvy offset adjustment for MCC if ref is frame 0: 0/1/2: 0/+2/-2 603 MS_U16 reg_mfe_s_mvdctl_ref1_offset:2; // H264 mvy offset adjustment for MCC if ref is frame 1: 0/1/2: 0/+2/-2 604 }; 605 MS_U16 reg2a; 606 }; 607 // IEAP 608 union { 609 struct { 610 MS_U16 reg_mfe_s_ieap_last_mode:4; // software control of the last mode of Intra4x4 mode 0 ~ 8 611 MS_U16 reg_mfe_s_ieap_constraint_intra:1; // software control constraint intra; 0/1: OFF/ON 612 MS_U16 reg_mfe_s_ieap_ccest_en:1; // software control cost estimator; 0/1: OFF/ON 613 MS_U16 reg_mfe_s_ieap_ccest_thr:2; // threshold of cost estimator set 0 ~ 3 for threshold 1 ~ 4 614 MS_U16 reg_mfe_s_ieap_drop_i16:1; // software control stop-Intra16x16-mode; 1:w/o I16M, 0:w/i I16MB 615 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_) 616 MS_U16 reg_mfe_s_ieap_early_termination:1; // 1/0: turn on/off ieap early termination 617 #endif 618 }; 619 MS_U16 reg2b; 620 }; 621 // QUAN 622 union { 623 struct { 624 MS_U16 reg_mfe_s_quan_idx_last:6; // the index of the last non-zero coefficient in the zig-zag order 625 MS_U16 reg_mfe_s_quan_idx_swlast:1; // software control of the index of the last non-zero coefficient in the zig-zag order; 0/1: disable/enable 626 #ifdef _MFE_AGATE_ 627 MS_U16 reg_mfe_g_mb_pitch:7; // mb pitch (x-direction) 628 #endif 629 #if defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_) 630 MS_U16 reg2c_dummy:1;// dummy 631 MS_U16 reg_mfe_g_ieap_sram_4x2_swap:1;//0/1: for ieap 4pels sram interface / for ieap 8pels sram interface 632 #endif 633 }; 634 MS_U16 reg2c; 635 }; 636 // TXIP control & debug 637 union { 638 struct { 639 MS_U16 reg_mfe_s_txip_mbx:9; //txip mbx 640 MS_U16 reg_mfe_s_txip_sng_mb:1; //0/1: disable/enable txip controller stop-and-go mechanism using (txip_mbx == reg_mfe_g_debug_trig_mbx) & (txip_mby == reg_mfe_g_debug_trig_mby) 641 MS_U16 reg_mfe_s_txip_sng_set:1; //txip controller stop-and-go mechanism using this register bit: 0/1: go/stop 642 MS_U16 reg_mfe_s_txip_dbf_full_halt_en:1; //txip controller stop-and-go mechanism using double buffer fullness as criterion; 0/1: disable/enable 643 }; 644 MS_U16 reg2d; 645 }; 646 union { 647 struct { 648 MS_U16 reg_mfe_s_txip_mby:9; // txip mby 649 }; 650 MS_U16 reg2e; 651 }; 652 union { 653 struct { 654 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 655 MS_U16 reg_mfe_s_txip_irfsh_mb_s0:13; // intra refresh mb start 0 656 MS_U16 reg2f_dummy:1; 657 #else 658 MS_U16 reg_mfe_s_txip_irfsh_mb_s0:12; // intra refresh mb start 0 659 #endif 660 MS_U16 reg_mfe_s_txip_irfsh_en:2; // intra refresh enable bits: bit0: enable condition 0; bit 1: enable condition 1 661 }; 662 MS_U16 reg2f; 663 }; 664 union { 665 struct { 666 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 667 MS_U16 reg_mfe_s_txip_irfsh_mb_e0:13; // intra refresh mb end 0 668 #else 669 MS_U16 reg_mfe_s_txip_irfsh_mb_e0:12; // intra refresh mb end 0 670 #endif 671 }; 672 MS_U16 reg30; 673 }; 674 union { 675 struct { 676 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 677 MS_U16 reg_mfe_s_txip_irfsh_mb_s1:13; // intra refresh mb start 1 678 #else 679 MS_U16 reg_mfe_s_txip_irfsh_mb_s1:12; // intra refresh mb start 1 680 #endif 681 }; 682 MS_U16 reg31; 683 }; 684 union { 685 struct { 686 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 687 MS_U16 reg_mfe_s_txip_irfsh_mb_e1:13; // intra refresh mb end 1 688 MS_U16 reg32_dummy:1; 689 #else 690 MS_U16 reg_mfe_s_txip_irfsh_mb_e1:12; // intra refresh mb end 1 691 #endif 692 MS_U16 reg_mfe_s_txip_timeout_en:1; // txip time out enable 693 MS_U16 reg_mfe_s_txip_wait_mode:1; // txip waiting mode to move to next MB; 0/1: idle count/cycle count 694 }; 695 MS_U16 reg32; 696 }; 697 union { 698 struct { 699 MS_U16 reg_mfe_s_txip_idle_cnt:16; // wait mode is 0: txip idle count (x 64T)/ wait mode is 1: txip total processing count (x 64T) 700 }; 701 MS_U16 reg33; 702 }; 703 union { 704 struct { 705 MS_U16 reg_mfe_s_txip_timeout:16; // txip timeout count (x 64T) 706 }; 707 MS_U16 reg34; 708 }; 709 // [ECDB PIPELINE] 710 // ECDB control & debug 711 union { 712 struct { 713 MS_U16 reg_mfe_s_ecdb_mbx:9; // ecdb mbx 714 }; 715 MS_U16 reg35; 716 }; 717 union { 718 struct { 719 MS_U16 reg_mfe_s_ecdb_mby:9; // ecdb mby 720 }; 721 MS_U16 reg36; 722 }; 723 // MDC 724 union { 725 struct { 726 MS_U16 reg_mfe_s_mdc_total_mb_bw:4; // total mb bit width used in video_pkt 727 MS_U16 reg_mfe_s_mdc_m4vpktpzero:1; // MPEG4 video packet preceding zeros: 0/1: 16/17 zeros 728 MS_U16 reg_mfe_s_mdc_m4time:2; // MPEG4 modulo time base: 0/1/2/3: 0/10/110/1110 729 MS_U16 reg_mfe_s_mdc_m4iadcvlc_th:3; // MPEG4 intra dc vlc threshold 730 MS_U16 reg_mfe_s_mdc_m4vop_tinc_bw:4; // vop_time_increment bit width 731 }; 732 MS_U16 reg37; 733 }; 734 union { 735 struct { 736 MS_U16 reg_mfe_s_mdc_m4vop_tinc:15; // vop_time_increment 737 }; 738 MS_U16 reg38; 739 }; 740 union { 741 struct { 742 MS_U16 reg_mfe_s_mdc_gob_frame_id:2; // H263 gob frame id 743 MS_U16 reg_mfe_s_mdc_h264_nal_ref_idc:2; // nal_ref_idc 744 MS_U16 reg_mfe_s_mdc_h264_nal_unit_type:1; // 0/1: 1/5 745 MS_U16 reg_mfe_s_mdc_h264_fnum_bits:2; // H264 frame num bits 746 MS_U16 reg_mfe_s_mdc_h264_dbf_control:1; // dbf control present flag 747 MS_U16 reg_mfe_s_mdc_h264_fnum_value:8; // H264 frame num value 748 }; 749 MS_U16 reg39; 750 }; 751 union { 752 struct { 753 MS_U16 reg_mfe_s_mdc_h264_idr_pic_id:3; 754 MS_U16 reg_mfe_s_mdc_h264_disable_dbf_idc:2; 755 MS_U16 reg_mfe_s_mdc_h264_alpha:4; // slice_alpha_c0_offset_div2 756 MS_U16 reg_mfe_s_mdc_h264_beta:4; // slice_beta_offset_div2 757 MS_U16 reg_mfe_s_mdc_h264_ridx_aor_flag:1; // reference index active override flag 758 }; 759 MS_U16 reg3a; 760 }; 761 // BSPOBUF/MVOBUF 762 union { 763 struct { 764 MS_U16 reg_mfe_s_bspobuf_set_adr:1; // set bsp obuf start address(write one clear) 765 MS_U16 reg_mfe_s_mvobuf_set_adr:1; // set mv obuf start address (write one clear) 766 MS_U16 reg_mfe_s_bspobuf_fifo_th:3; // bsp obuf threshold 767 MS_U16 reg_mfe_s_mvobuf_fifo_th:3; // mv obuf threshold 768 MS_U16 reg_mfe_s_bsp_fdc_skip:1; // fdc skip enable; 0: fdc skip disable, 1: fdc skip enable 769 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 770 MS_U16 dummy_reg3b:5; 771 MS_U16 reg_mfe_s_obuf_toggle_obuf0_status:1; // toggle buf0 status(write one clear) 772 MS_U16 reg_mfe_s_obuf_toggle_obuf1_status:1; // toggle buf1 status(write one clear) 773 #elif !defined(_MFE_T8_) 774 MS_U16 reg_mfe_s_txip_irfsh_mb_e1:13; // intra refresh mb end 1 775 #endif 776 }; 777 MS_U16 reg3b; 778 }; 779 union { 780 struct { 781 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 782 MS_U16 reg_mfe_s_bspobuf_low:16; // bsp obuf start address 783 #else 784 MS_U16 reg_mfe_s_bspobuf_sadr_low:16; // bsp obuf start address 785 #endif 786 }; 787 MS_U16 reg3c; 788 }; 789 union { 790 struct { 791 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 792 MS_U16 reg_mfe_s_bspobuf_high:OUTBUF_HI_BITS; // bsp obuf address high 793 MS_U16 reg3d_dummy_bits:(16-OUTBUF_HI_BITS-2); 794 MS_U16 reg_mfe_s_obuf_id:2; // 00: s0, 01: e0, 10: s1, 11: e1 795 #else 796 MS_U16 reg_mfe_s_bspobuf_sadr_high:OUTBUF_HI_BITS; // bsp obuf start address 797 #endif 798 799 }; 800 MS_U16 reg3d; 801 }; 802 union { 803 struct { 804 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 805 MS_U16 reg_mfe_s_obuf_write_id_adr:1; // write to this address to enable writing of bspobuf address 806 #else 807 MS_U16 reg_mfe_s_bspobuf_eadr_low:16; // bsp obuf end address 808 #endif 809 }; 810 MS_U16 reg3e; 811 }; 812 union { 813 struct { 814 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 815 MS_U16 reg_mfe_s_bspobuf_hw_en:1; // enable HW obuf automatic mechanism 816 MS_U16 reg_mfe_s_bspobuf_update_adr:1; // update obuf address(write one clear) 817 MS_U16 reg_mfe_s_bspobuf_adr_rchk_sel:2; // obuf adr read back check selection: 0/1/2/3: s0/e0/s1/e1 818 MS_U16 reg_mfe_s_bspobuf_adr_rchk_en:1; // enable bspobuf adr read back check through reg_mfe_s_bspobuf_wptr 819 MS_U16 dummy_reg3f:3; 820 MS_U16 reg_mfe_s_bsp_fdc_offset:7; // bsp's fdc offset 821 #else 822 MS_U16 reg_mfe_s_bspobuf_eadr_high:OUTBUF_HI_BITS; // bsp obuf end address 823 #endif 824 }; 825 MS_U16 reg3f; 826 }; 827 union { 828 struct { 829 MS_U16 reg_mfe_s_mvobuf_sadr_low:16; // mv obuf start address 830 }; 831 MS_U16 reg40; 832 }; 833 union { 834 struct { 835 MS_U16 reg_mfe_s_mvobuf_sadr_high:OUTBUF_HI_BITS; // mv obuf start address 836 }; 837 MS_U16 reg41; 838 }; 839 union { 840 struct { 841 MS_U16 reg_mfe_s_bsp_bit_cnt_low:16; // encoded bit count (one frame) 842 }; 843 MS_U16 reg42; 844 }; 845 union { 846 struct { 847 MS_U16 reg_mfe_s_bsp_bit_cnt_high:BITCOUNT_HI_BITS; // encoded bit count (one frame) 848 }; 849 MS_U16 reg43; 850 }; 851 union { 852 struct { 853 MS_U16 reg_mfe_s_bspobuf_wptr_low:16; // bspobuf write pointer (8 byte unit) 854 }; 855 MS_U16 reg44; 856 }; 857 union { 858 struct { 859 MS_U16 reg_mfe_s_bspobuf_wptr_high:OUTBUF_HI_BITS; // bspobuf write pointer (8 byte unit) 860 }; 861 MS_U16 reg45; 862 }; 863 // FDC 864 union { 865 struct { 866 MS_U16 reg_mfe_s_fdc_bs:16; // cpu to fdc bitstream data 867 }; 868 MS_U16 reg46; 869 }; 870 union { 871 struct { 872 MS_U16 reg_mfe_s_fdc_bs_len:5; // cpu to fdc bitstream len; 0 ~ 16 873 MS_U16 reg_mfe_s_fdc_bs_count:10; // cpu to fdc round count 874 }; 875 MS_U16 reg47; 876 }; 877 // [Table Control] 878 union { 879 struct { 880 MS_U16 reg_mfe_s_fdc_ack:1; // fdc to cpu ack; 0/1: frame data pool not empty/frame data pool empty; 48x64 bits of space 881 MS_U16 reg_mfe_s_fdc_done_clr:1; // fdc done clear (write one clear) 882 MS_U16 reg_mfe_s_fdc_done:1; // fdc done; indicate to CPU that data has been written to internal buffer 883 MS_U16 reg48_dummy:8; 884 MS_U16 reg_mfe_s_fdc_bs_vld:1; // set for bitstream write out (write one clear) 885 MS_U16 reg_mfe_s_tbc_en:1; // set for table read & write ; 1: enable, 0: disable (write one clear) 886 }; 887 MS_U16 reg48; 888 }; 889 union { 890 struct { 891 MS_U16 reg_mfe_s_tbc_rw:1; // table mode; 0: read, 1: write 892 MS_U16 reg_mfe_s_tbc_done_clr:1; // table done clear (write one clear) 893 MS_U16 reg_mfe_s_tbc_done:1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg_mfe_s_tbc_rdata 894 MS_U16 reg49_dummy:5; 895 MS_U16 reg_mfe_s_tbc_adr:6; // table address 896 }; 897 MS_U16 reg49; 898 }; 899 union { 900 struct { 901 MS_U16 reg_mfe_s_tbc_wdata:16; // table write data 902 }; 903 MS_U16 reg4a; 904 }; 905 union { 906 struct { 907 MS_U16 reg_mfe_s_tbc_rdata:16; // table read data 908 }; 909 MS_U16 reg4b; 910 }; 911 // [Get Neighbor] 912 union { 913 struct { 914 MS_U16 reg_mfe_s_gn_sadr_low:16; // gn base adr low 915 }; 916 MS_U16 reg4c; 917 }; 918 union { 919 struct { 920 MS_U16 reg_mfe_s_gn_sadr_high:OUTBUF_HI_BITS; // gn base adr high 921 #ifdef _MFE_M1_ 922 #if (16-OUTBUF_HI_BITS-1>0) 923 MS_U16 dummy_reg4d:16-OUTBUF_HI_BITS-1; 924 #endif 925 MS_U16 reg_mfe_s_gn_sadr_mode:1; // 1: gn save data in one frame 0: gn save data in one row 926 #endif 927 }; 928 MS_U16 reg4d; 929 }; 930 union { 931 struct { 932 MS_U16 reg_mfe_s_gn_mvibuf_sadr_low:16; // mv ibuf start address low 933 }; 934 MS_U16 reg4e; 935 }; 936 union { 937 struct { 938 MS_U16 reg_mfe_s_gn_mvibuf_sadr_high:OUTBUF_HI_BITS; // mv ibuf start address high 939 #if defined(MFE_DBF_PACKED_MODE) 940 #if (16-OUTBUF_HI_BITS-2 > 0) 941 MS_U16 reg4f_dummy:(16-OUTBUF_HI_BITS-2); 942 #endif 943 MS_U16 reg_mfe_s_gn_bwr_mode:2; // bit[0]: 0, DBF bottom row data write to reconstructed address, 944 // 1, DBF bottom row data write to IMI 945 // bit[1]: DBF packed mode. 0: disable, 1: enable 946 #endif 947 }; 948 MS_U16 reg4f; 949 }; 950 union { 951 struct { 952 MS_U16 reg_mfe_s_marb_rp0_promote:4; 953 MS_U16 reg_mfe_s_marb_rp1_promote:4; 954 MS_U16 reg_mfe_s_marb_rp2_promote:4; 955 MS_U16 reg_mfe_s_marb_rp3_promote:4; 956 }; 957 MS_U16 reg51; 958 }; 959 union { 960 struct { 961 MS_U16 reg_mfe_s_marb_mrpriority_thd:4; 962 MS_U16 reg_mfe_s_marb_mwpriority_thd:4; 963 MS_U16 reg_mfe_s_marb_rp4_occupy:4; 964 MS_U16 reg_mfe_s_marb_rp4_promote:4; 965 }; 966 MS_U16 reg55; 967 }; 968 union { 969 struct { 970 MS_U16 reg_mfe_s_marb_mrpriority_sw:2; // mfe2mi_rpriority software programmable 971 MS_U16 reg_mfe_s_marb_mr_timeout_ref:1; //miu read burst timeout count start point 972 MS_U16 reg_mfe_s_marb_mr_nwait_mw:1; //miu read not wait mi2mfe_wrdy 973 MS_U16 reg_mfe_s_marb_mwpriority_sw:2; //mfe2mi_wpriority software programmable 974 MS_U16 reg_mfe_s_marb_mw_timeout_ref:1; //miu write burst timeout count start point 975 MS_U16 reg_mfe_s_marb_mw_nwait_mr:1; //miu read not wait mi2mfe_wrdy 976 MS_U16 reg_mfe_s_marb_mr_pending:4; //max. pending read requests to miu 977 MS_U16 reg_mfe_s_marb_32b_ad_nswap:1; //32bits miu address not swap. only for 32bits mode 978 MS_U16 reg_mfe_s_marb_miu_wmode:1; //0/1: original miu protocol/new miu protocol(wd_en) 979 980 }; 981 MS_U16 reg56; 982 }; 983 union { 984 struct { 985 MS_U16 reg_mfe_s_marb_ubound_0_low:16; // MIU protect for MPEG4 BSP obuf 986 }; 987 MS_U16 reg58; 988 }; 989 union { 990 struct { 991 MS_U16 reg_mfe_s_marb_ubound_0_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 BSP obuf 992 MS_U16 reg59_dummy:(16-OUTBUF_HI_BITS); 993 994 }; 995 MS_U16 reg59; 996 }; 997 union { 998 struct { 999 MS_U16 reg_mfe_s_marb_lbound_0_low:16; // MIU protect for MPEG4 BSP obuf 1000 }; 1001 MS_U16 reg5a; 1002 }; 1003 union { 1004 struct { 1005 MS_U16 reg_mfe_s_marb_lbound_0_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 BSP obuf 1006 #ifdef _MFE_A3_ 1007 MS_U16 reg_mfe_s_marb_miu_bound_en_0:1; // 1008 #endif 1009 }; 1010 MS_U16 reg5b; 1011 }; 1012 union { 1013 struct { 1014 MS_U16 reg_mfe_s_marb_ubound_1_low:16; // MIU Upper bound protect for MPEG4 MC obuf rec 1015 }; 1016 MS_U16 reg5c; 1017 }; 1018 union { 1019 struct { 1020 MS_U16 reg_mfe_s_marb_ubound_1_high:OUTBUF_HI_BITS; // MIU Upper bound protect for MPEG4 MC obuf rec 1021 }; 1022 MS_U16 reg5d; 1023 }; 1024 union { 1025 struct { 1026 MS_U16 reg_mfe_s_marb_lbound_1_low:16; // MIU Lower bound protect for MPEG4 MC obuf 1027 }; 1028 MS_U16 reg5e; 1029 }; 1030 union { 1031 struct { 1032 MS_U16 reg_mfe_s_marb_lbound_1_high:OUTBUF_HI_BITS; // MIU Lower bound protect for MPEG4 MC obuf 1033 #ifdef _MFE_A3_ 1034 MS_U16 reg_mfe_s_marb_miu_bound_en_1:1; // 1035 #endif 1036 }; 1037 MS_U16 reg5f; 1038 }; 1039 union { 1040 struct { 1041 MS_U16 reg_mfe_s_marb_ubound_2_low:16; // MIU protect for MPEG4 MV obuf 1042 }; 1043 MS_U16 reg60; 1044 }; 1045 union { 1046 struct { 1047 MS_U16 reg_mfe_s_marb_ubound_2_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 MV obuf 1048 }; 1049 MS_U16 reg61; 1050 }; 1051 union { 1052 struct { 1053 MS_U16 reg_mfe_s_marb_lbound_2_low:16; // MIU protect for MPEG4 MV obuf 1054 }; 1055 MS_U16 reg62; 1056 }; 1057 union { 1058 struct { 1059 MS_U16 reg_mfe_s_marb_lbound_2_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 MV obuf 1060 #ifdef _MFE_A3_ 1061 MS_U16 reg_mfe_s_marb_miu_bound_en_2:1; // 1062 #endif 1063 }; 1064 MS_U16 reg63; 1065 }; 1066 union { 1067 struct { 1068 MS_U16 reg_mfe_s_marb_ubound_3_low:16; // MIU protect for MPEG4 GN 1069 }; 1070 MS_U16 reg64; 1071 }; 1072 union { 1073 struct { 1074 MS_U16 reg_mfe_s_marb_ubound_3_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 GN 1075 }; 1076 MS_U16 reg65; 1077 }; 1078 union { 1079 struct { 1080 MS_U16 reg_mfe_s_marb_lbound_3_low:16; // MIU protect for MPEG4 GN 1081 }; 1082 MS_U16 reg66; 1083 }; 1084 union { 1085 struct { 1086 MS_U16 reg_mfe_s_marb_lbound_3_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 GN 1087 #ifdef _MFE_A3_ 1088 MS_U16 reg_mfe_s_marb_miu_bound_en_3:1; // 1089 MS_U16 reg_mfe_s_marb_miu_off:1; // 1090 MS_U16 reg_mfe_s_marb_miu_bound_err:1; // 1091 #endif 1092 }; 1093 MS_U16 reg67; 1094 }; 1095 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 1096 union { 1097 struct { 1098 MS_U16 reg_mfe_s_marb_eimi_block:1; // miu emi/imi block, 0: disable 1099 MS_U16 reg_mfe_s_marb_lbwd_mode:1; // low bandwidth mode, 0: disable 1100 MS_U16 reg_mfe_s_marb_imi_burst_thd:5;//imi write burst bunch up threshold 1101 MS_U16 reg_mfe_s_marb_imi_timeout:3; //imi write burst timeout 1102 MS_U16 reg_mfe_s_marb_imilast_thd:4; //auto mfe2imi_last threshold 1103 MS_U16 reg_mfe_s_prfh_cryc_en:1; // 0: disable prfh_cryc circuit, 1: enable prfh_cryc circuit 1104 MS_U16 reg_mfe_s_prfh_refy_en:1; // 0: disable prfh_refy circuit, 1: enable prfh_refy circuit 1105 }; 1106 MS_U16 reg68; 1107 }; 1108 union { 1109 struct { 1110 MS_U16 reg_mfe_g_pat_gen_init:16; // pattern generation initial value 1111 }; 1112 MS_U16 reg69; 1113 }; 1114 union { 1115 struct { 1116 MS_U16 reg_mfe_s_bspobuf_idx:2; // HW obuf index(0->1->2->3->0->1�K) 1117 // SW obuf index(00->01->11->10->00...) 1118 MS_U16 reg_mfe_s_obuf0_status:1; 1119 MS_U16 reg_mfe_s_obuf1_status:1; 1120 // reg_mfe_s_bspobuf_adr_status:6 {fifo_not_full, fifo_not_empty, enable_obufadr_update, obufadr_update_cnt[2:0]} 1121 MS_U16 obufadr_update_cnt:3; 1122 MS_U16 enable_obufadr_update:1; 1123 MS_U16 fifo_not_empty:1; 1124 MS_U16 fifo_not_full:1; 1125 }; 1126 MS_U16 reg6a; 1127 }; 1128 union { 1129 struct { 1130 MS_U16 reg_mfe_s_marb_imi_sadr_low:16; // imi base address for low bandwidth mode (in 8-byte unit) 1131 }; 1132 MS_U16 reg6b; 1133 }; 1134 union { 1135 struct { 1136 MS_U16 reg_mfe_s_marb_imi_sadr_high:IMIBUF_HI_BITS; 1137 MS_U16 reg_mfe_s_marb_rimi_force:1; 1138 MS_U16 reg_mfe_s_marb_imi_cache_size:2; // imi cache size (0: 32kB, 1:64kB, 2:8kB, 3:16kB) 1139 }; 1140 MS_U16 reg6c; 1141 }; 1142 union { 1143 struct { 1144 MS_U16 reg_mfe_s_marb_imipriority_thd:4; //hardware mfe2imi_priority threshold 1145 MS_U16 reg_mfe_s_marb_imipriority_sw:2; //mfe2imi_priority software programmable 1146 MS_U16 dummy:2; 1147 MS_U16 reg_mfe_s_prfh_cryc_idle_cnt:4; // prfh idle count (x 16T) for prfh_cryc 1148 MS_U16 reg_mfe_s_prfh_refy_idle_cnt:4; // prfh idle count (x 16T) for prfh_refy 1149 }; 1150 MS_U16 reg6d; 1151 }; 1152 #endif 1153 union { 1154 struct { 1155 MS_U16 reg_mfe_s_mbr_qstep_min:7; // qstep min (note: max value of qstep_min is 128 because condition is qstep <= qstep_min) 1156 }; 1157 MS_U16 reg6e; 1158 }; 1159 union { 1160 struct { 1161 MS_U16 reg_mfe_s_mbr_qstep_max:13; // qstep max 1162 }; 1163 MS_U16 reg6f; 1164 }; 1165 union { 1166 struct { 1167 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 1168 MS_U16 reg_mfe_g_debug_mode:7; // debug mode 1169 MS_U16 reg_mfe_g_debug_trig_cycle:9; // wait (8 * reg_mfe_g_debug_trig_cycle) cycles 1170 #else 1171 MS_U16 reg_mfe_g_debug_mode:6; // debug mode 1172 MS_U16 reg_mfe_g_debug_trig_cycle:10; // wait (8 * reg_mfe_g_debug_trig_cycle) cycles 1173 #endif 1174 }; 1175 MS_U16 reg70; 1176 }; 1177 union { 1178 struct { 1179 MS_U16 reg_mfe_g_debug_trig_mbx:9; // debug trigger mbx 1180 }; 1181 MS_U16 reg71; 1182 }; 1183 union { 1184 struct { 1185 MS_U16 reg_mfe_g_debug_trig_mby:9; // debug trigger mby 1186 }; 1187 MS_U16 reg72; 1188 }; 1189 union { 1190 struct { 1191 MS_U16 reg_mfe_g_debug_trig:1; // reg trigger (write one clear) 1192 MS_U16 reg_mfe_g_debug_trig_mode:2; // debug trigger mode; 0/1/2/3: reg_trigger/3rd stage (mbx, mby)/frame start 1193 MS_U16 reg_mfe_g_debug_en:1; // debug enable 1194 MS_U16 reg_mfe_g_crc_mode:4; //'h0: Disable,��hc: bsp obuf, 'hd: mc obuf, 'hd: mc obuf 1195 MS_U16 reg_mfe_g_debug_tcycle_chk_en:1; //enable total cycle check 1196 MS_U16 reg_mfe_g_debug_tcycle_chk_sel:1; //select total cycle and report it on reg_mfe_g_crc_result[15:0] 1197 #if defined(_MFE_M1_)||defined(_MFE_AGATE_) 1198 MS_U16 reg_mfe_g_sw_buffer_mode:1; // 0/1: hw/sw buffer mode 1199 MS_U16 reg_mfe_g_sw_row_done:1; // sw row done (1T clk_jpe) (write one clear) 1200 MS_U16 reg_mfe_g_sw_vs:1; // sw vsync (1T clk_jpe) (write one clear) 1201 MS_U16 reg_mfe_g_pat_gen_en:1; // enable pattern generation 1202 MS_U16 reg_mfe_g_row_down_irq_en:1; // row done irq enable; 0: disable, 1: enable 1203 MS_U16 reg_mfe_g_vs_irq_en:1; // vs irq enable; 0: disable, 1: enable 1204 #endif 1205 }; 1206 MS_U16 reg73; 1207 }; 1208 union { 1209 struct { 1210 MS_U16 reg_mfe_g_debug_state0:16; // "debug state for TXIP/ECDB submodule {txip2q_en, txip2iq_en, txip2mbr_en, txip2zmem_en, txip2dpcm_en, 1211 // txip2mve_en, txip2mcobuf_en, txip2mbldr_en, ecdb2mdc_en, 1212 // ecdb2rlc_en, ecdb2vlc_en, 5'd0}" 1213 }; 1214 MS_U16 reg74; 1215 }; 1216 union { 1217 struct { 1218 MS_U16 reg_mfe_g_debug_state1; // "debug state for ME submodule {3'd0, load_w4_ok, load_w3_ok, load_w2_ok, load_w1_ok, load_w0_ok, 2'd0, 1219 // busy_ime, busy_fme, busy_mesr, busy_iacost, end_this_mb, init_this_mb" 1220 }; 1221 MS_U16 reg75; 1222 }; 1223 union { 1224 struct { 1225 MS_U16 reg_mfe_g_crc_result0:16; // CRC64[15..0] 1226 }; 1227 MS_U16 reg76; 1228 }; 1229 union { 1230 struct { 1231 MS_U16 reg_mfe_g_crc_result1:16; // CRC64[31..16] 1232 }; 1233 MS_U16 reg77; 1234 }; 1235 union { 1236 struct { 1237 MS_U16 reg_mfe_g_crc_result2:16; // CRC64[47..32] 1238 }; 1239 MS_U16 reg78; 1240 }; 1241 union { 1242 struct { 1243 MS_U16 reg_mfe_g_crc_result3:16; // CRC64[63..48] 1244 }; 1245 MS_U16 reg79; 1246 }; 1247 union { 1248 struct { 1249 MS_U16 reg_mfe_g_bist_fail0; 1250 }; 1251 MS_U16 reg7a; 1252 }; 1253 union { 1254 struct { 1255 MS_U16 reg_mfe_g_bist_fail1; 1256 }; 1257 MS_U16 reg7b; 1258 }; 1259 union { 1260 struct { 1261 MS_U16 reg_mfe_g_bist_fail2; 1262 }; 1263 MS_U16 reg7c; 1264 }; 1265 union { 1266 struct { 1267 #ifdef _MFE_M1_ 1268 MS_U16 reg_mfe_s_txip_eco0:1;//0: original, 1: fix mbldr_cry_done, mbldr_crc_done bug 1269 MS_U16 reg_mfe_s_txip_eco1:1; //reserved registers 1270 MS_U16 reg_mfe_rsv0:14; //reserved registers 1271 #elif defined(_MFE_MUJI_) || defined(_MFE_MONET_) || defined(_MFE_MESSI_) || defined(_MFE_MANHATTAN_) || defined(_MFE_MASERATI_) || defined(_MFE_MAXIM_) || defined(_MFE_KANO_) || defined(_MFE_K6_) 1272 MS_U16 reg_mfe_s_txip_eco0:1; //0: fix mbldr_cry_done, mbldr_crc_done bug, 1: original 1273 MS_U16 reg_mfe_s_dummy0:1; 1274 MS_U16 reg_eco_mreq_stallgo:1; 1275 MS_U16 reg_eco_marb_stallgo:1; 1276 MS_U16 reg_mfe_s_dummy1:1; 1277 MS_U16 reg_eco_bsp_stuffing:1; 1278 MS_U16 reg_eco_bsp_rdy_fix:1; 1279 MS_U16 reg_eco_bsp_multi_slice_fix:1; 1280 MS_U16 reg_mfe_s_reserved2:6; 1281 MS_U16 reg_mfe_g_secure_obufadr:1; 1282 MS_U16 reg_mfe_g_secure_miu_sel:1; 1283 #else 1284 MS_U16 reg_mfe_s_txip_eco0:1; //0: original, 1: fix mbldr_cry_done, mbldr_crc_done bug 1285 MS_U16 reg_mfe_s_txip_eco1:1; //reserved registers 1286 MS_U16 reg_eco_mreq_stallgo:1; //reg_eco_mreq_stallgo 1287 MS_U16 reg_eco_marb_stallgo:1; //reg_eco_marb_stallgo 1288 MS_U16 reg_mfe_dummy:2; 1289 MS_U16 reg_eco_bsp_rdy_fix:1; 1290 MS_U16 reg_eco_bsp_multi_slice_fix:1; 1291 MS_U16 reg_mfe_reg7d_dummy2:6; 1292 MS_U16 reg_mfe_g_secure_obufadr:1; 1293 MS_U16 reg_mfe_g_secure_miu_sel:1; 1294 #endif 1295 }; 1296 MS_U16 reg7d; 1297 }; 1298 union { 1299 struct { 1300 MS_U16 reg_mfe_rsv1; 1301 }; 1302 MS_U16 reg7e; 1303 }; 1304 union { 1305 struct { 1306 MS_U16 reg_mfe_rsv2:12; 1307 MS_U16 reg_mfe_s_mcc_prldr_mode:4; 1308 }; 1309 MS_U16 reg7f; 1310 }; 1311 1312 } MFE_REG; 1313 1314 typedef struct _mfe_reg1_ { 1315 // [GLOBAL SETTING] 1316 union { 1317 struct { 1318 MS_U16 reg_mfe_s_pp_en:1; // Video Stabilization Enable, 1: on, 0: off 1319 MS_U16 reg_mfe_s_pp_mw_burst_thd:5; // MI write burst bunch up threshold 1320 MS_U16 reg_mfe_s_pp_mw_timeout:3; // IMI write burst timeout 1321 MS_U16 reg_mfe_s_pp_mw_timeout_ref:1; // IMI write burst timeout count start point 1322 MS_U16 reg_mfe_s_pp_burst_split:2; // 0: disable; N: MIU Request IDLE ��N�� cycles with every last signal 1323 MS_U16 reg_mfe_s_pp_32b_ad_nswap:1; // 32bits miu address not swap. only for 32bits mode 1324 MS_U16 reg_mfe_s_00_dummy:3; // dummy bits 1325 }; 1326 MS_U16 reg00; 1327 }; 1328 union { 1329 struct { 1330 MS_U16 reg_mfe_s_pp_mwlast_thd:5; // auto mfepp2imi_wlast threshold 1331 MS_U16 reg_mfe_s_pp_mwpriority_sw:2; // mfepp2imi_wpriority software programmable 1332 MS_U16 reg_mfe_s_pp_mwpriority_thd:4; // hardware mfepp2imi_wpriority threshold 1333 MS_U16 reg_mfe_s_pp_mrlast_thd:5; // auto mfepp2mi_rlast threshold 1334 }; 1335 MS_U16 reg01; 1336 }; 1337 union { 1338 struct { 1339 MS_U16 reg_mfe_s_pp_mrpriority_sw:2; // mfepp2mi_rpriority software programmable 1340 MS_U16 reg_mfe_s_pp_mrpriority_thd:4; // hardware mfepp2mi_rpriority threshold 1341 MS_U16 reg_mfe_s_02_dummy:10; 1342 }; 1343 MS_U16 reg02; 1344 }; 1345 union { 1346 struct { 1347 MS_U16 reg_mfe_g_pp_buf0_badr_y_low:16; // Current Y IMI buffer 0 base address( 256 bytes aligned ) 1348 }; 1349 MS_U16 reg03; 1350 }; 1351 union { 1352 struct { 1353 MS_U16 reg_mfe_g_pp_buf0_badr_y_high:8; // Current Y IMI buffer 0 base address( 256 bytes aligned ) 1354 }; 1355 MS_U16 reg04; 1356 }; 1357 union { 1358 struct { 1359 MS_U16 reg_mfe_g_pp_buf0_badr_c_low:16; // Current CbCr IMI buffer 0 base address( 256 bytes aligned ) 1360 }; 1361 MS_U16 reg05; 1362 }; 1363 union { 1364 struct { 1365 MS_U16 reg_mfe_g_pp_buf0_badr_c_high:8; // Current CbCr IMI buffer 0 base address( 256 bytes aligned ) 1366 }; 1367 MS_U16 reg06; 1368 }; 1369 union { 1370 struct { 1371 MS_U16 reg_mfe_g_pp_buf1_badr_y_low:16; // Current Y IMI buffer 1 base address( 256 bytes aligned ) 1372 }; 1373 MS_U16 reg07; 1374 }; 1375 union { 1376 struct { 1377 MS_U16 reg_mfe_g_pp_buf1_badr_y_high:8; // Current Y IMI buffer 1 base address( 256 bytes aligned ) 1378 }; 1379 MS_U16 reg08; 1380 }; 1381 union { 1382 struct { 1383 MS_U16 reg_mfe_g_pp_buf1_badr_c_low:16; // Current CbCr IMI buffer 1 base address( 256 bytes aligned ) 1384 }; 1385 MS_U16 reg09; 1386 }; 1387 union { 1388 struct { 1389 MS_U16 reg_mfe_g_pp_buf1_badr_c_high:8; // Current CbCr IMI buffer 1 base address( 256 bytes aligned ) 1390 }; 1391 MS_U16 reg0a; 1392 }; 1393 union { 1394 struct { 1395 MS_U16 reg_mfe_g_mb_pitch:12; // mb pitch (x-direction) 1396 MS_U16 reg_mfe_g_mb_pitch_en:1; // 0: mb pitch off, 1: mb pitch enabled 1397 }; 1398 MS_U16 reg0b; 1399 }; 1400 union { 1401 struct { 1402 MS_U16 reg_mfe_g_capture_width_y:12; // Capture input frame width (Luma Pels) 1403 }; 1404 MS_U16 reg10; 1405 }; 1406 union { 1407 struct { 1408 #if defined(HW_SUPPORT_ANDROID_YV12) 1409 MS_U16 reg_mfe_g_capture_width_c:12; // Capture input frame width (Chroma Pels) 1410 #else 1411 MS_U16 reg_mfe_g_capture_hright_y:12; // Capture input frame height (Luma Pels) 1412 #endif 1413 }; 1414 MS_U16 reg11; 1415 }; 1416 union { 1417 struct { 1418 MS_U16 reg_mfe_g_enc_cury_offset:3; // Encoding frame Y shift 1419 MS_U16 reg_mfe_g_enc_cury_adr_low:13; // Encoding frame Y base address (8 bytes aligned) 1420 }; 1421 MS_U16 reg12; 1422 }; 1423 union { 1424 struct { 1425 MS_U16 reg_mfe_g_enc_cury_adr_high:16; // Encoding frame Y base address (8 bytes aligned) 1426 }; 1427 MS_U16 reg13; 1428 }; 1429 union { 1430 struct { 1431 MS_U16 reg_mfe_g_enc_curcb_offset:3; // Encoding frame Cb shift 1432 MS_U16 reg_mfe_g_enc_curcb_adr_low:13; // Encoding frame Cb base address (8 bytes aligned) 1433 }; 1434 MS_U16 reg14; 1435 }; 1436 union { 1437 struct { 1438 MS_U16 reg_mfe_g_enc_curcb_adr_high:16; // Encoding frame Cb base address (8 bytes aligned) 1439 }; 1440 MS_U16 reg15; 1441 }; 1442 union { 1443 struct { 1444 MS_U16 reg_mfe_g_enc_curcr_offset:3; // Encoding frame Cr shift 1445 MS_U16 reg_mfe_g_enc_curcr_adr_low:13; // Encoding frame Cr base address (8 bytes aligned) 1446 }; 1447 MS_U16 reg16; 1448 }; 1449 union { 1450 struct { 1451 MS_U16 reg_mfe_g_enc_curcr_adr_high:16; // Encoding frame Cr base address (8 bytes aligned) 1452 }; 1453 MS_U16 reg17; 1454 }; 1455 union { 1456 struct { 1457 MS_U16 reg_mfe_s_pp_semiplaner:1; // 0: y, cb, cr palner mode 1: y, cb/cr semiplaner mode 1458 }; 1459 MS_U16 reg18; 1460 }; 1461 union { 1462 struct { 1463 MS_U16 reg_mfe_s_jpe_rst_mcu_cnt_low:16; // JPE MCU count for restart marker 1464 }; 1465 MS_U16 reg20; 1466 }; 1467 union { 1468 struct { 1469 MS_U16 reg_mfe_s_jpe_rst_mcu_cnt_high:10; // JPE MCU count for restart marker 1470 MS_U16 reg_mfe_s_jpe_rst_en:1; // JPE restart marker enable 1471 }; 1472 MS_U16 reg21; 1473 }; 1474 union { 1475 struct { 1476 MS_U16 reg_mfe_s_cabac_bin_count_low:16; // CABAC total bin counts 1477 }; 1478 MS_U16 reg30; 1479 }; 1480 union { 1481 struct { 1482 MS_U16 reg_mfe_s_cabac_bin_count_high:16; // CABAC total bin counts 1483 }; 1484 MS_U16 reg31; 1485 }; 1486 union { 1487 struct { 1488 MS_U16 reg_mfe_s_cabac_bit_count_low:16; // CABAC total bit counts 1489 }; 1490 MS_U16 reg32; 1491 }; 1492 union { 1493 struct { 1494 MS_U16 reg_mfe_s_cabac_bit_count_high:16; // CABAC total bit counts 1495 }; 1496 MS_U16 reg33; 1497 }; 1498 1499 union { 1500 struct { 1501 MS_U16 reg_mfe_s_bspobuf_low:16; // bsp obuf start address 1502 }; 1503 MS_U16 reg34; 1504 }; 1505 union { 1506 struct { 1507 MS_U16 reg_mfe_s_bspobuf_high:(MFE_MIAW-16); // bsp obuf address high 1508 MS_U16 reg35_dummy_bits:(16-(MFE_MIAW-16)-2); 1509 MS_U16 reg_mfe_s_obuf_id:2; // 00: s0, 01: e0, 10: s1, 11: e1 1510 1511 }; 1512 MS_U16 reg35; 1513 }; 1514 union { 1515 struct { 1516 MS_U16 reg_mfe_s_obuf_write_id_adr:1; //write to this address to enable witring of bspobuf address 1517 MS_U16 reg_mfe_miu_sel:2; //select miu bank; 0: bank0, 1:bank1 1518 #if defined(MFE_SUPPORT_TLB) 1519 MS_U16 reg_mfe_tlb:1; // MIU TLB remap enable 1520 MS_U16 reg36_dummy_bits:12; 1521 #else 1522 MS_U16 reg36_dummy_bits:13; 1523 #endif 1524 }; 1525 MS_U16 reg36; 1526 }; 1527 union { 1528 struct { 1529 MS_U16 reg_mfe_g_secure_obufadr:1; // Enable security control (Obuf adr) 1530 MS_U16 reg_mfe_g_secure_miu_sel:1; // Enable security control (MIU sel) 1531 MS_U16 reg37_dummy_bits:14; 1532 }; 1533 MS_U16 reg37; 1534 }; 1535 union { 1536 struct { 1537 MS_U16 reg_mfe_s_secure_bank_sel:1; // select security bank; 0: bank0, 1:bank1 1538 MS_U16 reg38_dummy_bits:15; 1539 }; 1540 MS_U16 reg38; 1541 }; 1542 union { 1543 struct { 1544 MS_U16 reg_mfe_s_whist_en:1; // Write histogram enable 1545 MS_U16 reg_mfe_s_whist_count_range:1; // Write histogram count range or total 1546 MS_U16 reg_mfe_s_whist_mode:2; // Write histogram mode 0: Request count 1: Reserved 2: Latch count 3: Latch count without first data 1547 MS_U16 reg_mfe_s_whist_burst_mode:1; //Write histogram burst count mode 0: Count request 1: Count burs 1548 MS_U16 reg_mfe_s_whist_upper_bound_en:1; //Write histogram upper bound enable 1549 MS_U16 reg_mfe_s_whist_lower_bound_en:1; //Write histogram lower bound enable 1550 MS_U16 reg40_dummy_bits:9; 1551 }; 1552 MS_U16 reg40; 1553 }; 1554 union { 1555 struct { 1556 MS_U16 reg_mfe_s_whist_upper_bound:16; // Write histogram upper bound 1557 }; 1558 MS_U16 reg41; 1559 }; 1560 union { 1561 struct { 1562 MS_U16 reg_mfe_s_whist_lower_bound:16; // Write histogram lower bound 1563 }; 1564 MS_U16 reg42; 1565 }; 1566 union { 1567 struct { 1568 MS_U16 reg_mfe_s_whist_count_bubble:16; // Write histogram bubble count 1569 }; 1570 MS_U16 reg43; 1571 }; 1572 union { 1573 struct { 1574 MS_U16 reg_mfe_s_whist_count_burst:16; // Write histogram burst count 1575 }; 1576 MS_U16 reg44; 1577 }; 1578 union { 1579 struct { 1580 MS_U16 reg_mfe_s_rhist_en:1; // Read histogram enable 1581 MS_U16 reg_mfe_s_rhist_count_range:1; // Read histogram count range or total 1582 MS_U16 reg_mfe_s_rhist_mode:2; // Read histogram mode 0: Request count 1: Reserved 2: Latch count 3: Latch count without first data 1583 MS_U16 reg_mfe_s_rhist_burst_mode:1; //Read histogram burst count mode 0: Count request 1: Count burs 1584 MS_U16 reg_mfe_s_rhist_upper_bound_en:1; //Read histogram upper bound enable 1585 MS_U16 reg_mfe_s_rhist_lower_bound_en:1; //Read histogram lower bound enable 1586 MS_U16 reg45_dummy_bits:9; 1587 }; 1588 MS_U16 reg45; 1589 }; 1590 union { 1591 struct { 1592 MS_U16 reg_mfe_s_rhist_upper_bound:16; // Read histogram upper bound 1593 }; 1594 MS_U16 reg46; 1595 }; 1596 union { 1597 struct { 1598 MS_U16 reg_mfe_s_rhist_lower_bound:16; // Read histogram lower bound 1599 }; 1600 MS_U16 reg47; 1601 }; 1602 union { 1603 struct { 1604 MS_U16 reg_mfe_s_rhist_count_bubble:16; // Read histogram bubble count 1605 }; 1606 MS_U16 reg48; 1607 }; 1608 union { 1609 struct { 1610 MS_U16 reg_mfe_s_rhist_count_burst:16; // Read histogram burst count 1611 }; 1612 MS_U16 reg49; 1613 }; 1614 union { 1615 struct { 1616 MS_U16 reg_mfe_g_jpd_hsk_en:1; // JPD handshake enable 1617 MS_U16 reg_mfe_s_packed422_en:1; // MFE YUV422 input enable 1618 MS_U16 reg_mfe_s_packed422_endian:1; // Endianness of YUV422 1619 MS_U16 reg_mfe_s_packed422_yc_swap:1; // YUV422 YC swap mode 1620 MS_U16 reg_mfe_s_packed422_uv_swap:1; // YUV422 UV swap mode 1621 MS_U16 reg_mfe_s_packed422_delta:8; // 8-bit, Delta between JPD counter and MFE counter 1622 MS_U16 reg_mfe_g_jpd_hsk_shot:1; // Shot for JPD handshake enable 1623 MS_U16 reg_mfe_g_jpd_hsk_mfe:1; // JPD handshake enable in MFE 1624 MS_U16 reg_mfe_g_jpd_frame_done_mask:1; // 0: Monitor JPD framedone when handshake enable 1: Disable JPD framedone monitor 1625 }; 1626 MS_U16 reg52; 1627 }; 1628 1629 #if defined(MFE_YUV_LOADER) 1630 union { 1631 struct { 1632 MS_U16 reg_mfe_g_yuvldr_en:1; // YUV data loader 1633 MS_U16 reg_mfe_g_hevd_tile:1; // EVD tile (32x16) 1634 MS_U16 reg_mfe_g_hevd_tile32:1; // 32x32 tile 1635 MS_U16 reg_mfe_g_yuv420_semi:1; // YUV420 semi-planar 1636 MS_U16 reg_mfe_g_yuv420_semi_uv_swap:1; // YUV420 semi-planar uv-swap 1637 MS_U16 reg56_dummy_bits:11; 1638 }; 1639 MS_U16 reg56; 1640 }; 1641 #endif 1642 } MFE_REG1; 1643 1644 ////////////////////////////////////////////////////////////////////////// 1645 // PERFORMANCE 1646 ////////////////////////////////////////////////////////////////////////// 1647 1648 #define CLOCK_GATING // Enable clock gating 1649 1650 #define FME_PIPELINE_OPEN // Enable David's FME speedup version 1651 1652 //#define DONT_PUT_FDC 1653 1654 ////////////////////////////////////////////////////////////////////////// 1655 // DEBUG Flags: FDC && QTable 1656 ////////////////////////////////////////////////////////////////////////// 1657 1658 //#define CHECK_FDC_DONE // Verify if hw receives the fdc command 1659 1660 //#define CHECK_WriteQTable_DONE // Verify if hw receives the WriteQTable command 1661 1662 //#define QTABLE_READBACK_CHECK // Verify all WriteQTable Value 1663 1664 ////////////////////////////////////////////////////////////////////////// 1665 // DEBUG Flags: StopAndGo series 1666 ////////////////////////////////////////////////////////////////////////// 1667 1668 #define STOP_FRAME 0UL 1669 #define STOP_MBX 7UL 1670 #define STOP_MBY 7UL 1671 // #define TEST_MB_STOPANDGO 1672 // #define TEST_MB_STOPANDDROP 1673 1674 // #define TEST_STOPANDGO 1675 // #define TEST_STOPANDDROP 1676 1677 1678 ////////////////////////////////////////////////////////////////////////// 1679 // DEBUG Flags: test miu protection 1680 ////////////////////////////////////////////////////////////////////////// 1681 1682 1683 #define TEST_MIU_PROTECTION_MODE 0UL 1684 1685 1686 1687 1688 1689 #ifdef REG_JPEG_CMODEL 1690 1691 ////////////////////////////////////////////////////////////////////////// 1692 // DEBUG Flags: continuous shot test (JPEG only) 1693 ////////////////////////////////////////////////////////////////////////// 1694 1695 //#define TEST_CONTINUOUS_SHOT 1696 //#define CONTINUOUS_SHOT_NUMBER 5UL //number of test shot 1697 1698 ////////////////////////////////////////////////////////////////////////// 1699 // DEBUG Flags: input row mode test (JPEG only) 1700 ////////////////////////////////////////////////////////////////////////// 1701 //JPEG row mode only! 1702 // #define TEST_INPUT_ROW_MODE_HW 1703 1704 #ifdef TEST_INPUT_ROW_MODE_HW 1705 #ifndef DONT_PUT_FDC 1706 #define DONT_PUT_FDC 1707 #endif 1708 1709 #define NUM_OF_ROW_DONE_BEFORE_FS 1UL 1710 #endif 1711 1712 //JPEG row mode only! only check fs_fail_irq 1713 //#define TEST_INPUT_ROW_MODE_SW_HW 1714 #ifdef TEST_INPUT_ROW_MODE_SW_HW 1715 #define NUM_OF_ROW_DONE_BEFORE_FS 1UL 1716 #endif 1717 #endif // REG_JPEG_CMODEL 1718 ////////////////////////////////////////////////////////////////////////// 1719 // DEBUG Flags: test CRC mode 1720 ////////////////////////////////////////////////////////////////////////// 1721 #define TEST_CRC_MODE 1722 1723 #endif 1724 1725