1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __RVE_REG_H__ 3 #define __RVE_REG_H__ 4 5 #include "rve_drv.h" 6 7 /* sys reg */ 8 #define RVE_SWREG0_IVE_VERSION 0x000 9 #define RVE_SWREG1_IVE_IRQ 0x004 10 #define RVE_SWREG2_IRQ_CTRL 0x008 11 #define RVE_SWREG3_IVE_IDLE_PRC_STA 0x00c 12 #define RVE_SWREG4_IVE_FORCE_IDLE_WBASE 0x010 13 #define RVE_SWREG5_IVE_IDLE_CTRL 0x014 14 #define RVE_SWREG6_IVE_WORK_STA 0x018 15 #define RVE_SWREG7_IVE_SWAP 0x01c 16 17 /* llp reg */ 18 #define RVE_SWLTB0_START_BASE 0x100 19 #define RVE_SWLTB1_CTRL 0x104 20 #define RVE_SWLTB2_CFG_DONE 0x108 21 #define RVE_SWLTB3_ENABLE 0x10c 22 #define RVE_SWLTB4_PAUSE_CTRL 0x110 23 #define RVE_SWLTB5_DECODED_NUM 0x114 24 #define RVE_SWLTB6_SKIP_NUM 0x118 25 #define RVE_SWLTB7_TOTAL_NUM 0x11c 26 #define RVE_SWLTB8_LAST_FRAME_BASE 0x120 27 #define RVE_SWLTB9_LAST_IDX 0x124 28 29 /* op reg */ 30 #define RVE_SWCFG0_EN 0x200 31 #define RVE_SWCFG4_OPERATOR 0x210 32 #define RVE_SWCFG5_CTRL 0x214 33 #define RVE_SWCFG6_TIMEOUT_THRESH 0x218 34 #define RVE_SWCFG7_DDR_CTRL 0x21c 35 #define RVE_SWCFG9_PIC_INFO 0x224 36 #define RVE_SWCFG10_HOR_STRIDE0 0x228 37 #define RVE_SWCFG11_HOR_STRIDE1 0x22c 38 #define RVE_SWCFG12_SRC0_BASE 0x230 39 #define RVE_SWCFG13_SRC1_BASE 0x234 40 #define RVE_SWCFG14_SRC2_BASE 0x238 41 #define RVE_SWCFG15_SRC3_BASE 0x23c 42 #define RVE_SWCFG16_DST0_BASE 0x240 43 #define RVE_SWCFG17_DST1_BASE 0x244 44 #define RVE_SWCFG18_DST2_BASE 0x248 45 #define RVE_SWCFG20_OP_CTRL0 0x250 46 #define RVE_SWCFG21_OP_CTRL1 0x254 47 #define RVE_SWCFG22_OP_CTRL2 0x258 48 #define RVE_SWCFG23_OP_CTRL3 0x25c 49 #define RVE_SWCFG24_OP_CTRL4 0x260 50 #define RVE_SWCFG25_OP_CTRL5 0x264 51 #define RVE_SWCFG26_OP_CTRL6 0x268 52 #define RVE_SWCFG27_OP_CTRL7 0x26c 53 #define RVE_SWCFG28_OP_CTRL8 0x270 54 #define RVE_SWCFG29_OP_CTRL9 0x274 55 56 /* monitor reg */ 57 #define RVE_SWCFG32_MONITOR_CTRL0 0x280 58 #define RVE_SWCFG33_MONITOR_CTRL1 0x284 59 #define RVE_SWCFG34_MONITOR_INFO0 0x288 60 #define RVE_SWCFG35_MONITOR_INFO1 0x28c 61 #define RVE_SWCFG36_MONITOR_INFO2 0x290 62 #define RVE_SWCFG37_MONITOR_INFO3 0x294 63 #define RVE_SWCFG38_MONITOR_INFO4 0x298 64 #define RVE_SWCFG39_MONITOR_INFO5 0x29c 65 66 /* mmu reg */ 67 68 /* common reg */ 69 #define RVE_SYS_REG 0x000 70 #define RVE_LTB_REG 0x100 71 #define RVE_CFG_REG 0x200 72 #define RVE_MMU_REG 0x300 73 74 /* mode value */ 75 #define RVE_LLP_MODE 0x8000 76 #define RVE_LLP_DONE 0x11 77 #define RVE_CLEAR_UP_REG6_WROK_STA 0xff0000 78 79 void rve_soft_reset(struct rve_scheduler_t *scheduler); 80 int rve_set_reg(struct rve_job *job, struct rve_scheduler_t *scheduler); 81 int rve_init_reg(struct rve_job *job); 82 int rve_get_version(struct rve_scheduler_t *scheduler); 83 84 void rve_dump_read_back_reg(struct rve_scheduler_t *scheduler); 85 void rve_get_monitor_info(struct rve_job *job); 86 87 #endif 88 89