1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1103B_H 8 #define _ASM_ARCH_CRU_RV1103B_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 #define RC_OSC_HZ (125 * MHz) 16 17 #define GPLL_HZ (1188 * MHz) 18 19 /* RV1103B pll id */ 20 enum rv1103b_pll_id { 21 GPLL, 22 PLL_COUNT, 23 }; 24 25 struct rv1103b_clk_info { 26 unsigned long id; 27 char *name; 28 bool is_cru; 29 }; 30 31 struct rv1103b_clk_priv { 32 struct rv1103b_cru *cru; 33 struct rv1103b_grf *grf; 34 ulong gpll_hz; 35 ulong armclk_hz; 36 ulong armclk_enter_hz; 37 ulong armclk_init_hz; 38 bool sync_kernel; 39 bool set_armclk_rate; 40 }; 41 42 struct rv1103b_grf_clk_priv { 43 struct rv1103b_grf *grf; 44 }; 45 46 struct rv1103b_pll { 47 unsigned int con0; 48 unsigned int con1; 49 unsigned int con2; 50 unsigned int con3; 51 unsigned int con4; 52 unsigned int reserved0[3]; 53 }; 54 55 struct rv1103b_cru { 56 unsigned int reserved0[192]; 57 unsigned int peri_clksel_con[4]; 58 unsigned int reserved1[316]; 59 unsigned int peri_clkgate_con[12]; 60 unsigned int reserved2[116]; 61 unsigned int peri_softrst_con[12]; 62 unsigned int reserved3[15924]; 63 unsigned int vepu_clksel_con[3]; 64 unsigned int reserved4[317]; 65 unsigned int vepu_clkgate_con[1]; 66 unsigned int reserved5[127]; 67 unsigned int vepu_softrst_con[1]; 68 unsigned int reserved6[15935]; 69 unsigned int npu_clksel_con[3]; 70 unsigned int reserved7[317]; 71 unsigned int npu_clkgate_con[1]; 72 unsigned int reserved8[127]; 73 unsigned int npu_softrst_con[1]; 74 unsigned int reserved9[15935]; 75 unsigned int vi_clksel_con[1]; 76 unsigned int reserved10[319]; 77 unsigned int vi_clkgate_con[3]; 78 unsigned int reserved11[125]; 79 unsigned int vi_softrst_con[3]; 80 unsigned int reserved12[15933]; 81 unsigned int core_clksel_con[3]; 82 unsigned int reserved13[16381]; 83 unsigned int ddr_clksel_con[1]; 84 unsigned int reserved14[16207]; 85 struct rv1103b_pll pll[2]; 86 unsigned int reserved15[128]; 87 unsigned int mode; 88 unsigned int reserved16[31]; 89 unsigned int clksel_con[42]; 90 unsigned int reserved17[278]; 91 unsigned int clkgate_con[7]; 92 unsigned int reserved18[121]; 93 unsigned int softrst_con[1]; 94 unsigned int reserved19[127]; 95 unsigned int glb_cnt_th; 96 unsigned int glb_rst_st; 97 unsigned int glb_srst_fst; 98 unsigned int glb_srst_snd; 99 unsigned int glb_rst_con; 100 unsigned int reserved20[15803]; 101 unsigned int pmu_clksel_con[3]; 102 unsigned int reserved21[317]; 103 unsigned int pmu_clkgate_con[3]; 104 unsigned int reserved22[125]; 105 unsigned int pmu_softrst_con[3]; 106 unsigned int reserved23[15933]; 107 unsigned int pmu1_clksel_con[1]; 108 unsigned int reserved24[319]; 109 unsigned int pmu1_clkgate_con[2]; 110 unsigned int reserved25[126]; 111 unsigned int pmu1_softrst_con[2]; 112 }; 113 check_member(rv1103b_cru, pmu1_softrst_con[1], 0x80a04); 114 115 struct pll_rate_table { 116 unsigned long rate; 117 unsigned int fbdiv; 118 unsigned int postdiv1; 119 unsigned int refdiv; 120 unsigned int postdiv2; 121 unsigned int dsmpd; 122 unsigned int frac; 123 }; 124 125 #define RV1103B_TOPCRU_BASE 0x60000 126 #define RV1103B_PERICRU_BASE 0x0 127 #define RV1103B_VICRU_BASE 0x30000 128 #define RV1103B_NPUCRU_BASE 0x20000 129 #define RV1103B_CORECRU_BASE 0x40000 130 #define RV1103B_VEPUCRU_BASE 0x10000 131 #define RV1103B_DDRCRU_BASE 0x50000 132 #define RV1103B_SUBDDRCRU_BASE 0x58000 133 #define RV1103B_PMUCRU_BASE 0x70000 134 #define RV1103B_PMU1CRU_BASE 0x80000 135 136 #define RV1103B_CRU_BASE 0x20000000 137 138 #define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE) 139 #define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE) 140 #define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE) 141 #define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE) 142 143 enum { 144 /* CORECRU_CLK_SEL0_CON */ 145 CLK_CORE_SRC_SEL_SHIFT = 1, 146 CLK_CORE_SRC_SEL_MASK = 0x1 << CLK_CORE_SRC_SEL_SHIFT, 147 CLK_CORE_SRC_SEL_GPLL = 0, 148 CLK_CORE_SRC_SEL_PVTPLL, 149 150 /* CRU_PERI_CLK_SEL0_CON */ 151 CLK_TSADC_TSEN_DIV_SHIFT = 10, 152 CLK_TSADC_TSEN_DIV_MASK = 0x1f << CLK_TSADC_TSEN_DIV_SHIFT, 153 CLK_TSADC_DIV_SHIFT = 4, 154 CLK_TSADC_DIV_MASK = 0x1f << CLK_TSADC_DIV_SHIFT, 155 PCLK_PERI_DIV_SHIFT = 0, 156 PCLK_PERI_DIV_MASK = 0x3 << PCLK_PERI_DIV_SHIFT, 157 158 /* CRU_PERI_CLK_SEL1_CON */ 159 CLK_SARADC_DIV_SHIFT = 0, 160 CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, 161 162 /* CRU_CLK_SEL5_CON */ 163 CLK_UART2_SRC_DIV_SHIFT = 10, 164 CLK_UART2_SRC_DIV_MASK = 0x1f << CLK_UART2_SRC_DIV_SHIFT, 165 CLK_UART1_SRC_DIV_SHIFT = 5, 166 CLK_UART1_SRC_DIV_MASK = 0x1f << CLK_UART1_SRC_DIV_SHIFT, 167 CLK_UART0_SRC_DIV_SHIFT = 0, 168 CLK_UART0_SRC_DIV_MASK = 0x1f << CLK_UART0_SRC_DIV_SHIFT, 169 170 /* CRU_CLK_SEL10_CON */ 171 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 172 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 173 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 174 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 175 176 /* CRU_CLK_SEL31_CON */ 177 CLK_EMMC_SEL_SHIFT = 15, 178 CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT, 179 ACLK_PERI_SEL_SHIFT = 10, 180 ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT, 181 ACLK_PERI_SEL_600M = 0, 182 ACLK_PERI_SEL_480M, 183 ACLK_PERI_SEL_400M, 184 LSCLK_PERI_SEL_SHIFT = 9, 185 LSCLK_PERI_SEL_MASK = 0x1 << LSCLK_PERI_SEL_SHIFT, 186 LSCLK_PERI_SEL_300M = 0, 187 LSCLK_PERI_SEL_200M, 188 CLK_EMMC_DIV_SHIFT = 0, 189 CLK_EMMC_DIV_MASK = 0xff << CLK_EMMC_DIV_SHIFT, 190 191 /* CRU_CLK_SEL32_CON */ 192 CLK_SDMMC_SEL_SHIFT = 15, 193 CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT, 194 CLK_MMC_SEL_GPLL = 0, 195 CLK_MMC_SEL_OSC, 196 CLK_UART2_SEL_SHIFT = 12, 197 CLK_UART2_SEL_MASK = 3 << CLK_UART2_SEL_SHIFT, 198 CLK_UART1_SEL_SHIFT = 10, 199 CLK_UART1_SEL_MASK = 3 << CLK_UART1_SEL_SHIFT, 200 CLK_UART0_SEL_SHIFT = 8, 201 CLK_UART0_SEL_MASK = 3 << CLK_UART0_SEL_SHIFT, 202 CLK_UART_SEL_SRC = 0, 203 CLK_UART_SEL_FRAC, 204 CLK_UART_SEL_OSC, 205 CLK_SDMMC_DIV_SHIFT = 0, 206 CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT, 207 208 /* CRU_CLK_SEL33_CON */ 209 CLK_SFC_SEL_SHIFT = 15, 210 CLK_SFC_SEL_MASK = 0x1 << CLK_SFC_SEL_SHIFT, 211 CLK_SFC_DIV_SHIFT = 0, 212 CLK_SFC_DIV_MASK = 0xff << CLK_SFC_DIV_SHIFT, 213 214 /* CRU_CLK_SEL34_CON */ 215 CLK_PWM2_SEL_SHIFT = 14, 216 CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, 217 CLK_PWM1_SEL_SHIFT = 13, 218 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, 219 CLK_PWM0_SEL_SHIFT = 12, 220 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 221 CLK_PWM_SEL_100M = 0, 222 CLK_PWM_SEL_24M, 223 CLK_SPI0_SEL_SHIFT = 2, 224 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 225 CLK_SPI0_SEL_200M = 0, 226 CLK_SPI0_SEL_100M, 227 CLK_SPI0_SEL_50M, 228 CLK_SPI0_SEL_24M, 229 CLK_I2C1_SEL_SHIFT = 1, 230 CLK_I2C1_SEL_MASK = 0x1 << CLK_I2C1_SEL_SHIFT, 231 CLK_I2C0_SEL_SHIFT = 0, 232 CLK_I2C0_SEL_MASK = 0x1 << CLK_I2C0_SEL_SHIFT, 233 CLK_I2C_SEL_100M = 0, 234 CLK_I2C_SEL_24M, 235 236 /* CRU_CLK_SEL35_CON */ 237 CLK_PKA_CRYPTO_SEL_SHIFT = 4, 238 CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 239 CLK_CORE_CRYPTO_SEL_SHIFT = 2, 240 CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 241 CLK_CORE_CRYPTO_SEL_300M = 0, 242 CLK_CORE_CRYPTO_SEL_200M, 243 CLK_CORE_CRYPTO_SEL_100M, 244 DCLK_DECOM_SEL_SHIFT = 0, 245 DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT, 246 DCLK_DECOM_SEL_480M = 0, 247 DCLK_DECOM_SEL_400M, 248 DCLK_DECOM_SEL_300M, 249 250 /* CRU_CLK_SEL37_CON */ 251 CLK_CORE_GPLL_DIV_SHIFT = 13, 252 CLK_CORE_GPLL_DIV_MASK = 0x7 << CLK_CORE_GPLL_DIV_SHIFT, 253 CLK_CORE_GPLL_SEL_SHIFT = 12, 254 CLK_CORE_GPLL_SEL_MASK = 0x1 << CLK_CORE_GPLL_SEL_SHIFT, 255 CLK_CORE_GPLL_SEL_GPLL = 0, 256 CLK_CORE_GPLL_SEL_OSC, 257 258 /* CRU_PMU_CLK_SEL2_CON */ 259 LSCLK_PMU_SEL_SHIFT = 4, 260 LSCLK_PMU_SEL_MASK = 0x1 << LSCLK_PMU_SEL_SHIFT, 261 LSCLK_PMU_SEL_24M = 0, 262 LSCLK_PMU_SEL_RC_OSC, 263 LSCLK_PMU_DIV_SHIFT = 0, 264 LSCLK_PMU_DIV_MASK = 0x3 << LSCLK_PMU_DIV_SHIFT, 265 266 }; 267 #endif 268