1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "rpi_hw.h" 16 17 /* Special value used to verify platform parameters from BL2 to BL31 */ 18 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) 19 20 #define PLATFORM_STACK_SIZE ULL(0x1000) 21 22 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 23 #define PLATFORM_CLUSTER_COUNT U(1) 24 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 25 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 26 27 #define RPI_PRIMARY_CPU U(0) 28 29 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 30 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 31 PLATFORM_CORE_COUNT) 32 33 #define PLAT_MAX_RET_STATE U(1) 34 #define PLAT_MAX_OFF_STATE U(2) 35 36 /* Local power state for power domains in Run state. */ 37 #define PLAT_LOCAL_STATE_RUN U(0) 38 /* Local power state for retention. Valid only for CPU power domains */ 39 #define PLAT_LOCAL_STATE_RET U(1) 40 /* 41 * Local power state for OFF/power-down. Valid for CPU and cluster power 42 * domains. 43 */ 44 #define PLAT_LOCAL_STATE_OFF U(2) 45 46 /* 47 * Macros used to parse state information from State-ID if it is using the 48 * recommended encoding for State-ID. 49 */ 50 #define PLAT_LOCAL_PSTATE_WIDTH U(4) 51 #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 52 53 /* 54 * Some data must be aligned on the biggest cache line size in the platform. 55 * This is known only to the platform as it might have a combination of 56 * integrated and external caches. 57 */ 58 #define CACHE_WRITEBACK_SHIFT U(6) 59 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 60 61 /* 62 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and 63 * secure DRAM. Note that this is all actually DRAM with different names, 64 * there is no Secure RAM in the Raspberry Pi 3. 65 */ 66 #if RPI3_USE_UEFI_MAP 67 #define SEC_ROM_BASE ULL(0x00000000) 68 #define SEC_ROM_SIZE ULL(0x00010000) 69 70 /* FIP placed after ROM to append it to BL1 with very little padding. */ 71 #define PLAT_RPI3_FIP_BASE ULL(0x00010000) 72 #define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00020000) 73 74 /* Reserve 2M of secure SRAM and DRAM, starting at 2M */ 75 #define SEC_SRAM_BASE ULL(0x00200000) 76 #define SEC_SRAM_SIZE ULL(0x00100000) 77 78 #define SEC_DRAM0_BASE ULL(0x00300000) 79 #define SEC_DRAM0_SIZE ULL(0x00100000) 80 81 /* Windows on ARM requires some RAM at 4M */ 82 #define NS_DRAM0_BASE ULL(0x00400000) 83 #define NS_DRAM0_SIZE ULL(0x00C00000) 84 #else 85 #define SEC_ROM_BASE ULL(0x00000000) 86 #define SEC_ROM_SIZE ULL(0x00020000) 87 88 /* FIP placed after ROM to append it to BL1 with very little padding. */ 89 #define PLAT_RPI3_FIP_BASE ULL(0x00020000) 90 #define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000) 91 92 /* We have 16M of memory reserved starting at 256M */ 93 #define SEC_SRAM_BASE ULL(0x10000000) 94 #define SEC_SRAM_SIZE ULL(0x00100000) 95 96 #define SEC_DRAM0_BASE ULL(0x10100000) 97 #define SEC_DRAM0_SIZE ULL(0x00F00000) 98 /* End of reserved memory */ 99 100 #define NS_DRAM0_BASE ULL(0x11000000) 101 #define NS_DRAM0_SIZE ULL(0x02000000) 102 #endif /* RPI3_USE_UEFI_MAP */ 103 104 #if TRANSFER_LIST 105 #define FW_NS_HANDOFF_BASE NS_DRAM0_BASE 106 #endif 107 /* 108 * BL33 entrypoint. 109 */ 110 #define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE + FW_HANDOFF_SIZE 111 #define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE - FW_HANDOFF_SIZE 112 113 /* 114 * I/O registers. 115 */ 116 #define DEVICE0_BASE RPI_IO_BASE 117 #define DEVICE0_SIZE RPI_IO_SIZE 118 119 /* 120 * Arm TF lives in SRAM, partition it here 121 */ 122 #define SHARED_RAM_BASE SEC_SRAM_BASE 123 #define SHARED_RAM_SIZE ULL(0x00001000) 124 125 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 126 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 127 128 /* 129 * Mailbox to control the secondary cores.All secondary cores are held in a wait 130 * loop in cold boot. To release them perform the following steps (plus any 131 * additional barriers that may be needed): 132 * 133 * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT; 134 * *entrypoint = ADDRESS_TO_JUMP_TO; 135 * 136 * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; 137 * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO; 138 * 139 * sev(); 140 */ 141 #define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 142 143 /* The secure entry point to be used on warm reset by all CPUs. */ 144 #define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE 145 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) 146 147 /* Hold entries for each CPU. */ 148 #define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \ 149 PLAT_RPI3_TM_ENTRYPOINT_SIZE) 150 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8) 151 #define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \ 152 PLATFORM_CORE_COUNT) 153 154 #define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \ 155 PLAT_RPI3_TM_HOLD_SIZE) 156 157 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0) 158 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1) 159 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2) 160 161 /* 162 * BL1 specific defines. 163 * 164 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 165 * addresses. 166 * 167 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 168 * the current BL1 RW debug size plus a little space for growth. 169 */ 170 #define PLAT_MAX_BL1_RW_SIZE ULL(0x12000) 171 172 #define BL1_RO_BASE SEC_ROM_BASE 173 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 174 #define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE) 175 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 176 177 /* 178 * In order to access the TCG Event Log in BL2, we need to expose the BL1_RW region 179 * where the log resides. 180 */ 181 #if !TRANSFER_LIST 182 #define RPI3_MAP_BL1_RW \ 183 MAP_REGION_FLAT(BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \ 184 MT_MEMORY | MT_RW | MT_SECURE) 185 #endif /* !TRANSFER_LIST */ 186 187 /* 188 * BL2 specific defines. 189 * 190 * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug 191 * size plus a little space for growth. 192 */ 193 #define PLAT_MAX_BL2_SIZE ULL(0x2C000) 194 195 #define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE) 196 #define BL2_LIMIT BL31_BASE 197 198 /* 199 * BL31 specific defines. 200 * 201 * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the 202 * current BL31 debug size plus a little space for growth. 203 */ 204 #define PLAT_MAX_BL31_SIZE ULL(0x20000) 205 206 #define BL31_BASE (BL31_LIMIT - PLAT_MAX_BL31_SIZE) 207 #if TRANSFER_LIST 208 #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - FW_HANDOFF_SIZE) 209 #else 210 #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 211 #endif 212 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 213 214 #if TRANSFER_LIST 215 #define FW_HANDOFF_BASE BL31_LIMIT 216 #define FW_HANDOFF_LIMIT (FW_HANDOFF_BASE + FW_HANDOFF_SIZE) 217 #define FW_HANDOFF_SIZE UL(0x1000) 218 #else 219 #define FW_HANDOFF_SIZE 0 220 #endif 221 /* 222 * BL32 specific defines. 223 * 224 * BL32 can execute from Secure SRAM or Secure DRAM. 225 */ 226 #define BL32_SRAM_BASE BL_RAM_BASE 227 #define BL32_SRAM_LIMIT BL31_BASE 228 #define BL32_DRAM_BASE SEC_DRAM0_BASE 229 #define BL32_DRAM_LIMIT (SEC_DRAM0_BASE + SEC_DRAM0_SIZE) 230 231 #ifdef SPD_opteed 232 /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 233 #define RPI3_OPTEE_PAGEABLE_LOAD_SIZE 0x080000 /* 512KB */ 234 #define RPI3_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - \ 235 RPI3_OPTEE_PAGEABLE_LOAD_SIZE) 236 #endif 237 238 #define SEC_SRAM_ID 0 239 #define SEC_DRAM_ID 1 240 241 #if RPI3_BL32_RAM_LOCATION_ID == SEC_SRAM_ID 242 # define BL32_MEM_BASE BL_RAM_BASE 243 # define BL32_MEM_SIZE BL_RAM_SIZE 244 # define BL32_BASE BL32_SRAM_BASE 245 # define BL32_LIMIT BL32_SRAM_LIMIT 246 #elif RPI3_BL32_RAM_LOCATION_ID == SEC_DRAM_ID 247 # define BL32_MEM_BASE SEC_DRAM0_BASE 248 # define BL32_MEM_SIZE SEC_DRAM0_SIZE 249 # define BL32_BASE BL32_DRAM_BASE 250 # define BL32_LIMIT BL32_DRAM_LIMIT 251 #else 252 # error "Unsupported RPI3_BL32_RAM_LOCATION_ID value" 253 #endif 254 #define BL32_SIZE (BL32_LIMIT - BL32_BASE) 255 256 #ifdef SPD_none 257 #undef BL32_BASE 258 #endif /* SPD_none */ 259 260 /* 261 * Other memory-related defines. 262 */ 263 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 264 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 265 266 #define MAX_MMAP_REGIONS 8 267 #define MAX_XLAT_TABLES 4 268 269 #define MAX_IO_DEVICES U(3) 270 #define MAX_IO_HANDLES U(4) 271 272 #define MAX_IO_BLOCK_DEVICES U(1) 273 274 /* 275 * Serial-related constants. 276 */ 277 #define PLAT_RPI_MINI_UART_BASE RPI3_MINI_UART_BASE 278 #define PLAT_RPI_PL011_UART_BASE RPI3_PL011_UART_BASE 279 #define PLAT_RPI_PL011_UART_CLOCK RPI3_PL011_UART_CLOCK 280 #define PLAT_RPI_UART_BAUDRATE ULL(115200) 281 #define PLAT_RPI_CRASH_UART_BASE PLAT_RPI_MINI_UART_BASE 282 283 /* 284 * System counter 285 */ 286 #define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000) 287 288 /* 289 * TCG Event Log 290 */ 291 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 292 293 /* 294 * NT_FW_CONFIG magic dram addr and max size 295 */ 296 #define PLAT_RPI3_DTO_BASE ULL(0x11530000) 297 #define PLAT_RPI3_DTO_MAX_SIZE ULL(0x001000) 298 299 #endif /* PLATFORM_DEF_H */ 300