1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip HDMI/DP Combo PHY with Samsung IP block
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <generic-phy.h>
11 #include <reset.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <asm/io.h>
15 #include <linux/bitfield.h>
16 #include <linux/iopoll.h>
17 #include <asm/arch/clock.h>
18
19 #define HDPTXPHY_GRF_CON0 0x0000
20 #define RO_REF_CLK_SEL GENMASK(11, 10)
21 #define LC_REF_CLK_SEL GENMASK(9, 8)
22 #define PLL_EN BIT(7)
23 #define BIAS_EN BIT(6)
24 #define BGR_EN BIT(5)
25 #define HDPTX_MODE_SEL BIT(0)
26 #define HDPTXPHY_GRF_STATUS0 0x0080
27 #define PLL_LOCK_DONE BIT(3)
28 #define PHY_CLK_RDY BIT(2)
29 #define PHY_RDY BIT(1)
30 #define SB_RDY BIT(0)
31
32 /* cmn_reg0008 */
33 #define OVRD_LCPLL_EN BIT(7)
34 #define LCPLL_EN BIT(6)
35
36 /* cmn_reg003C */
37 #define ANA_LCPLL_RESERVED7 BIT(7)
38
39 /* cmn_reg003D */
40 #define OVRD_ROPLL_EN BIT(7)
41 #define ROPLL_EN BIT(6)
42
43 /* cmn_reg0046 */
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0)
46
47 /* cmn_reg0047 */
48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
50
51 /* cmn_reg004E */
52 #define ANA_ROPLL_PI_EN BIT(5)
53
54 /* cmn_reg0051 */
55 #define ROPLL_PMS_MDIV GENMASK(7, 0)
56
57 /* cmn_reg0055 */
58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0)
59
60 /* cmn_reg0059 */
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0)
63
64 /* cmn_reg005A */
65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0)
67
68 /* cmn_reg005B */
69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0)
71
72 /* cmn_reg005D */
73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5)
74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
75
76 /* cmn_reg005E */
77 #define ANA_ROPLL_SDM_EN BIT(6)
78 #define OVRD_ROPLL_SDM_RSTN BIT(5)
79 #define ROPLL_SDM_RSTN BIT(4)
80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3)
81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2)
82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1)
83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0)
84
85 /* cmn_reg005F */
86 #define OVRD_ROPLL_SDC_RSTN BIT(5)
87 #define ROPLL_SDC_RSTN BIT(4)
88
89 /* cmn_reg0060 */
90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0)
91
92 /* cmn_reg0064 */
93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3)
94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2)
95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1)
96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0)
97
98 /* cmn_reg0065 */
99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0)
100
101 /* cmn_reg0069 */
102 #define ROPLL_SDC_N_RBR GENMASK(2, 0)
103
104 /* cmn_reg006A */
105 #define ROPLL_SDC_N_HBR GENMASK(5, 3)
106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0)
107
108 /* cmn_reg006B */
109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1)
110
111 /* cmn_reg006C */
112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0)
113
114 /* cmn_reg0070 */
115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0)
116
117 /* cmn_reg0074 */
118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3)
119 #define ROPLL_SDC_NDIV_RSTN BIT(2)
120 #define OVRD_ROPLL_SSC_EN BIT(1)
121 #define ROPLL_SSC_EN BIT(0)
122
123 /* cmn_reg0075 */
124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0)
125
126 /* cmn_reg0076 */
127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2)
128
129 /* cmn_reg0077 */
130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3)
131
132 /* cmn_reg0081 */
133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3)
134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1)
135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0)
136
137 /* cmn_reg0082 */
138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0)
139
140 /* cmn_reg0083 */
141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5)
142
143 /* cmn_reg0084 */
144 #define PLL_LCRO_CLK_SEL BIT(5)
145
146 /* cmn_reg0085 */
147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0)
148
149 /* cmn_reg0087 */
150 #define ANA_PLL_TX_HS_CLK_EN BIT(2)
151
152 /* cmn_reg0095 */
153 #define DP_TX_LINK_BW GENMASK(1, 0)
154
155 /* cmn_reg0097 */
156 #define DIG_CLK_SEL BIT(1)
157
158 /* cmn_reg0099 */
159 #define SSC_EN GENMASK(7, 6)
160 #define CMN_ROPLL_ALONE_MODE BIT(2)
161
162 /* cmn_reg009A */
163 #define HS_SPEED_SEL BIT(0)
164
165 /* cmn_reg009B */
166 #define LS_SPEED_SEL BIT(4)
167
168 /* sb_reg0102 */
169 #define OVRD_SB_RXTERM_EN BIT(5)
170 #define SB_RXRERM_EN BIT(4)
171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0)
172
173 /* sb_reg0103 */
174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3)
175 #define OVRD_SB_RX_RESCAL_DONE BIT(1)
176 #define SB_RX_RESCAL_DONE BIT(0)
177
178 /* sb_reg0104 */
179 #define OVRD_SB_EN BIT(5)
180 #define SB_EN BIT(4)
181 #define OVRD_SB_AUX_EN BIT(1)
182 #define SB_AUX_EN BIT(0)
183
184 /* sb_reg0105 */
185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0)
186
187 /* sb_reg0106 */
188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4)
189
190 /* sb_reg010D */
191 #define ANA_SB_DMRX_LPBK_DATA BIT(4)
192
193 /* sb_reg010F */
194 #define OVRD_SB_VREG_EN BIT(7)
195 #define SB_VREG_EN BIT(6)
196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0)
197
198 /* sb_reg0110 */
199 #define ANA_SB_VREG_OUT_SEL BIT(1)
200 #define ANA_SB_VREG_REF_SEL BIT(0)
201
202 /* sb_reg0113 */
203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4)
204 #define SB_RX_RTERM_CTRL GENMASK(3, 0)
205
206 /* sb_reg0114 */
207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3)
208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0)
209
210 /* sb_reg0115 */
211 #define SB_READY_DELAY_TIME GENMASK(5, 3)
212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0)
213
214 /* sb_reg0116 */
215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4)
216
217 /* sb_reg0117 */
218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0)
219
220 /* sb_reg0118 */
221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0)
222
223 /* sb_reg011A */
224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0)
225
226 /* sb_reg011B */
227 #define SB_EARC_SIG_DET_BYPASS BIT(4)
228 #define SB_AFC_TOL GENMASK(3, 0)
229
230 /* sb_reg011C */
231 #define SB_AFC_STB_NUM GENMASK(3, 0)
232
233 /* sb_reg011D */
234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0)
235
236 /* sb_reg011E */
237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0)
238
239 /* sb_reg011F */
240 #define SB_PWM_AFC_CTRL GENMASK(7, 2)
241 #define SB_RCAL_RSTN BIT(1)
242
243 /* sb_reg0120 */
244 #define SB_AUX_EN_IN BIT(7)
245
246 /* sb_reg0123 */
247 #define OVRD_SB_READY BIT(5)
248 #define SB_READY BIT(4)
249
250 /* lntop_reg0200 */
251 #define PROTOCOL_SEL BIT(2)
252
253 /* lntop_reg0206 */
254 #define DATA_BUS_WIDTH GENMASK(2, 1)
255 #define BUS_WIDTH_SEL BIT(0)
256
257 /* lntop_reg0207 */
258 #define LANE_EN GENMASK(3, 0)
259
260 /* lane_reg0301 */
261 #define OVRD_LN_TX_DRV_EI_EN BIT(7)
262 #define LN_TX_DRV_EI_EN BIT(6)
263
264 /* lane_reg0303 */
265 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5)
266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0)
267
268 /* lane_reg0304 */
269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4)
270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0)
271
272 /* lane_reg0305 */
273 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6)
274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2)
275
276 /* lane_reg0306 */
277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5)
278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2)
279 #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0)
280
281 /* lane_reg0307 */
282 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6)
283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3)
284
285 /* lane_reg030A */
286 #define LN_ANA_TX_JEQ_EN BIT(4)
287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0)
288
289 /* lane_reg030B */
290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4)
291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0)
292
293 /* lane_reg030C */
294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4)
295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0)
296
297 /* lane_reg030D */
298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4)
299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0)
300
301 /* lane_reg030E */
302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4)
303
304 /* lane_reg0310 */
305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0)
306
307 /* lane_reg0311 */
308 #define LN_TX_SER_40BIT_EN_RBR BIT(3)
309 #define LN_TX_SER_40BIT_EN_HBR BIT(2)
310 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1)
311 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0)
312
313 /* lane_reg0316 */
314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0)
315
316 /* lane_reg031B */
317 #define LN_ANA_TX_RESERVED GENMASK(7, 0)
318
319 /* lane_reg031E */
320 #define LN_POLARITY_INV BIT(2)
321 #define LN_LANE_MODE BIT(1)
322
323 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset))
324
325 struct rockchip_hdptx_phy {
326 struct udevice *dev;
327 struct regmap *regmap;
328 struct regmap *grf;
329
330 struct reset_ctl apb_reset;
331 struct reset_ctl cmn_reset;
332 struct reset_ctl init_reset;
333 struct reset_ctl lane_reset;
334 u32 lane_polarity_invert[4];
335 bool dp_mode;
336 };
337
338 enum {
339 DP_BW_RBR,
340 DP_BW_HBR,
341 DP_BW_HBR2,
342 DP_BW_HBR3,
343 };
344
345 enum {
346 EDP_BW_2_16,
347 EDP_BW_2_43,
348 EDP_BW_3_24,
349 EDP_BW_4_32,
350 };
351
352 struct tx_drv_ctrl {
353 u8 tx_drv_lvl_ctrl;
354 u8 tx_drv_post_lvl_ctrl;
355 u8 ana_tx_drv_idrv_idn_ctrl;
356 u8 ana_tx_drv_idrv_iup_ctrl;
357 u8 ana_tx_drv_accdrv_en;
358 u8 ana_tx_drv_accdrv_ctrl;
359 u8 tx_drv_pre_lvl_ctrl;
360 u8 ana_tx_jeq_en;
361 u8 tx_jeq_even_ctrl;
362 u8 tx_jeq_odd_ctrl;
363 } __packed;
364
365 struct tx_pll_ctrl {
366 u8 mdiv;
367 u8 sdiv;
368 u8 sdm_denominator;
369 u8 sdm_numerator_sign;
370 u8 sdm_numerator;
371 u8 sdc_clock_div;
372 u8 sdc_numerator;
373 u8 sdc_denominator;
374 u8 ssc_deviation;
375 u8 ssc_freq;
376 } __packed;
377
378 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
379 /* voltage swing 0, pre-emphasis 0->3 */
380 {
381 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
382 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
383 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
384 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
385 },
386
387 /* voltage swing 1, pre-emphasis 0->2 */
388 {
389 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
390 { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
391 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
392 },
393
394 /* voltage swing 2, pre-emphasis 0->1 */
395 {
396 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
397 { 0xc, 0x5, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
398 },
399
400 /* voltage swing 3, pre-emphasis 0 */
401 {
402 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
403 }
404 };
405
406 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
407 /* voltage swing 0, pre-emphasis 0->3 */
408 {
409 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
410 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
411 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
412 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
413 },
414
415 /* voltage swing 1, pre-emphasis 0->2 */
416 {
417 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
418 { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
419 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
420 },
421
422 /* voltage swing 2, pre-emphasis 0->1 */
423 {
424 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
425 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
426 },
427
428 /* voltage swing 3, pre-emphasis 0 */
429 {
430 { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
431 }
432 };
433
434 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
435 /* voltage swing 0, pre-emphasis 0->3 */
436 {
437 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
438 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
439 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4, 0x0, 0x1, 0x7, 0x7 },
440 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
441 },
442
443 /* voltage swing 1, pre-emphasis 0->2 */
444 {
445 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
446 { 0xb, 0x7, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
447 { 0xd, 0x9, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
448 },
449
450 /* voltage swing 2, pre-emphasis 0->1 */
451 {
452 { 0x8, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
453 { 0xc, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
454 },
455
456 /* voltage swing 3, pre-emphasis 0 */
457 {
458 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
459 }
460 };
461
462 static struct tx_drv_ctrl tx_drv_ctrl_r216_r243[4][4] = {
463 /* voltage swing 0, pre-emphasis 0->3 */
464 {
465 { 0x0, 0x1, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
466 { 0x1, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
467 { 0x1, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
468 { 0x3, 0x5, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
469 },
470
471 /* voltage swing 1, pre-emphasis 0->2 */
472 {
473 { 0x1, 0x1, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
474 { 0x2, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
475 { 0x3, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
476 },
477
478 /* voltage swing 2, pre-emphasis 0->1 */
479 {
480 { 0x1, 0x1, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
481 { 0x1, 0x2, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
482 },
483
484 /* voltage swing 3, pre-emphasis 0 */
485 {
486 { 0x3, 0x2, 0x2, 0x2, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
487 }
488 };
489
490 static struct tx_drv_ctrl tx_drv_ctrl_r324[4][4] = {
491 /* voltage swing 0, pre-emphasis 0->3 */
492 {
493 { 0x1, 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
494 { 0x2, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
495 { 0x2, 0x4, 0x5, 0x5, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
496 { 0x4, 0x6, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
497 },
498
499 /* voltage swing 1, pre-emphasis 0->2 */
500 {
501 { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
502 { 0x2, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
503 { 0x4, 0x5, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
504 },
505
506 /* voltage swing 2, pre-emphasis 0->1 */
507 {
508 { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
509 { 0x4, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
510 },
511
512 /* voltage swing 3, pre-emphasis 0 */
513 {
514 { 0x3, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
515 }
516 };
517
518 static struct tx_drv_ctrl tx_drv_ctrl_r432[4][4] = {
519 /* voltage swing 0, pre-emphasis 0->3 */
520 {
521 { 0x1, 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
522 { 0x2, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
523 { 0x2, 0x4, 0x6, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
524 { 0x4, 0x6, 0x6, 0x6, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
525 },
526
527 /* voltage swing 1, pre-emphasis 0->2 */
528 {
529 { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
530 { 0x3, 0x4, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
531 { 0x5, 0x6, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
532 },
533
534 /* voltage swing 2, pre-emphasis 0->1 */
535 {
536 { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
537 { 0x4, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 },
538 },
539
540 /* voltage swing 3, pre-emphasis 0 */
541 {
542 { 0x5, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
543 }
544 };
545
546 static struct tx_drv_ctrl tx_drv_ctrl_rbr_dp_mode[4][4] = {
547 /* voltage swing 0, pre-emphasis 0->3 */
548 {
549 { 0x2, 0x0, 0x2, 0x2, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
550 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
551 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
552 { 0xd, 0xb, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
553 },
554
555 /* voltage swing 1, pre-emphasis 0->2 */
556 {
557 { 0x4, 0x0, 0x4, 0x4, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
558 { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
559 { 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
560 },
561
562 /* voltage swing 2, pre-emphasis 0->1 */
563 {
564 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
565 { 0xc, 0x5, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
566 },
567
568 /* voltage swing 3, pre-emphasis 0 */
569 {
570 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
571 }
572 };
573
574 static struct tx_drv_ctrl tx_drv_ctrl_hbr_dp_mode[4][4] = {
575 /* voltage swing 0, pre-emphasis 0->3 */
576 {
577 { 0x2, 0x0, 0x1, 0x1, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
578 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
579 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
580 { 0xd, 0xc, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
581 },
582
583 /* voltage swing 1, pre-emphasis 0->2 */
584 {
585 { 0x6, 0x1, 0x2, 0x2, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
586 { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
587 { 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
588 },
589
590 /* voltage swing 2, pre-emphasis 0->1 */
591 {
592 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
593 { 0xd, 0x6, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
594 },
595
596 /* voltage swing 3, pre-emphasis 0 */
597 {
598 { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
599 }
600 };
601
602 /* pll configurations for link rate R216/R243/R324/R432 */
603 static const struct tx_pll_ctrl tx_pll_ctrl_extra[4] = {
604 { 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0d, 0x1d }, /* R216 */
605 { 0x65, 0x01, 0x60, 0x00, 0x10, 0x01, 0x13, 0x18, 0x1c, 0x0d }, /* R243 */
606 { 0x87, 0x01, 0x21, 0x00, 0x00, 0x02, 0x03, 0x08, 0x0d, 0x1c }, /* R324 */
607 { 0x5a, 0x00, 0x32, 0x00, 0x00, 0x01, 0x01, 0x01, 0x0e, 0x1a }, /* R432 */
608 };
609
rockchip_hdptx_phy_parse_training_table(struct udevice * dev)610 static int rockchip_hdptx_phy_parse_training_table(struct udevice *dev)
611 {
612 int size = sizeof(struct tx_drv_ctrl) * 10;
613 const uint8_t *prop;
614 u8 *buf, *training_table;
615 int i, j;
616
617 prop = dev_read_u8_array_ptr(dev, "training-table", size);
618 if (!prop)
619 return 0;
620
621 buf = kzalloc(size, GFP_KERNEL);
622 if (!buf)
623 return -ENOMEM;
624
625 memcpy(buf, prop, size);
626
627 training_table = buf;
628
629 for (i = 0; i < 4; i++) {
630 for (j = 0; j < 4; j++) {
631 struct tx_drv_ctrl *ctrl;
632
633 if (i + j > 3)
634 continue;
635
636 ctrl = (struct tx_drv_ctrl *)training_table;
637 tx_drv_ctrl_rbr[i][j] = *ctrl;
638 tx_drv_ctrl_hbr[i][j] = *ctrl;
639 tx_drv_ctrl_hbr2[i][j] = *ctrl;
640 training_table += sizeof(*ctrl);
641 }
642 }
643
644 kfree(buf);
645
646 return 0;
647 }
648
rockchip_grf_write(struct regmap * grf,uint reg,uint mask,uint val)649 static inline void rockchip_grf_write(struct regmap *grf, uint reg, uint mask,
650 uint val)
651 {
652 regmap_write(grf, reg, (mask << 16) | (val & mask));
653 }
654
rockchip_hdptx_phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)655 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode,
656 int submode)
657 {
658 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev);
659
660 hdptx->dp_mode = (submode == PHY_SUBMODE_DP);
661
662 return 0;
663 }
664
rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)665 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx,
666 struct phy_configure_opts_dp *dp)
667 {
668 int i;
669
670 if (dp->set_rate) {
671 switch (dp->link_rate) {
672 case 1620:
673 case 2160:
674 case 2430:
675 case 2700:
676 case 3240:
677 case 4320:
678 case 5400:
679 break;
680 default:
681 return -EINVAL;
682 }
683 }
684
685 switch (dp->lanes) {
686 case 1:
687 case 2:
688 case 4:
689 break;
690 default:
691 return -EINVAL;
692 }
693
694 if (dp->set_voltages) {
695 for (i = 0; i < dp->lanes; i++) {
696 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
697 return -EINVAL;
698
699 if (dp->voltage[i] + dp->pre[i] > 3)
700 return -EINVAL;
701 }
702 }
703
704 return 0;
705 }
706
rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp,u8 lane)707 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
708 struct phy_configure_opts_dp *dp,
709 u8 lane)
710 {
711 const struct tx_drv_ctrl *ctrl;
712
713 switch (dp->link_rate) {
714 case 1620:
715 if (hdptx->dp_mode)
716 ctrl = &tx_drv_ctrl_rbr_dp_mode[dp->voltage[lane]][dp->pre[lane]];
717 else
718 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
719 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
720 LN_TX_SER_40BIT_EN_RBR,
721 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1));
722 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),
723 LN_TX_JEQ_EVEN_CTRL_RBR,
724 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR, ctrl->tx_jeq_even_ctrl));
725 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30),
726 LN_TX_JEQ_ODD_CTRL_RBR,
727 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR, ctrl->tx_jeq_odd_ctrl));
728 break;
729 case 2160:
730 case 2430:
731 ctrl = &tx_drv_ctrl_r216_r243[dp->voltage[lane]][dp->pre[lane]];
732 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
733 LN_TX_SER_40BIT_EN_HBR,
734 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));
735 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
736 LN_TX_JEQ_EVEN_CTRL_HBR,
737 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, ctrl->tx_jeq_even_ctrl));
738 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
739 LN_TX_JEQ_ODD_CTRL_HBR,
740 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl));
741 break;
742 case 2700:
743 if (hdptx->dp_mode)
744 ctrl = &tx_drv_ctrl_hbr_dp_mode[dp->voltage[lane]][dp->pre[lane]];
745 else
746 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
747 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
748 LN_TX_SER_40BIT_EN_HBR,
749 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));
750 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
751 LN_TX_JEQ_EVEN_CTRL_HBR,
752 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, ctrl->tx_jeq_even_ctrl));
753 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
754 LN_TX_JEQ_ODD_CTRL_HBR,
755 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl));
756 break;
757 case 3240:
758 ctrl = &tx_drv_ctrl_r324[dp->voltage[lane]][dp->pre[lane]];
759 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
760 LN_TX_SER_40BIT_EN_HBR2,
761 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
762 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
763 LN_TX_JEQ_EVEN_CTRL_HBR2,
764 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, ctrl->tx_jeq_even_ctrl));
765 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
766 LN_TX_JEQ_ODD_CTRL_HBR2,
767 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, ctrl->tx_jeq_odd_ctrl));
768 break;
769 case 4320:
770 ctrl = &tx_drv_ctrl_r432[dp->voltage[lane]][dp->pre[lane]];
771 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
772 LN_TX_SER_40BIT_EN_HBR2,
773 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
774 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
775 LN_TX_JEQ_EVEN_CTRL_HBR2,
776 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, ctrl->tx_jeq_even_ctrl));
777 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
778 LN_TX_JEQ_ODD_CTRL_HBR2,
779 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, ctrl->tx_jeq_odd_ctrl));
780 break;
781 case 5400:
782 default:
783 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
784 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
785 LN_TX_SER_40BIT_EN_HBR2,
786 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
787 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
788 LN_TX_JEQ_EVEN_CTRL_HBR2,
789 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, ctrl->tx_jeq_even_ctrl));
790 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
791 LN_TX_JEQ_ODD_CTRL_HBR2,
792 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, ctrl->tx_jeq_odd_ctrl));
793 break;
794 }
795
796 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c),
797 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL,
798 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) |
799 FIELD_PREP(LN_TX_DRV_LVL_CTRL,
800 ctrl->tx_drv_lvl_ctrl));
801 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10),
802 OVRD_LN_TX_DRV_POST_LVL_CTRL |
803 LN_TX_DRV_POST_LVL_CTRL,
804 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) |
805 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL,
806 ctrl->tx_drv_post_lvl_ctrl));
807 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c14),
808 OVRD_LN_TX_DRV_PRE_LVL_CTRL |
809 LN_TX_DRV_PRE_LVL_CTRL,
810 FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL, 0x1) |
811 FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL,
812 ctrl->tx_drv_pre_lvl_ctrl));
813 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18),
814 LN_ANA_TX_DRV_IDRV_IDN_CTRL |
815 LN_ANA_TX_DRV_IDRV_IUP_CTRL |
816 LN_ANA_TX_DRV_ACCDRV_EN,
817 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL,
818 ctrl->ana_tx_drv_idrv_idn_ctrl) |
819 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL,
820 ctrl->ana_tx_drv_idrv_iup_ctrl) |
821 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN,
822 ctrl->ana_tx_drv_accdrv_en));
823 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c),
824 LN_ANA_TX_DRV_ACCDRV_POL_SEL |
825 LN_ANA_TX_DRV_ACCDRV_CTRL,
826 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) |
827 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL,
828 ctrl->ana_tx_drv_accdrv_ctrl));
829 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),
830 LN_ANA_TX_JEQ_EN,
831 FIELD_PREP(LN_ANA_TX_JEQ_EN, ctrl->ana_tx_jeq_en));
832 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c),
833 LN_ANA_TX_RESERVED,
834 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1));
835 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58),
836 LN_ANA_TX_SER_VREG_GAIN_CTRL,
837 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2));
838 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40),
839 LN_ANA_TX_SYNC_LOSS_DET_MODE,
840 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3));
841 }
842
rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)843 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx,
844 struct phy_configure_opts_dp *dp)
845 {
846 u8 lane;
847 u32 status;
848 int ret;
849
850 for (lane = 0; lane < dp->lanes; lane++)
851 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);
852
853 reset_deassert(&hdptx->lane_reset);
854
855 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
856 status, FIELD_GET(PHY_RDY, status),
857 50, 5000);
858 if (ret) {
859 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
860 return ret;
861 }
862
863 return 0;
864 }
865
is_extra_recommended_link_rate(u32 link_rate)866 static bool is_extra_recommended_link_rate(u32 link_rate)
867 {
868 switch (link_rate) {
869 case 2160:
870 case 2430:
871 case 3240:
872 case 4320:
873 return true;
874 }
875
876 return false;
877 }
878
rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)879 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx,
880 struct phy_configure_opts_dp *dp)
881 {
882 u32 bw, status;
883 u32 bw_extra = 0;
884 int ret;
885
886 reset_assert(&hdptx->lane_reset);
887 udelay(10);
888 reset_assert(&hdptx->cmn_reset);
889 udelay(10);
890 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
891 FIELD_PREP(PLL_EN, 0x0));
892 udelay(10);
893 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
894 FIELD_PREP(LANE_EN, 0x0));
895
896 switch (dp->link_rate) {
897 case 1620:
898 bw = DP_BW_RBR;
899 break;
900 case 2160:
901 bw_extra = EDP_BW_2_16;
902 bw = DP_BW_HBR;
903 break;
904 case 2430:
905 bw_extra = EDP_BW_2_43;
906 bw = DP_BW_HBR;
907 break;
908 case 2700:
909 bw = DP_BW_HBR;
910 break;
911 case 3240:
912 bw_extra = EDP_BW_3_24;
913 bw = DP_BW_HBR2;
914 break;
915 case 4320:
916 bw_extra = EDP_BW_4_32;
917 bw = DP_BW_HBR2;
918 break;
919 case 5400:
920 bw = DP_BW_HBR2;
921 break;
922 default:
923 return -EINVAL;
924 }
925
926 if (is_extra_recommended_link_rate(dp->link_rate)) {
927 const struct tx_pll_ctrl *pll_ctrl = &tx_pll_ctrl_extra[bw_extra];
928
929 regmap_write(hdptx->regmap, 0x0144 + bw * 0x4,
930 FIELD_PREP(ROPLL_PMS_MDIV, pll_ctrl->mdiv));
931 regmap_write(hdptx->regmap, 0x0180 + bw * 0x4,
932 FIELD_PREP(ROPLL_SDM_DENOMINATOR, pll_ctrl->sdm_denominator));
933 regmap_write(hdptx->regmap, 0x0194 + bw * 0x4,
934 FIELD_PREP(ROPLL_SDM_NUMERATOR, pll_ctrl->sdm_numerator));
935 regmap_write(hdptx->regmap, 0x01b0 + bw * 0x4,
936 FIELD_PREP(ROPLL_SDC_NUMERATOR, pll_ctrl->sdc_numerator));
937 regmap_write(hdptx->regmap, 0x01c0 + bw * 0x4,
938 FIELD_PREP(ROPLL_SDC_DENOMINATOR, pll_ctrl->sdc_denominator));
939
940 if (bw == DP_BW_RBR) {
941 regmap_update_bits(hdptx->regmap, 0x0168, ROPLL_PMS_SDIV_RBR,
942 FIELD_PREP(ROPLL_PMS_SDIV_RBR, pll_ctrl->sdiv));
943 regmap_update_bits(hdptx->regmap, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_RBR,
944 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR,
945 pll_ctrl->sdm_numerator_sign));
946 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR,
947 FIELD_PREP(ROPLL_SDC_N_RBR, pll_ctrl->sdc_clock_div));
948 } else if (bw == DP_BW_HBR) {
949 regmap_update_bits(hdptx->regmap, 0x0168, ROPLL_PMS_SDIV_HBR,
950 FIELD_PREP(ROPLL_PMS_SDIV_HBR, pll_ctrl->sdiv));
951 regmap_update_bits(hdptx->regmap, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_HBR,
952 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR,
953 pll_ctrl->sdm_numerator_sign));
954 regmap_update_bits(hdptx->regmap, 0x01a8, ROPLL_SDC_N_HBR,
955 FIELD_PREP(ROPLL_SDC_N_HBR, pll_ctrl->sdc_clock_div));
956 } else {
957 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2,
958 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, pll_ctrl->sdiv));
959 regmap_update_bits(hdptx->regmap, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_HBR2,
960 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2,
961 pll_ctrl->sdm_numerator_sign));
962 regmap_update_bits(hdptx->regmap, 0x01a8, ROPLL_SDC_N_HBR2,
963 FIELD_PREP(ROPLL_SDC_N_HBR2, pll_ctrl->sdc_clock_div));
964 }
965 }
966
967 regmap_update_bits(hdptx->regmap, 0x0254, DP_TX_LINK_BW,
968 FIELD_PREP(DP_TX_LINK_BW, bw));
969
970 if (dp->ssc) {
971 regmap_update_bits(hdptx->regmap, 0x01d0,
972 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
973 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
974 FIELD_PREP(ROPLL_SSC_EN, 0x1));
975 if (is_extra_recommended_link_rate(dp->link_rate)) {
976 const struct tx_pll_ctrl *pll_ctrl = &tx_pll_ctrl_extra[bw_extra];
977
978 regmap_write(hdptx->regmap, 0x01d4,
979 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION,
980 pll_ctrl->ssc_deviation));
981 regmap_update_bits(hdptx->regmap, 0x01d8,
982 ANA_ROPLL_SSC_FM_FREQ,
983 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ,
984 pll_ctrl->ssc_freq));
985 } else {
986 regmap_write(hdptx->regmap, 0x01d4,
987 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc));
988 regmap_update_bits(hdptx->regmap, 0x01d8,
989 ANA_ROPLL_SSC_FM_FREQ,
990 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f));
991 }
992 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
993 FIELD_PREP(SSC_EN, 0x2));
994 } else {
995 regmap_update_bits(hdptx->regmap, 0x01d0,
996 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
997 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
998 FIELD_PREP(ROPLL_SSC_EN, 0x0));
999 regmap_update_bits(hdptx->regmap, 0x01d4,
1000 ANA_ROPLL_SSC_FM_DEVIATION,
1001 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20));
1002 regmap_update_bits(hdptx->regmap, 0x01d8,
1003 ANA_ROPLL_SSC_FM_FREQ,
1004 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc));
1005 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
1006 FIELD_PREP(SSC_EN, 0x0));
1007 }
1008
1009 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
1010 FIELD_PREP(PLL_EN, 0x1));
1011 udelay(10);
1012 reset_deassert(&hdptx->cmn_reset);
1013 udelay(10);
1014
1015 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
1016 status, FIELD_GET(PLL_LOCK_DONE, status),
1017 50, 1000);
1018 if (ret) {
1019 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n");
1020 return ret;
1021 }
1022
1023 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
1024 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0)));
1025
1026 return 0;
1027 }
1028
rockchip_hdptx_phy_configure(struct phy * phy,union phy_configure_opts * opts)1029 static int rockchip_hdptx_phy_configure(struct phy *phy,
1030 union phy_configure_opts *opts)
1031 {
1032 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev);
1033 enum phy_mode mode = generic_phy_get_mode(phy);
1034 int ret;
1035
1036 if (mode != PHY_MODE_DP)
1037 return -EINVAL;
1038
1039 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp);
1040 if (ret) {
1041 dev_err(hdptx->dev, "invalid params for phy configure\n");
1042 return ret;
1043 }
1044
1045 if (opts->dp.set_rate) {
1046 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp);
1047 if (ret) {
1048 dev_err(hdptx->dev, "failed to set rate: %d\n", ret);
1049 return ret;
1050 }
1051 }
1052
1053 if (opts->dp.set_voltages) {
1054 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp);
1055 if (ret) {
1056 dev_err(hdptx->dev, "failed to set voltages: %d\n",
1057 ret);
1058 return ret;
1059 }
1060 }
1061
1062 return 0;
1063 }
1064
rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy * hdptx)1065 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx)
1066 {
1067 regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN,
1068 FIELD_PREP(OVRD_LCPLL_EN, 0x1) |
1069 FIELD_PREP(LCPLL_EN, 0x0));
1070 regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN,
1071 FIELD_PREP(OVRD_ROPLL_EN, 0x1) |
1072 FIELD_PREP(ROPLL_EN, 0x1));
1073 regmap_update_bits(hdptx->regmap, 0x0138, ANA_ROPLL_PI_EN,
1074 FIELD_PREP(ANA_ROPLL_PI_EN, 0x1));
1075 regmap_write(hdptx->regmap, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87));
1076 regmap_write(hdptx->regmap, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
1077 regmap_write(hdptx->regmap, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
1078 regmap_write(hdptx->regmap, 0x0154,
1079 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87));
1080 regmap_write(hdptx->regmap, 0x0158,
1081 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
1082 regmap_write(hdptx->regmap, 0x015c,
1083 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
1084 regmap_write(hdptx->regmap, 0x0164,
1085 FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) |
1086 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1));
1087 regmap_write(hdptx->regmap, 0x0168,
1088 FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) |
1089 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1));
1090 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2,
1091 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0));
1092 regmap_update_bits(hdptx->regmap, 0x0178, ANA_ROPLL_SDM_EN,
1093 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1));
1094 regmap_update_bits(hdptx->regmap, 0x0178,
1095 OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN,
1096 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) |
1097 FIELD_PREP(ROPLL_SDM_RSTN, 0x1));
1098 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR,
1099 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1));
1100 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR,
1101 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1));
1102 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2,
1103 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1));
1104 regmap_update_bits(hdptx->regmap, 0x017c,
1105 OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN,
1106 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) |
1107 FIELD_PREP(ROPLL_SDC_RSTN, 0x1));
1108 regmap_write(hdptx->regmap, 0x0180,
1109 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21));
1110 regmap_write(hdptx->regmap, 0x0184,
1111 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
1112 regmap_write(hdptx->regmap, 0x0188,
1113 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
1114 regmap_update_bits(hdptx->regmap, 0x0190,
1115 ROPLL_SDM_NUMERATOR_SIGN_RBR |
1116 ROPLL_SDM_NUMERATOR_SIGN_HBR |
1117 ROPLL_SDM_NUMERATOR_SIGN_HBR2,
1118 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) |
1119 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) |
1120 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1));
1121 regmap_write(hdptx->regmap, 0x0194,
1122 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0));
1123 regmap_write(hdptx->regmap, 0x0198,
1124 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
1125 regmap_write(hdptx->regmap, 0x019c,
1126 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
1127 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR,
1128 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2));
1129 regmap_update_bits(hdptx->regmap, 0x01a8,
1130 ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2,
1131 FIELD_PREP(ROPLL_SDC_N_HBR, 0x2) |
1132 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x2));
1133 regmap_write(hdptx->regmap, 0x01b0,
1134 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3));
1135 regmap_write(hdptx->regmap, 0x01b4,
1136 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
1137 regmap_write(hdptx->regmap, 0x01b8,
1138 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
1139 regmap_write(hdptx->regmap, 0x01c0,
1140 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8));
1141 regmap_write(hdptx->regmap, 0x01c4,
1142 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
1143 regmap_write(hdptx->regmap, 0x01c8,
1144 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
1145 regmap_update_bits(hdptx->regmap, 0x01d0,
1146 OVRD_ROPLL_SDC_NDIV_RSTN | ROPLL_SDC_NDIV_RSTN,
1147 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) |
1148 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1));
1149 regmap_update_bits(hdptx->regmap, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL,
1150 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1));
1151 regmap_update_bits(hdptx->regmap, 0x0118,
1152 ROPLL_ANA_CPP_CTRL_COARSE | ROPLL_ANA_CPP_CTRL_FINE,
1153 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) |
1154 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe));
1155 regmap_update_bits(hdptx->regmap, 0x011c,
1156 ROPLL_ANA_LPF_C_SEL_COARSE |
1157 ROPLL_ANA_LPF_C_SEL_FINE,
1158 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) |
1159 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4));
1160 regmap_update_bits(hdptx->regmap, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL,
1161 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0));
1162 regmap_update_bits(hdptx->regmap, 0x025c, DIG_CLK_SEL,
1163 FIELD_PREP(DIG_CLK_SEL, 0x1));
1164 regmap_update_bits(hdptx->regmap, 0x021c, ANA_PLL_TX_HS_CLK_EN,
1165 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1));
1166 regmap_update_bits(hdptx->regmap, 0x0204,
1167 ANA_PLL_CD_HSCLK_EAST_EN | ANA_PLL_CD_HSCLK_WEST_EN,
1168 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) |
1169 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0));
1170 regmap_update_bits(hdptx->regmap, 0x0264, CMN_ROPLL_ALONE_MODE,
1171 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1));
1172 regmap_update_bits(hdptx->regmap, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL,
1173 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4));
1174 regmap_update_bits(hdptx->regmap, 0x00f0, ANA_LCPLL_RESERVED7,
1175 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1));
1176 regmap_update_bits(hdptx->regmap, 0x020c, ANA_PLL_CD_VREG_ICTRL,
1177 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1));
1178 regmap_update_bits(hdptx->regmap, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE,
1179 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3));
1180 regmap_update_bits(hdptx->regmap, 0x0210, PLL_LCRO_CLK_SEL,
1181 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1));
1182 regmap_update_bits(hdptx->regmap, 0x0268, HS_SPEED_SEL,
1183 FIELD_PREP(HS_SPEED_SEL, 0x1));
1184 regmap_update_bits(hdptx->regmap, 0x026c, LS_SPEED_SEL,
1185 FIELD_PREP(LS_SPEED_SEL, 0x1));
1186 }
1187
rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy * hdptx)1188 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx)
1189 {
1190 u32 status;
1191 int ret;
1192
1193 regmap_update_bits(hdptx->regmap, 0x0414, ANA_SB_TX_HLVL_PROG,
1194 FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7));
1195 regmap_update_bits(hdptx->regmap, 0x0418, ANA_SB_TX_LLVL_PROG,
1196 FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7));
1197 regmap_update_bits(hdptx->regmap, 0x044c,
1198 SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL,
1199 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) |
1200 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3));
1201 regmap_update_bits(hdptx->regmap, 0x0450,
1202 SB_TG_SB_EN_DELAY_TIME | SB_TG_RXTERN_EN_DELAY_TIME,
1203 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) |
1204 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2));
1205 regmap_update_bits(hdptx->regmap, 0x0454,
1206 SB_READY_DELAY_TIME | SB_TG_OSC_EN_DELAY_TIME,
1207 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) |
1208 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2));
1209 regmap_update_bits(hdptx->regmap, 0x0458,
1210 SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME,
1211 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2));
1212 regmap_update_bits(hdptx->regmap, 0x045c,
1213 SB_TG_PLL_CD_VREG_FAST_PULSE_TIME,
1214 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4));
1215 regmap_update_bits(hdptx->regmap, 0x0460,
1216 SB_TG_EARC_DMRX_RECVRD_CLK_CNT,
1217 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa));
1218 regmap_update_bits(hdptx->regmap, 0x0468, SB_TG_CNT_RUN_NO_7_0,
1219 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3));
1220 regmap_update_bits(hdptx->regmap, 0x046c,
1221 SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL,
1222 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) |
1223 FIELD_PREP(SB_AFC_TOL, 0x3));
1224 regmap_update_bits(hdptx->regmap, 0x0470, SB_AFC_STB_NUM,
1225 FIELD_PREP(SB_AFC_STB_NUM, 0x4));
1226 regmap_update_bits(hdptx->regmap, 0x0474, SB_TG_OSC_CNT_MIN,
1227 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67));
1228 regmap_update_bits(hdptx->regmap, 0x0478, SB_TG_OSC_CNT_MAX,
1229 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a));
1230 regmap_update_bits(hdptx->regmap, 0x047c, SB_PWM_AFC_CTRL,
1231 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5));
1232 regmap_update_bits(hdptx->regmap, 0x0434, ANA_SB_DMRX_LPBK_DATA,
1233 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1));
1234 regmap_update_bits(hdptx->regmap, 0x0440,
1235 ANA_SB_VREG_OUT_SEL | ANA_SB_VREG_REF_SEL,
1236 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) |
1237 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1));
1238 regmap_update_bits(hdptx->regmap, 0x043c, ANA_SB_VREG_GAIN_CTRL,
1239 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0));
1240 regmap_update_bits(hdptx->regmap, 0x0408, ANA_SB_RXTERM_OFFSP,
1241 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3));
1242 regmap_update_bits(hdptx->regmap, 0x040c, ANA_SB_RXTERM_OFFSN,
1243 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3));
1244 regmap_update_bits(hdptx->regmap, 0x047c, SB_RCAL_RSTN,
1245 FIELD_PREP(SB_RCAL_RSTN, 0x1));
1246 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
1247 FIELD_PREP(SB_AUX_EN, 0x1));
1248 regmap_update_bits(hdptx->regmap, 0x0480, SB_AUX_EN_IN,
1249 FIELD_PREP(SB_AUX_EN_IN, 0x1));
1250 regmap_update_bits(hdptx->regmap, 0x040c, OVRD_SB_RX_RESCAL_DONE,
1251 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1));
1252 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_EN,
1253 FIELD_PREP(OVRD_SB_EN, 0x1));
1254 regmap_update_bits(hdptx->regmap, 0x0408, OVRD_SB_RXTERM_EN,
1255 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1));
1256 regmap_update_bits(hdptx->regmap, 0x043c, OVRD_SB_VREG_EN,
1257 FIELD_PREP(OVRD_SB_VREG_EN, 0x1));
1258 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_AUX_EN,
1259 FIELD_PREP(OVRD_SB_AUX_EN, 0x1));
1260
1261 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
1262 FIELD_PREP(BGR_EN, 0x1));
1263 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
1264 FIELD_PREP(BIAS_EN, 0x1));
1265 udelay(10);
1266 reset_deassert(&hdptx->init_reset);
1267 udelay(1000);
1268 reset_deassert(&hdptx->cmn_reset);
1269 udelay(20);
1270
1271 regmap_update_bits(hdptx->regmap, 0x040c, SB_RX_RESCAL_DONE,
1272 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1));
1273 udelay(100);
1274 regmap_update_bits(hdptx->regmap, 0x0410, SB_EN,
1275 FIELD_PREP(SB_EN, 0x1));
1276 udelay(100);
1277 regmap_update_bits(hdptx->regmap, 0x0408, SB_RXRERM_EN,
1278 FIELD_PREP(SB_RXRERM_EN, 0x1));
1279 udelay(10);
1280 regmap_update_bits(hdptx->regmap, 0x043c, SB_VREG_EN,
1281 FIELD_PREP(SB_VREG_EN, 0x1));
1282 udelay(10);
1283 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
1284 FIELD_PREP(SB_AUX_EN, 0x1));
1285 udelay(100);
1286
1287 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
1288 status, FIELD_GET(SB_RDY, status),
1289 50, 1000);
1290 if (ret) {
1291 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n");
1292 return ret;
1293 }
1294
1295 return 0;
1296 }
1297
rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy * hdptx)1298 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx)
1299 {
1300 u32 lane;
1301
1302 reset_assert(&hdptx->lane_reset);
1303 reset_assert(&hdptx->cmn_reset);
1304 reset_assert(&hdptx->init_reset);
1305
1306 reset_assert(&hdptx->apb_reset);
1307 udelay(10);
1308 reset_deassert(&hdptx->apb_reset);
1309
1310 for (lane = 0; lane < 4; lane++)
1311 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04),
1312 OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN,
1313 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) |
1314 FIELD_PREP(LN_TX_DRV_EI_EN, 0));
1315
1316 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
1317 FIELD_PREP(PLL_EN, 0));
1318 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
1319 FIELD_PREP(BIAS_EN, 0));
1320 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
1321 FIELD_PREP(BGR_EN, 0));
1322 }
1323
rockchip_hdptx_phy_power_on(struct phy * phy)1324 static int rockchip_hdptx_phy_power_on(struct phy *phy)
1325 {
1326 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev);
1327 enum phy_mode mode = generic_phy_get_mode(phy);
1328 u32 lane;
1329
1330 rockchip_hdptx_phy_reset(hdptx);
1331
1332 for (lane = 0; lane < 4; lane++) {
1333 u32 invert = hdptx->lane_polarity_invert[lane];
1334
1335 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78),
1336 LN_POLARITY_INV | LN_LANE_MODE,
1337 FIELD_PREP(LN_POLARITY_INV, invert) |
1338 FIELD_PREP(LN_LANE_MODE, 1));
1339 }
1340
1341 if (mode == PHY_MODE_DP) {
1342 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
1343 HDPTX_MODE_SEL,
1344 FIELD_PREP(HDPTX_MODE_SEL, 0x1));
1345
1346 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
1347 FIELD_PREP(PROTOCOL_SEL, 0x0));
1348 regmap_update_bits(hdptx->regmap, 0x0818, DATA_BUS_WIDTH,
1349 FIELD_PREP(DATA_BUS_WIDTH, 0x1));
1350 regmap_update_bits(hdptx->regmap, 0x0818, BUS_WIDTH_SEL,
1351 FIELD_PREP(BUS_WIDTH_SEL, 0x0));
1352
1353 rockchip_hdptx_phy_dp_pll_init(hdptx);
1354 rockchip_hdptx_phy_dp_aux_init(hdptx);
1355 } else {
1356 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
1357 HDPTX_MODE_SEL,
1358 FIELD_PREP(HDPTX_MODE_SEL, 0x0));
1359
1360 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
1361 FIELD_PREP(PROTOCOL_SEL, 0x1));
1362 }
1363
1364 return 0;
1365 }
1366
rockchip_hdptx_phy_power_off(struct phy * phy)1367 static int rockchip_hdptx_phy_power_off(struct phy *phy)
1368 {
1369 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev);
1370
1371 rockchip_hdptx_phy_reset(hdptx);
1372
1373 return 0;
1374 }
1375
1376 static const struct phy_ops rockchip_hdptx_phy_ops = {
1377 .set_mode = rockchip_hdptx_phy_set_mode,
1378 .configure = rockchip_hdptx_phy_configure,
1379 .power_on = rockchip_hdptx_phy_power_on,
1380 .power_off = rockchip_hdptx_phy_power_off,
1381 };
1382
rockchip_hdptx_phy_probe(struct udevice * dev)1383 static int rockchip_hdptx_phy_probe(struct udevice *dev)
1384 {
1385 struct rockchip_hdptx_phy *hdptx = dev_get_priv(dev);
1386 struct udevice *syscon;
1387 u32 prop[4];
1388 int ret;
1389
1390 ret = regmap_init_mem(dev, &hdptx->regmap);
1391 if (ret)
1392 return ret;
1393
1394 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
1395 &syscon);
1396 if (ret)
1397 return ret;
1398
1399 hdptx->grf = syscon_get_regmap(syscon);
1400 if (IS_ERR(hdptx->grf)) {
1401 ret = PTR_ERR(hdptx->grf);
1402 dev_err(dev, "unable to find regmap: %d\n", ret);
1403 return ret;
1404 }
1405
1406 hdptx->dev = dev;
1407
1408 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset);
1409 if (ret < 0) {
1410 dev_err(dev, "failed to get apb reset: %d\n", ret);
1411 return ret;
1412 }
1413
1414 ret = reset_get_by_name(dev, "init", &hdptx->init_reset);
1415 if (ret < 0) {
1416 dev_err(dev, "failed to get init reset: %d\n", ret);
1417 return ret;
1418 }
1419
1420 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset);
1421 if (ret < 0) {
1422 dev_err(dev, "failed to get cmn reset: %d\n", ret);
1423 return ret;
1424 }
1425
1426 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset);
1427 if (ret < 0) {
1428 dev_err(dev, "failed to get lane reset: %d\n", ret);
1429 return ret;
1430 }
1431
1432 ret = rockchip_hdptx_phy_parse_training_table(dev);
1433 if (ret) {
1434 dev_err(dev, "failed to parse training table: %d\n", ret);
1435 return ret;
1436 }
1437
1438 if (!dev_read_u32_array(dev, "lane-polarity-invert", prop, ARRAY_SIZE(prop))) {
1439 hdptx->lane_polarity_invert[0] = prop[0];
1440 hdptx->lane_polarity_invert[1] = prop[1];
1441 hdptx->lane_polarity_invert[2] = prop[2];
1442 hdptx->lane_polarity_invert[3] = prop[3];
1443 }
1444
1445 return 0;
1446 }
1447
1448 static const struct udevice_id rockchip_hdptx_phy_ids[] = {
1449 { .compatible = "rockchip,rk3588-hdptx-phy", },
1450 {}
1451 };
1452
1453 U_BOOT_DRIVER(rockchip_hdptx_phy) = {
1454 .name = "rockchip_hdptx_phy",
1455 .id = UCLASS_PHY,
1456 .ops = &rockchip_hdptx_phy_ops,
1457 .of_match = rockchip_hdptx_phy_ids,
1458 .probe = rockchip_hdptx_phy_probe,
1459 .priv_auto_alloc_size = sizeof(struct rockchip_hdptx_phy),
1460 };
1461