1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __DRIVERS_PINCTRL_ROCKCHIP_H 7 #define __DRIVERS_PINCTRL_ROCKCHIP_H 8 9 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <linux/types.h> 11 12 #define RK_GPIO0_A0 0 13 #define RK_GPIO0_A1 1 14 #define RK_GPIO0_A2 2 15 #define RK_GPIO0_A3 3 16 #define RK_GPIO0_A4 4 17 #define RK_GPIO0_A5 5 18 #define RK_GPIO0_A6 6 19 #define RK_GPIO0_A7 7 20 #define RK_GPIO0_B0 8 21 #define RK_GPIO0_B1 9 22 #define RK_GPIO0_B2 10 23 #define RK_GPIO0_B3 11 24 #define RK_GPIO0_B4 12 25 #define RK_GPIO0_B5 13 26 #define RK_GPIO0_B6 14 27 #define RK_GPIO0_B7 15 28 #define RK_GPIO0_C0 16 29 #define RK_GPIO0_C1 17 30 #define RK_GPIO0_C2 18 31 #define RK_GPIO0_C3 19 32 #define RK_GPIO0_C4 20 33 #define RK_GPIO0_C5 21 34 #define RK_GPIO0_C6 22 35 #define RK_GPIO0_C7 23 36 #define RK_GPIO0_D0 24 37 #define RK_GPIO0_D1 25 38 #define RK_GPIO0_D2 26 39 #define RK_GPIO0_D3 27 40 #define RK_GPIO0_D4 28 41 #define RK_GPIO0_D5 29 42 #define RK_GPIO0_D6 30 43 #define RK_GPIO0_D7 31 44 45 #define RK_GPIO1_A0 32 46 #define RK_GPIO1_A1 33 47 #define RK_GPIO1_A2 34 48 #define RK_GPIO1_A3 35 49 #define RK_GPIO1_A4 36 50 #define RK_GPIO1_A5 37 51 #define RK_GPIO1_A6 38 52 #define RK_GPIO1_A7 39 53 #define RK_GPIO1_B0 40 54 #define RK_GPIO1_B1 41 55 #define RK_GPIO1_B2 42 56 #define RK_GPIO1_B3 43 57 #define RK_GPIO1_B4 44 58 #define RK_GPIO1_B5 45 59 #define RK_GPIO1_B6 46 60 #define RK_GPIO1_B7 47 61 #define RK_GPIO1_C0 48 62 #define RK_GPIO1_C1 49 63 #define RK_GPIO1_C2 50 64 #define RK_GPIO1_C3 51 65 #define RK_GPIO1_C4 52 66 #define RK_GPIO1_C5 53 67 #define RK_GPIO1_C6 54 68 #define RK_GPIO1_C7 55 69 #define RK_GPIO1_D0 56 70 #define RK_GPIO1_D1 57 71 #define RK_GPIO1_D2 58 72 #define RK_GPIO1_D3 59 73 #define RK_GPIO1_D4 60 74 #define RK_GPIO1_D5 61 75 #define RK_GPIO1_D6 62 76 #define RK_GPIO1_D7 63 77 78 #define RK_GPIO2_A0 64 79 #define RK_GPIO2_A1 65 80 #define RK_GPIO2_A2 66 81 #define RK_GPIO2_A3 67 82 #define RK_GPIO2_A4 68 83 #define RK_GPIO2_A5 69 84 #define RK_GPIO2_A6 70 85 #define RK_GPIO2_A7 71 86 #define RK_GPIO2_B0 72 87 #define RK_GPIO2_B1 73 88 #define RK_GPIO2_B2 74 89 #define RK_GPIO2_B3 75 90 #define RK_GPIO2_B4 76 91 #define RK_GPIO2_B5 77 92 #define RK_GPIO2_B6 78 93 #define RK_GPIO2_B7 79 94 #define RK_GPIO2_C0 80 95 #define RK_GPIO2_C1 81 96 #define RK_GPIO2_C2 82 97 #define RK_GPIO2_C3 83 98 #define RK_GPIO2_C4 84 99 #define RK_GPIO2_C5 85 100 #define RK_GPIO2_C6 86 101 #define RK_GPIO2_C7 87 102 #define RK_GPIO2_D0 88 103 #define RK_GPIO2_D1 89 104 #define RK_GPIO2_D2 90 105 #define RK_GPIO2_D3 91 106 #define RK_GPIO2_D4 92 107 #define RK_GPIO2_D5 93 108 #define RK_GPIO2_D6 94 109 #define RK_GPIO2_D7 95 110 111 #define RK_GPIO3_A0 96 112 #define RK_GPIO3_A1 97 113 #define RK_GPIO3_A2 98 114 #define RK_GPIO3_A3 99 115 #define RK_GPIO3_A4 100 116 #define RK_GPIO3_A5 101 117 #define RK_GPIO3_A6 102 118 #define RK_GPIO3_A7 103 119 #define RK_GPIO3_B0 104 120 #define RK_GPIO3_B1 105 121 #define RK_GPIO3_B2 106 122 #define RK_GPIO3_B3 107 123 #define RK_GPIO3_B4 108 124 #define RK_GPIO3_B5 109 125 #define RK_GPIO3_B6 110 126 #define RK_GPIO3_B7 111 127 #define RK_GPIO3_C0 112 128 #define RK_GPIO3_C1 113 129 #define RK_GPIO3_C2 114 130 #define RK_GPIO3_C3 115 131 #define RK_GPIO3_C4 116 132 #define RK_GPIO3_C5 117 133 #define RK_GPIO3_C6 118 134 #define RK_GPIO3_C7 119 135 #define RK_GPIO3_D0 120 136 #define RK_GPIO3_D1 121 137 #define RK_GPIO3_D2 122 138 #define RK_GPIO3_D3 123 139 #define RK_GPIO3_D4 124 140 #define RK_GPIO3_D5 125 141 #define RK_GPIO3_D6 126 142 #define RK_GPIO3_D7 127 143 144 #define RK_GPIO4_A0 128 145 #define RK_GPIO4_A1 129 146 #define RK_GPIO4_A2 130 147 #define RK_GPIO4_A3 131 148 #define RK_GPIO4_A4 132 149 #define RK_GPIO4_A5 133 150 #define RK_GPIO4_A6 134 151 #define RK_GPIO4_A7 135 152 #define RK_GPIO4_B0 136 153 #define RK_GPIO4_B1 137 154 #define RK_GPIO4_B2 138 155 #define RK_GPIO4_B3 139 156 #define RK_GPIO4_B4 140 157 #define RK_GPIO4_B5 141 158 #define RK_GPIO4_B6 142 159 #define RK_GPIO4_B7 143 160 #define RK_GPIO4_C0 144 161 #define RK_GPIO4_C1 145 162 #define RK_GPIO4_C2 146 163 #define RK_GPIO4_C3 147 164 #define RK_GPIO4_C4 148 165 #define RK_GPIO4_C5 149 166 #define RK_GPIO4_C6 150 167 #define RK_GPIO4_C7 151 168 #define RK_GPIO4_D0 152 169 #define RK_GPIO4_D1 153 170 #define RK_GPIO4_D2 154 171 #define RK_GPIO4_D3 155 172 #define RK_GPIO4_D4 156 173 #define RK_GPIO4_D5 157 174 #define RK_GPIO4_D6 158 175 #define RK_GPIO4_D7 159 176 177 #define RK_GENMASK_VAL(h, l, v) \ 178 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 179 180 /** 181 * Encode variants of iomux registers into a type variable 182 */ 183 #define IOMUX_GPIO_ONLY BIT(0) 184 #define IOMUX_WIDTH_4BIT BIT(1) 185 #define IOMUX_SOURCE_PMU BIT(2) 186 #define IOMUX_UNROUTED BIT(3) 187 #define IOMUX_WIDTH_3BIT BIT(4) 188 #define IOMUX_8WIDTH_2BIT BIT(5) 189 #define IOMUX_WRITABLE_32BIT BIT(6) 190 #define IOMUX_L_SOURCE_PMU BIT(7) 191 192 /** 193 * Defined some common pins constants 194 */ 195 #define ROCKCHIP_PULL_BITS_PER_PIN 2 196 #define ROCKCHIP_PULL_PINS_PER_REG 8 197 #define ROCKCHIP_PULL_BANK_STRIDE 16 198 #define ROCKCHIP_DRV_BITS_PER_PIN 2 199 #define ROCKCHIP_DRV_PINS_PER_REG 8 200 #define ROCKCHIP_DRV_BANK_STRIDE 16 201 #define ROCKCHIP_DRV_3BITS_PER_PIN 3 202 203 /** 204 * @type: iomux variant using IOMUX_* constants 205 * @offset: if initialized to -1 it will be autocalculated, by specifying 206 * an initial offset value the relevant source offset can be reset 207 * to a new value for autocalculating the following iomux registers. 208 */ 209 struct rockchip_iomux { 210 int type; 211 int offset; 212 }; 213 214 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 215 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 216 217 /** 218 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 219 */ 220 enum rockchip_pin_drv_type { 221 DRV_TYPE_IO_DEFAULT = 0, 222 DRV_TYPE_IO_1V8_OR_3V0, 223 DRV_TYPE_IO_1V8_ONLY, 224 DRV_TYPE_IO_1V8_3V0_AUTO, 225 DRV_TYPE_IO_3V3_ONLY, 226 DRV_TYPE_MAX 227 }; 228 229 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 230 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 231 232 /** 233 * enum type index corresponding to rockchip_pull_list arrays index. 234 */ 235 enum rockchip_pin_pull_type { 236 PULL_TYPE_IO_DEFAULT = 0, 237 PULL_TYPE_IO_1V8_ONLY, 238 PULL_TYPE_IO_1 = 1, 239 PULL_TYPE_MAX 240 }; 241 242 /** 243 * enum mux route register type, should be invalid/default/topgrf/pmugrf. 244 * INVALID: means do not need to set mux route 245 * DEFAULT: means same regmap as pin iomux 246 * TOPGRF: means mux route setting in topgrf 247 * PMUGRF: means mux route setting in pmugrf 248 */ 249 enum rockchip_pin_route_type { 250 ROUTE_TYPE_DEFAULT = 0, 251 ROUTE_TYPE_TOPGRF = 1, 252 ROUTE_TYPE_PMUGRF = 2, 253 254 ROUTE_TYPE_INVALID = -1, 255 }; 256 257 /** 258 * @drv_type: drive strength variant using rockchip_perpin_drv_type 259 * @offset: if initialized to -1 it will be autocalculated, by specifying 260 * an initial offset value the relevant source offset can be reset 261 * to a new value for autocalculating the following drive strength 262 * registers. if used chips own cal_drv func instead to calculate 263 * registers offset, the variant could be ignored. 264 */ 265 struct rockchip_drv { 266 enum rockchip_pin_drv_type drv_type; 267 int offset; 268 }; 269 270 /** 271 * @priv: common pinctrl private basedata 272 * @pin_base: first pin number 273 * @nr_pins: number of pins in this bank 274 * @name: name of the bank 275 * @bank_num: number of the bank, to account for holes 276 * @iomux: array describing the 4 iomux sources of the bank 277 * @drv: array describing the 4 drive strength sources of the bank 278 * @pull_type: array describing the 4 pull type sources of the bank 279 * @recalced_mask: bits describing the mux recalced pins of per bank 280 * @route_mask: bits describing the routing pins of per bank 281 */ 282 struct rockchip_pin_bank { 283 struct rockchip_pinctrl_priv *priv; 284 u32 pin_base; 285 u8 nr_pins; 286 char *name; 287 u8 bank_num; 288 struct rockchip_iomux iomux[4]; 289 struct rockchip_drv drv[4]; 290 enum rockchip_pin_pull_type pull_type[4]; 291 u32 recalced_mask; 292 u32 route_mask; 293 }; 294 295 #define PIN_BANK(id, pins, label) \ 296 { \ 297 .bank_num = id, \ 298 .nr_pins = pins, \ 299 .name = label, \ 300 .iomux = { \ 301 { .offset = -1 }, \ 302 { .offset = -1 }, \ 303 { .offset = -1 }, \ 304 { .offset = -1 }, \ 305 }, \ 306 } 307 308 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 309 { \ 310 .bank_num = id, \ 311 .nr_pins = pins, \ 312 .name = label, \ 313 .iomux = { \ 314 { .type = iom0, .offset = -1 }, \ 315 { .type = iom1, .offset = -1 }, \ 316 { .type = iom2, .offset = -1 }, \ 317 { .type = iom3, .offset = -1 }, \ 318 }, \ 319 } 320 321 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 322 iom3, offset0, offset1, offset2, \ 323 offset3) \ 324 { \ 325 .bank_num = id, \ 326 .nr_pins = pins, \ 327 .name = label, \ 328 .iomux = { \ 329 { .type = iom0, .offset = offset0 }, \ 330 { .type = iom1, .offset = offset1 }, \ 331 { .type = iom2, .offset = offset2 }, \ 332 { .type = iom3, .offset = offset3 }, \ 333 }, \ 334 } 335 336 #define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \ 337 iom1, iom2, iom3, \ 338 offset0, offset1, \ 339 offset2, offset3, pull0, \ 340 pull1, pull2, pull3) \ 341 { \ 342 .bank_num = id, \ 343 .nr_pins = pins, \ 344 .name = label, \ 345 .iomux = { \ 346 { .type = iom0, .offset = offset0 }, \ 347 { .type = iom1, .offset = offset1 }, \ 348 { .type = iom2, .offset = offset2 }, \ 349 { .type = iom3, .offset = offset3 }, \ 350 }, \ 351 .pull_type[0] = pull0, \ 352 .pull_type[1] = pull1, \ 353 .pull_type[2] = pull2, \ 354 .pull_type[3] = pull3, \ 355 } 356 357 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 358 { \ 359 .bank_num = id, \ 360 .nr_pins = pins, \ 361 .name = label, \ 362 .iomux = { \ 363 { .offset = -1 }, \ 364 { .offset = -1 }, \ 365 { .offset = -1 }, \ 366 { .offset = -1 }, \ 367 }, \ 368 .drv = { \ 369 { .drv_type = type0, .offset = -1 }, \ 370 { .drv_type = type1, .offset = -1 }, \ 371 { .drv_type = type2, .offset = -1 }, \ 372 { .drv_type = type3, .offset = -1 }, \ 373 }, \ 374 } 375 376 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 377 iom2, iom3, pull0, pull1, \ 378 pull2, pull3) \ 379 { \ 380 .bank_num = id, \ 381 .nr_pins = pins, \ 382 .name = label, \ 383 .iomux = { \ 384 { .type = iom0, .offset = -1 }, \ 385 { .type = iom1, .offset = -1 }, \ 386 { .type = iom2, .offset = -1 }, \ 387 { .type = iom3, .offset = -1 }, \ 388 }, \ 389 .pull_type[0] = pull0, \ 390 .pull_type[1] = pull1, \ 391 .pull_type[2] = pull2, \ 392 .pull_type[3] = pull3, \ 393 } 394 395 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 396 drv2, drv3, pull0, pull1, \ 397 pull2, pull3) \ 398 { \ 399 .bank_num = id, \ 400 .nr_pins = pins, \ 401 .name = label, \ 402 .iomux = { \ 403 { .offset = -1 }, \ 404 { .offset = -1 }, \ 405 { .offset = -1 }, \ 406 { .offset = -1 }, \ 407 }, \ 408 .drv = { \ 409 { .drv_type = drv0, .offset = -1 }, \ 410 { .drv_type = drv1, .offset = -1 }, \ 411 { .drv_type = drv2, .offset = -1 }, \ 412 { .drv_type = drv3, .offset = -1 }, \ 413 }, \ 414 .pull_type[0] = pull0, \ 415 .pull_type[1] = pull1, \ 416 .pull_type[2] = pull2, \ 417 .pull_type[3] = pull3, \ 418 } 419 420 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 421 iom2, iom3, drv0, drv1, drv2, \ 422 drv3, offset0, offset1, \ 423 offset2, offset3) \ 424 { \ 425 .bank_num = id, \ 426 .nr_pins = pins, \ 427 .name = label, \ 428 .iomux = { \ 429 { .type = iom0, .offset = -1 }, \ 430 { .type = iom1, .offset = -1 }, \ 431 { .type = iom2, .offset = -1 }, \ 432 { .type = iom3, .offset = -1 }, \ 433 }, \ 434 .drv = { \ 435 { .drv_type = drv0, .offset = offset0 }, \ 436 { .drv_type = drv1, .offset = offset1 }, \ 437 { .drv_type = drv2, .offset = offset2 }, \ 438 { .drv_type = drv3, .offset = offset3 }, \ 439 }, \ 440 } 441 442 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 443 iom2, iom3, drv0, drv1, drv2, \ 444 drv3, pull0, pull1, pull2, \ 445 pull3) \ 446 { \ 447 .bank_num = id, \ 448 .nr_pins = pins, \ 449 .name = label, \ 450 .iomux = { \ 451 { .type = iom0, .offset = -1 }, \ 452 { .type = iom1, .offset = -1 }, \ 453 { .type = iom2, .offset = -1 }, \ 454 { .type = iom3, .offset = -1 }, \ 455 }, \ 456 .drv = { \ 457 { .drv_type = drv0, .offset = -1 }, \ 458 { .drv_type = drv1, .offset = -1 }, \ 459 { .drv_type = drv2, .offset = -1 }, \ 460 { .drv_type = drv3, .offset = -1 }, \ 461 }, \ 462 .pull_type[0] = pull0, \ 463 .pull_type[1] = pull1, \ 464 .pull_type[2] = pull2, \ 465 .pull_type[3] = pull3, \ 466 } 467 468 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 469 label, iom0, iom1, iom2, \ 470 iom3, drv0, drv1, drv2, \ 471 drv3, offset0, offset1, \ 472 offset2, offset3, pull0, \ 473 pull1, pull2, pull3) \ 474 { \ 475 .bank_num = id, \ 476 .nr_pins = pins, \ 477 .name = label, \ 478 .iomux = { \ 479 { .type = iom0, .offset = -1 }, \ 480 { .type = iom1, .offset = -1 }, \ 481 { .type = iom2, .offset = -1 }, \ 482 { .type = iom3, .offset = -1 }, \ 483 }, \ 484 .drv = { \ 485 { .drv_type = drv0, .offset = offset0 }, \ 486 { .drv_type = drv1, .offset = offset1 }, \ 487 { .drv_type = drv2, .offset = offset2 }, \ 488 { .drv_type = drv3, .offset = offset3 }, \ 489 }, \ 490 .pull_type[0] = pull0, \ 491 .pull_type[1] = pull1, \ 492 .pull_type[2] = pull2, \ 493 .pull_type[3] = pull3, \ 494 } 495 496 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 497 { \ 498 .bank_num = ID, \ 499 .pin = PIN, \ 500 .func = FUNC, \ 501 .route_offset = REG, \ 502 .route_val = VAL, \ 503 .route_type = FLAG, \ 504 } 505 506 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ 507 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) 508 509 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ 510 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) 511 512 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ 513 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) 514 515 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 516 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 517 518 #define PIN_BANK_IOMUX_4_OFFSET(id, pins, label, offset0, offset1, \ 519 offset2, offset3) \ 520 PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, IOMUX_WIDTH_4BIT, \ 521 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, \ 522 IOMUX_WIDTH_4BIT, offset0, offset1, \ 523 offset2, offset3) 524 525 /** 526 * struct rockchip_mux_recalced_data: recalculate a pin iomux data. 527 * @num: bank number. 528 * @pin: pin number. 529 * @reg: register offset. 530 * @bit: index at register. 531 * @mask: mask bit 532 */ 533 struct rockchip_mux_recalced_data { 534 u8 num; 535 u8 pin; 536 u32 reg; 537 u8 bit; 538 u8 mask; 539 }; 540 541 /** 542 * struct rockchip_mux_route_data: route a pin iomux data. 543 * @bank_num: bank number. 544 * @pin: index at register or used to calc index. 545 * @func: the min pin. 546 * @route_type: the register type. 547 * @route_offset: the max pin. 548 * @route_val: the register offset. 549 */ 550 struct rockchip_mux_route_data { 551 u8 bank_num; 552 u8 pin; 553 u8 func; 554 enum rockchip_pin_route_type route_type : 8; 555 u32 route_offset; 556 u32 route_val; 557 }; 558 559 /** 560 */ 561 struct rockchip_pin_ctrl { 562 struct rockchip_pin_bank *pin_banks; 563 u32 nr_banks; 564 u32 nr_pins; 565 int grf_mux_offset; 566 int pmu_mux_offset; 567 int grf_drv_offset; 568 int pmu_drv_offset; 569 struct rockchip_mux_recalced_data *iomux_recalced; 570 u32 niomux_recalced; 571 struct rockchip_mux_route_data *iomux_routes; 572 u32 niomux_routes; 573 574 int (*set_mux)(struct rockchip_pin_bank *bank, 575 int pin, int mux); 576 int (*set_pull)(struct rockchip_pin_bank *bank, 577 int pin_num, int pull); 578 int (*set_drive)(struct rockchip_pin_bank *bank, 579 int pin_num, int strength); 580 int (*set_schmitt)(struct rockchip_pin_bank *bank, 581 int pin_num, int enable); 582 }; 583 584 /** 585 */ 586 struct rockchip_pinctrl_priv { 587 struct rockchip_pin_ctrl *ctrl; 588 struct regmap *regmap_base; 589 struct regmap *regmap_pmu; 590 struct regmap *regmap_ioc1; 591 struct regmap *regmap_rmio; 592 }; 593 594 extern const struct pinctrl_ops rockchip_pinctrl_ops; 595 int rockchip_pinctrl_probe(struct udevice *dev); 596 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 597 int *reg, u8 *bit, int *mask); 598 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); 599 int rockchip_translate_drive_value(int type, int strength); 600 int rockchip_translate_pull_value(int type, int pull); 601 602 #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ 603