1 /* 2 * (C) Copyright 2025 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _PMIC_RK801_H_ 8 #define _PMIC_RK801_H_ 9 10 #define DEV_OFF BIT(0) 11 12 #define RK8XX_ID_MSK 0xfff0 13 14 enum rk801_reg { 15 RK801_ID_DCDC1, 16 RK801_ID_DCDC2, 17 RK801_ID_DCDC4, 18 RK801_ID_DCDC3, 19 RK801_ID_LDO1, 20 RK801_ID_LDO2, 21 RK801_ID_SWITCH, 22 RK801_ID_MAX, 23 }; 24 25 #define RK801_SLP_REG_OFFSET 5 26 #define RK801_NUM_REGULATORS 7 27 28 /* RK801 Register Definitions */ 29 #define RK801_ID_MSB 0x00 30 #define RK801_ID_LSB 0x01 31 #define RK801_OTP_VER_REG 0x02 32 #define RK801_POWER_EN0_REG 0x03 33 #define RK801_POWER_EN1_REG 0x04 34 #define RK801_POWER_SLP_EN_REG 0x05 35 #define RK801_POWER_FPWM_EN_REG 0x06 36 #define RK801_SLP_LP_CONFIG_REG 0x07 37 #define RK801_BUCK_CONFIG_REG 0x08 38 #define RK801_BUCK1_ON_VSEL_REG 0x09 39 #define RK801_BUCK2_ON_VSEL_REG 0x0a 40 #define RK801_BUCK4_ON_VSEL_REG 0x0b 41 #define RK801_LDO1_ON_VSEL_REG 0x0c 42 #define RK801_LDO2_ON_VSEL_REG 0x0d 43 #define RK801_BUCK1_SLP_VSEL_REG 0x0e 44 #define RK801_BUCK2_SLP_VSEL_REG 0x0f 45 #define RK801_BUCK4_SLP_VSEL_REG 0x10 46 #define RK801_LDO1_SLP_VSEL_REG 0x11 47 #define RK801_LDO2_SLP_VSEL_REG 0x12 48 #define RK801_LDO_SW_IMAX_REG 0x13 49 #define RK801_SYS_STS_REG 0x14 50 #define RK801_SYS_CFG0_REG 0x15 51 #define RK801_SYS_CFG1_REG 0x16 52 #define RK801_SYS_CFG2_REG 0x17 53 #define RK801_SYS_CFG3_REG 0x18 54 #define RK801_SYS_CFG4_REG 0x19 55 #define RK801_SLEEP_CFG_REG 0x1a 56 #define RK801_ON_SOURCE_REG 0x1b 57 #define RK801_OFF_SOURCE_REG 0x1c 58 #define RK801_PWRON_KEY_REG 0x1d 59 #define RK801_INT_STS0_REG 0x1e 60 #define RK801_INT_MASK0_REG 0x1f 61 #define RK801_INT_CONFIG_REG 0x20 62 #define RK801_CON_BACK1_REG 0x21 63 #define RK801_CON_BACK2_REG 0x22 64 #define RK801_DATA_CON0_REG 0x23 65 #define RK801_DATA_CON1_REG 0x24 66 #define RK801_DATA_CON2_REG 0x25 67 #define RK801_DATA_CON3_REG 0x26 68 #define RK801_POWER_EXIT_SLP_SEQ0_REG 0x27 69 #define RK801_POWER_EXIT_SLP_SEQ1_REG 0x28 70 #define RK801_POWER_EXIT_SLP_SEQ2_REG 0x29 71 #define RK801_POWER_EXIT_SLP_SEQ3_REG 0x2a 72 #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ0_REG 0x2b 73 #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ1_REG 0x2c 74 #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ2_REG 0x2d 75 #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ3_REG 0x2e 76 #define RK801_BUCK_DEBUG1_REG 0x2f 77 #define RK801_BUCK_DEBUG2_REG 0x30 78 #define RK801_BUCK_DEBUG3_REG 0x31 79 #define RK801_BUCK_DEBUG4_REG 0x32 80 #define RK801_BUCK_DEBUG5_REG 0x33 81 #define RK801_BUCK_DEBUG7_REG 0x34 82 #define RK801_OTP_EN_CON_REG 0x35 83 #define RK801_TEST_CON_REG 0x36 84 #define RK801_EFUSE_CONTROL_REG 0x37 85 #define RK801_SYS_CFG3_OTP_REG 0x38 86 87 /* RK801 IRQ Definitions */ 88 #define RK801_IRQ_PWRON_FALL 0 89 #define RK801_IRQ_PWRON_RISE 1 90 #define RK801_IRQ_PWRON 2 91 #define RK801_IRQ_PWRON_LP 3 92 #define RK801_IRQ_HOTDIE 4 93 #define RK801_IRQ_VDC_RISE 5 94 #define RK801_IRQ_VDC_FALL 6 95 #define RK801_IRQ_PWRON_FALL_MSK BIT(0) 96 #define RK801_IRQ_PWRON_RISE_MSK BIT(1) 97 #define RK801_IRQ_PWRON_MSK BIT(2) 98 #define RK801_IRQ_PWRON_LP_MSK BIT(3) 99 #define RK801_IRQ_HOTDIE_MSK BIT(4) 100 #define RK801_IRQ_VDC_RISE_MSK BIT(5) 101 #define RK801_IRQ_VDC_FALL_MSK BIT(6) 102 103 /* RK801_SLP_LP_CONFIG_REG */ 104 #define RK801_BUCK_SLP_LP_EN BIT(3) 105 #define RK801_PLDO_SLP_LP_EN BIT(1) 106 #define RK801_SLP_LP_MASK (RK801_PLDO_SLP_LP_EN | RK801_BUCK_SLP_LP_EN) 107 108 /* RK801_SLEEP_CFG_REG */ 109 #define RK801_SLEEP_FUN_MSK 0x3 110 #define RK801_NONE_FUN 0x0 111 #define RK801_SLEEP_FUN 0x1 112 #define RK801_SHUTDOWN_FUN 0x2 113 #define RK801_RESET_FUN 0x3 114 115 /* RK801_SYS_CFG2_REG */ 116 #define RK801_SLEEP_POL_MSK BIT(1) 117 #define RK801_SLEEP_ACT_H BIT(1) 118 #define RK801_SLEEP_ACT_L 0 119 120 #define RK801_RST_MSK (0x3 << 4) 121 #define RK801_RST_RESTART_PMU (0x0 << 4) 122 #define RK801_RST_RESTART_REG (0x1 << 4) 123 #define RK801_RST_RESTART_REG_RESETB (0x2 << 4) 124 125 /* RK801_INT_CONFIG_REG */ 126 #define RK801_INT_POL_MSK BIT(1) 127 #define RK801_INT_ACT_H BIT(1) 128 #define RK801_INT_ACT_L 0 129 130 #define RK801_FPWM_MODE 1 131 #define RK801_AUTO_PWM_MODE 0 132 #define RK801_PLDO_HRDEC_EN BIT(6) 133 134 struct reg_data { 135 u8 reg; 136 u8 val; 137 u8 mask; 138 }; 139 140 struct rk801_priv { 141 struct virq_chip *irq_chip; 142 struct gpio_desc pwrctrl_gpio; 143 bool req_pwrctrl_dvs; 144 int variant; 145 int irq; 146 }; 147 #endif 148