1 /* 2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3 * Author: Zhihuan He <huan.he@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RV1108_PCTL_PHY_H 8 #define _ASM_ARCH_SDRAM_RV1108_PCTL_PHY_H 9 10 #include <common.h> 11 12 struct ddr_pctl { 13 u32 scfg; 14 u32 sctl; 15 u32 stat; 16 u32 intrstat; 17 u32 reserved0[(0x40 - 0x10) / 4]; 18 u32 mcmd; 19 u32 powctl; 20 u32 powstat; 21 u32 cmdtstat; 22 u32 cmdtstaten; 23 u32 reserved1[(0x60 - 0x54) / 4]; 24 u32 mrrcfg0; 25 u32 mrrstat0; 26 u32 mrrstat1; 27 u32 reserved2[(0x7c - 0x6c) / 4]; 28 u32 mcfg1; 29 u32 mcfg; 30 u32 ppcfg; 31 u32 mstat; 32 u32 lpddr2zqcfg; 33 u32 reserved3; 34 u32 dtupdes; 35 u32 dtuna; 36 u32 dtune; 37 u32 dtuprd0; 38 u32 dtuprd1; 39 u32 dtuprd2; 40 u32 dtuprd3; 41 u32 dtuawdt; 42 u32 reserved4[(0xc0 - 0xb4) / 4]; 43 u32 togcnt1u; 44 u32 tinit; 45 u32 trsth; 46 u32 togcnt100n; 47 u32 trefi; 48 u32 tmrd; 49 u32 trfc; 50 u32 trp; 51 u32 trtw; 52 u32 tal; 53 u32 tcl; 54 u32 tcwl; 55 u32 tras; 56 u32 trc; 57 u32 trcd; 58 u32 trrd; 59 u32 trtp; 60 u32 twr; 61 u32 twtr; 62 u32 texsr; 63 u32 txp; 64 u32 txpdll; 65 u32 tzqcs; 66 u32 tzqcsi; 67 u32 tdqs; 68 u32 tcksre; 69 u32 tcksrx; 70 u32 tcke; 71 u32 tmod; 72 u32 trstl; 73 u32 tzqcl; 74 u32 tmrr; 75 u32 tckesr; 76 u32 tdpd; 77 u32 trefi_mem_ddr3; 78 u32 reserved5[(0x180 - 0x14c) / 4]; 79 u32 ecccfg; 80 u32 ecctst; 81 u32 eccclr; 82 u32 ecclog; 83 u32 reserved6[(0x200 - 0x190) / 4]; 84 u32 dtuwactl; 85 u32 dturactl; 86 u32 dtucfg; 87 u32 dtuectl; 88 u32 dtuwd0; 89 u32 dtuwd1; 90 u32 dtuwd2; 91 u32 dtuwd3; 92 u32 dtuwdm; 93 u32 dturd0; 94 u32 dturd1; 95 u32 dturd2; 96 u32 dturd3; 97 u32 dtulfsrwd; 98 u32 dtulfsrrd; 99 u32 dtueaf; 100 u32 dfitctrldelay; 101 u32 dfiodtcfg; 102 u32 dfiodtcfg1; 103 u32 dfiodtrankmap; 104 u32 dfitphywrdata; 105 u32 dfitphywrlat; 106 u32 dfitphywrdatalat; 107 u32 reserved7; 108 u32 dfitrddataen; 109 u32 dfitphyrdlat; 110 u32 reserved8[(0x270 - 0x268) / 4]; 111 u32 dfitphyupdtype0; 112 u32 dfitphyupdtype1; 113 u32 dfitphyupdtype2; 114 u32 dfitphyupdtype3; 115 u32 dfitctrlupdmin; 116 u32 dfitctrlupdmax; 117 u32 dfitctrlupddly; 118 u32 reserved9; 119 u32 dfiupdcfg; 120 u32 dfitrefmski; 121 u32 dfitctrlupdi; 122 u32 reserved10[(0x2ac - 0x29c) / 4]; 123 u32 dfitrcfg0; 124 u32 dfitrstat0; 125 u32 dfitrwrlvlen; 126 u32 dfitrrdlvlen; 127 u32 dfitrrdlvlgateen; 128 u32 dfiststat0; 129 u32 dfistcfg0; 130 u32 dfistcfg1; 131 u32 reserved11; 132 u32 dfitdramclken; 133 u32 dfitdramclkdis; 134 u32 dfistcfg2; 135 u32 dfistparclr; 136 u32 dfistparlog; 137 u32 reserved12[(0x2f0 - 0x2e4) / 4]; 138 u32 dfilpcfg0; 139 u32 reserved13[(0x300 - 0x2f4) / 4]; 140 u32 dfitrwrlvlresp0; 141 u32 dfitrwrlvlresp1; 142 u32 dfitrwrlvlresp2; 143 u32 dfitrrdlvlresp0; 144 u32 dfitrrdlvlresp1; 145 u32 dfitrrdlvlresp2; 146 u32 dfitrwrlvldelay0; 147 u32 dfitrwrlvldelay1; 148 u32 dfitrwrlvldelay2; 149 u32 dfitrrdlvldelay0; 150 u32 dfitrrdlvldelay1; 151 u32 dfitrrdlvldelay2; 152 u32 dfitrrdlvlgatedelay0; 153 u32 dfitrrdlvlgatedelay1; 154 u32 dfitrrdlvlgatedelay2; 155 u32 dfitrcmd; 156 u32 reserved14[(0x3f8 - 0x340) / 4]; 157 u32 ipvr; 158 u32 iptr; 159 }; 160 check_member(ddr_pctl, iptr, 0x03fc); 161 162 struct ddr_phy { 163 u32 phy_reg0; 164 u32 phy_reg1; 165 u32 phy_reg2; 166 u32 phy_reg3; 167 u32 reserved0; 168 u32 phy_reg5; 169 u32 phy_reg6; 170 u32 reserveds1[(0x24 - 0x1c) / 4]; 171 u32 phy_reg9; 172 u32 reserveds2[(0x2c - 0x28) / 4]; 173 u32 phy_regb; 174 u32 phy_regc; 175 u32 reserveds3[(0x44 - 0x34) / 4]; 176 u32 phy_reg11; 177 u32 phy_reg12; 178 u32 phy_reg13; 179 u32 phy_reg14; 180 u32 reserved4; 181 u32 phy_reg16; 182 u32 phy_reg17; 183 u32 phy_reg18; 184 u32 reserveds5[(0x80 - 0x64) / 4]; 185 u32 phy_reg20; 186 u32 phy_reg21; 187 u32 reserveds6[(0x98 - 0x88) / 4]; 188 u32 phy_reg26; 189 u32 phy_reg27; 190 u32 phy_reg28; 191 u32 reserveds7[(0xac - 0xa4) / 4]; 192 u32 phy_reg2b; 193 u32 phy_reg2c; 194 u32 reserveds8[(0xb8 - 0xb4) / 4]; 195 u32 phy_reg2e; 196 u32 phy_reg2f; 197 u32 phy_reg30; 198 u32 phy_reg31; 199 u32 reserveds9[(0xd8 - 0xc8) / 4]; 200 u32 phy_reg36; 201 u32 phy_reg37; 202 u32 phy_reg38; 203 u32 reserveds10[(0xec - 0xe4) / 4]; 204 u32 phy_reg3b; 205 u32 phy_reg3c; 206 u32 reserveds11[(0xf8 - 0xf4) / 4]; 207 u32 phy_reg3e; 208 u32 phy_reg3f; 209 u32 reserveds12[(0x1c0 - 0x100) / 4]; 210 u32 phy_reg_skew_cs0data[(0x218 - 0x1c0) / 4]; 211 u32 reserveds13[(0x28c - 0x218) / 4]; 212 u32 phy_vref; 213 /*dll bypass switch reg,0x290*/ 214 u32 phy_regdll; 215 u32 reserveds14[(0x2c0 - 0x294) / 4]; 216 u32 phy_reg_ca_skew[(0x2f8 - 0x2c0) / 4]; 217 u32 reserveds15[(0x300 - 0x2f8) / 4]; 218 u32 phy_reg_skew_cs1data[(0x358 - 0x300) / 4]; 219 u32 reserveds16[(0x3c0 - 0x358) / 4]; 220 u32 phy_regf0; 221 u32 phy_regf1; 222 u32 reserveds17[(0x3e4 - 0x3c8) / 4]; 223 u32 phy_regf9; 224 u32 phy_regfa; 225 u32 phy_regfb; 226 u32 phy_regfc; 227 u32 reserved18; 228 u32 reserved19; 229 u32 phy_regff; 230 }; 231 check_member(ddr_phy, phy_regff, 0x03fc); 232 233 union noc_timing_t { 234 u32 d32; 235 struct { 236 unsigned acttoact : 6; 237 unsigned rdtomiss : 6; 238 unsigned wrtomiss : 6; 239 unsigned burstlen : 3; 240 unsigned rdtowr : 5; 241 unsigned wrtord : 5; 242 unsigned bwratio : 1; 243 } b; 244 }; 245 246 union noc_activate_t { 247 u32 d32; 248 struct { 249 unsigned rrd : 4; 250 unsigned faw : 6; 251 unsigned fawbank : 1; 252 unsigned reserved : 21; 253 } b; 254 }; 255 256 struct ddr_timing { 257 u32 freq; 258 struct pctl_timing { 259 u32 togcnt1u; 260 u32 tinit; 261 u32 trsth; 262 u32 togcnt100n; 263 u32 trefi; 264 u32 tmrd; 265 u32 trfc; 266 u32 trp; 267 u32 trtw; 268 u32 tal; 269 u32 tcl; 270 u32 tcwl; 271 u32 tras; 272 u32 trc; 273 u32 trcd; 274 u32 trrd; 275 u32 trtp; 276 u32 twr; 277 u32 twtr; 278 u32 texsr; 279 u32 txp; 280 u32 txpdll; 281 u32 tzqcs; 282 u32 tzqcsi; 283 u32 tdqs; 284 u32 tcksre; 285 u32 tcksrx; 286 u32 tcke; 287 u32 tmod; 288 u32 trstl; 289 u32 tzqcl; 290 u32 tmrr; 291 u32 tckesr; 292 u32 tdpd; 293 u32 trefi_mem_ddr3; 294 } pctl_timing; 295 struct phy_timing { 296 u32 mr[4]; 297 u32 bl; 298 u32 cl_al; 299 } phy_timing; 300 union noc_timing_t noc_timing; 301 u32 readlatency; 302 union noc_activate_t activate; 303 u32 devtodev; 304 }; 305 306 struct ddr_config { 307 /* 308 * 000: lpddr 309 * 001: ddr 310 * 010: ddr2 311 * 011: ddr3 312 * 100: lpddr2-s2 313 * 101: lpddr2-s4 314 * 110: lpddr3 315 */ 316 u32 ddr_type; 317 u32 chn_cnt; 318 u32 rank; 319 u32 cs0_row; 320 u32 cs1_row; 321 322 /* 2: 4bank, 3: 8bank */ 323 u32 bank; 324 u32 col; 325 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 326 u32 dbw; 327 /* bw(0: 8bit, 1: 16bit, 2: 32bit) */ 328 u32 bw; 329 }; 330 331 struct ddr_schedule { 332 u32 col; 333 u32 bank; 334 u32 row; 335 }; 336 337 enum { 338 PHY_LOW_SPEED_MHZ = 400, 339 /* PHY_REG0 */ 340 CHN_ENABLE_SHIFT = 4, 341 DQ_16BIT_EN_MASK = 3 << 4, 342 DQ_16BIT_EN = 3 << 4, 343 DQ_32BIT_EN_MASK = 0xf << 4, 344 DQ_32BIT_EN = 0xf << 4, 345 RESET_DIGITAL_CORE_SHIFT = 3, 346 RESET_DIGITAL_CORE_MASK = 1 << RESET_DIGITAL_CORE_SHIFT, 347 RESET_DIGITAL_CORE_ACT = 0, 348 RESET_DIGITAL_CORE_DIS = 1, 349 RESET_ANALOG_LOGIC_SHIFT = 2, 350 RESET_ANALOG_LOGIC_MASK = 1 << RESET_ANALOG_LOGIC_SHIFT, 351 RESET_ANALOG_LOGIC_ACT = 0, 352 RESET_ANALOG_LOGIC_DIS = 1, 353 354 /* PHY_REG1 */ 355 MEMORY_SELECT_DDR3 = 0, 356 MEMORY_SELECT_DDR2 = 1, 357 MEMORY_SELECT_LPDDR2 = 2, 358 PHY_BL_8 = 1 << 2, 359 PHY_BL_4 = 0 << 2, 360 361 /* PHY_REG2 */ 362 DQS_GATE_TRAINING_SEL_CS0 = 1 << 5, 363 DQS_GATE_TRAINING_ACT = 1, 364 DQS_GATE_TRAINING_DIS = 0, 365 366 /* PHY_REG12 */ 367 CMD_PRCOMP_SHIFT = 3, 368 CMD_PRCOMP_MASK = 0x1f << CMD_PRCOMP_SHIFT, 369 370 /* DDRPHY_REG13 */ 371 CMD_DLL_BYPASS_SHIFT = 4, 372 CMD_DLL_BYPASS = 1, 373 CMD_DLL_BYPASS_MASK = 1, 374 CMD_DLL_BYPASS_DISABLE = 0, 375 376 /* DDRPHY_REG14 */ 377 CK_DLL_BYPASS_SHIFT = 3, 378 CK_DLL_BYPASS = 1, 379 CK_DLL_BYPASS_DISABLE = 0, 380 381 /* DDRPHY_REG26 */ 382 LEFT_CHN_A_DQ_DLL_SHIFT = 4, 383 LEFT_CHN_A_DQ_DLL_BYPASS = 1, 384 LEFT_CHN_A_DQ_DLL_BYPASS_MASK = 1, 385 LEFT_CHN_A_DQ_DLL_BYPASS_DIS = 0, 386 387 /* DDRPHY_REG27 */ 388 LEFT_CHN_A_DQS_DLL_SHIFT = 3, 389 LEFT_CHN_A_DQS_DLL_BYPASS = 1, 390 LEFT_CHN_A_DQS_DLL_BYPASS_DIS = 0, 391 392 /* DDRPHY_REG28 */ 393 LEFT_CHN_A_READ_DQS_22_5_DELAY = 1, 394 LEFT_CHN_A_READ_DQS_45_DELAY = 2, 395 396 /* DDRPHY_REG36 */ 397 RIGHT_CHN_A_DQ_DLL_SHIFT = 4, 398 RIGHT_CHN_A_DQ_DLL_BYPASS = 1, 399 RIGHT_CHN_A_DQ_DLL_BYPASS_MASK = 1, 400 RIGHT_CHN_A_DQ_DLL_BYPASS_DIS = 0, 401 402 /* DDRPHY_REG37 */ 403 RIGHT_CHN_A_DQS_DLL_SHIFT = 3, 404 RIGHT_CHN_A_DQS_DLL_BYPASS = 1, 405 RIGHT_CHN_A_DQS_DLL_BYPASS_DIS = 0, 406 407 /* DDRPHY_REG38 */ 408 RIGHT_CHN_A_READ_DQS_22_5_DELAY = 1, 409 RIGHT_CHN_A_READ_DQS_45_DELAY = 2, 410 411 /* PHY_REGDLL */ 412 RIGHT_CHN_A_TX_DQ_BYPASS_SHIFT = 2, 413 RIGHT_CHN_A_TX_DQ_BYPASS_SET = 1, 414 RIGHT_CHN_A_TX_DQ_BYPASS_DIS = 0, 415 LEFT_CHN_A_TX_DQ_BYPASS_SHIFT = 1, 416 LEFT_CHN_A_TX_DQ_BYPASS_SET = 1, 417 LEFT_CHN_A_TX_DQ_BYPASS_DIS = 0, 418 CMD_CK_DLL_BYPASS_SHIFT = 0, 419 CMD_CK_DLL_BYPASS_SET = 1, 420 CMD_CK_DLL_BYPASS_DIS = 0, 421 422 /* PHY_REGFF */ 423 CHN_A_TRAINING_DONE_MASK = 3, 424 CHN_A_HIGH_8BIT_TRAINING_DONE = 1 << 1, 425 CHN_A_LOW_8BIT_TRAINING_DONE = 1, 426 }; 427 428 /*PCTL*/ 429 enum { 430 /* PCTL_SCTL */ 431 INIT_STATE = 0, 432 CFG_STATE = 1, 433 GO_STATE = 2, 434 SLEEP_STATE = 3, 435 WAKEUP_STATE = 4, 436 437 /* PCTL_STAT*/ 438 PCTL_CTL_STAT_MASK = 0x7, 439 INIT_MEM = 0, 440 CONFIG = 1, 441 CONFIG_REQ = 2, 442 ACCESS = 3, 443 ACCESS_REQ = 4, 444 LOW_POWER = 5, 445 LOW_POWER_ENTRY_REQ = 6, 446 LOW_POWER_EXIT_REQ = 7, 447 448 /* PCTL_MCMD */ 449 START_CMD = 0x80000000, 450 RANK_SEL_SHIFT = 20, 451 RANK_SEL_CS0 = 1, 452 RANK_SEL_CS1 = 2, 453 RANK_SEL_CS0_CS1 = 3, 454 BANK_ADDR_SHIFT = 17, 455 BANK_ADDR_MASK = 0x7, 456 CMD_ADDR_SHIFT = 4, 457 CMD_ADDR_MASK = 0x1fff, 458 LPDDR23_MA_SHIFT = 4, 459 LPDDR23_MA_MASK = 0xff, 460 LPDDR23_OP_SHIFT = 12, 461 LPDDR23_OP_MASK = 0xff, 462 DDR3_DLL_RESET = 1 << 8, 463 DESELECT_CMD = 0x0, 464 PREA_CMD = 0x1, 465 REF_CMD = 0x2, 466 MRS_CMD = 0x3, 467 ZQCS_CMD = 0x4, 468 ZQCL_CMD = 0x5, 469 RSTL_CMD = 0x6, 470 MPR_CMD = 0x8, 471 DFICTRLUPD_CMD = 0xa, 472 MR0 = 0x0, 473 MR1 = 0x1, 474 MR2 = 0x2, 475 MR3 = 0x3, 476 477 /* PCTL_POWCTL */ 478 POWER_UP_START = 1, 479 POWER_UP_START_MASK = 1, 480 481 /* PCTL_POWSTAT */ 482 POWER_UP_DONE = 1, 483 484 /*PCTL_PPCFG*/ 485 PPMEM_EN_MASK = 1, 486 PPMEM_EN = 1, 487 PPMEM_DIS = 0, 488 /* PCTL_TREFI */ 489 UPD_REF = 0x80000000, 490 491 /* PCTL_DFISTCFG0 */ 492 DFI_DATA_BYTE_DISABLE_EN_SHIFT = 2, 493 DFI_DATA_BYTE_DISABLE_EN = 1, 494 DFI_FREQ_RATIO_EN_SHIFT = 1, 495 DFI_FREQ_RATIO_EN = 1, 496 DFI_INIT_START_SHIFT = 0, 497 DFI_INIT_START_EN = 1, 498 499 /* PCTL_DFISTCFG1 */ 500 DFI_DRAM_CLK_DISABLE_EN_DPD_SHIFT = 1, 501 DFI_DRAM_CLK_DISABLE_EN_DPD = 1, 502 DFI_DRAM_CLK_DISABLE_EN_SHIFT = 0, 503 DFI_DRAM_CLK_DISABLE_EN = 1, 504 505 /* PCTL_DFISTCFG2 */ 506 PARITY_EN_SHIFT = 1, 507 PARITY_EN = 1, 508 PARITY_INTR_EN_SHIFT = 0, 509 PARITY_INTR_EN = 1, 510 511 /* PCTL_DFILPCFG0 */ 512 DFI_LP_EN_PD = 1, 513 DFI_LP_WAKEUP_PD_SHIFT = 4, 514 DFI_LP_WAKEUP_PD_32_CYCLES = 1, 515 DFI_LP_EN_SR_SHIFT = 8, 516 DFI_LP_EN_SR = 1, 517 DFI_LP_WAKEUP_SR_SHIFT = 12, 518 DFI_LP_WAKEUP_SR_32_CYCLES = 1, 519 DFI_TLP_RESP_SHIFT = 16, 520 DFI_TLP_RESP = 5, 521 522 /* PCTL_DFITPHYUPDTYPE0 */ 523 TPHYUPD_TYPE0 = 1, 524 525 /* PCTL_DFITPHYRDLAT */ 526 TPHY_RDLAT = 0xd, 527 528 /* PCTL_DFITPHYWRDATA */ 529 TPHY_WRDATA = 0x0, 530 531 /* PCTL_DFIUPDCFG */ 532 DFI_PHYUPD_DISABLE = 0 << 1, 533 DFI_CTRLUPD_DISABLE = 0, 534 535 /* PCTL_DFIODTCFG */ 536 RANK0_ODT_WRITE_SEL_SHIFT = 3, 537 RANK0_ODT_WRITE_SEL = 1, 538 RANK0_ODT_WRITE_DIS = 0, 539 RANK1_ODT_WRITE_SEL_SHIFT = 11, 540 RANK1_ODT_WRITE_SEL = 1, 541 RANK1_ODT_WRITE_DIS = 0, 542 543 /* PCTL_DFIODTCFG1 */ 544 ODT_LEN_BL8_W_SHIFT = 16, 545 ODT_LEN_BL8_W = 7, 546 ODT_LEN_BL8_W_0 = 0, 547 548 /* PCTL_MCFG */ 549 MDDR_LPDDR23_CLOCK_STOP_IDLE_DIS = 0 << 24, 550 LPDDR2_EN = 3 << 22, 551 DDR3_EN = 1 << 5, 552 DDR2_EN = 0 << 5, 553 LPDDR2_S4 = 1 << 6, 554 MEM_BL_8 = 1, 555 MEM_BL_4 = 0, 556 MDDR_LPDDR2_BL_4 = 1 << 20, 557 MDDR_LPDDR2_BL_8 = 2 << 20, 558 TFAW_CFG_5_TDDR = 1 << 18, 559 TFAW_CFG_6_TDDR = 2 << 18, 560 PD_EXIT_SLOW_EXIT_MODE = 0 << 17, 561 PD_EXIT_FAST_EXIT_MODE = 1 << 17, 562 PD_TYPE_ACT_PD = 1 << 16, 563 PD_IDLE_DISABLE = 0 << 8, 564 PD_IDLE_MASK = 0xff << 8, 565 PD_IDLE_SHIFT = 8, 566 TWO_T_SHIFT = 3, 567 568 /* PCTL_MCFG1 */ 569 SR_IDLE_MASK = 0xff, 570 HW_EXIT_IDLE_EN_SHIFT = 31, 571 HW_EXIT_IDLE_EN_MASK = 1 << HW_EXIT_IDLE_EN_SHIFT, 572 HW_EXIT_IDLE_EN = 1 << HW_EXIT_IDLE_EN_SHIFT, 573 574 /* PCTL_SCFG */ 575 HW_LOW_POWER_EN = 1, 576 }; 577 578 enum { 579 /* PHY_DDR3_RON_RTT */ 580 PHY_RON_RTT_DISABLE = 0, 581 PHY_RON_RTT_451OHM = 1, 582 PHY_RON_RTT_225OHM = 2, 583 PHY_RON_RTT_150OHM = 3, 584 PHY_RON_RTT_112OHM = 4, 585 PHY_RON_RTT_90OHM = 5, 586 PHY_RON_RTT_75OHM = 6, 587 PHY_RON_RTT_64OHM = 7, 588 589 PHY_RON_RTT_56OHM = 16, 590 PHY_RON_RTT_50OHM = 17, 591 PHY_RON_RTT_45OHM = 18, 592 PHY_RON_RTT_41OHM = 19, 593 PHY_RON_RTT_37OHM = 20, 594 PHY_RON_RTT_34OHM = 21, 595 PHY_RON_RTT_33OHM = 22, 596 PHY_RON_RTT_30OHM = 23, 597 598 PHY_RON_RTT_28OHM = 24, 599 PHY_RON_RTT_26OHM = 25, 600 PHY_RON_RTT_25OHM = 26, 601 PHY_RON_RTT_23OHM = 27, 602 PHY_RON_RTT_22OHM = 28, 603 PHY_RON_RTT_21OHM = 29, 604 PHY_RON_RTT_20OHM = 30, 605 PHY_RON_RTT_19OHM = 31, 606 }; 607 608 #endif 609