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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting 92 // therefrom. 93 // 94 // 95 /// @file regMVD.h 96 /// @brief Hardware register definition for Video Decoder 97 /// @author MStar Semiconductor Inc. 98 // 99 /////////////////////////////////////////////////////////////////////////////// 100 101 #ifndef _REG_AUDIO_H_ 102 #define _REG_AUDIO_H_ 103 104 #include "audio_mbox.h" 105 #include "audio_comm2.h" 106 #include "decR2_proj.h" 107 108 #define A3_PATCH_DMA_OLD_MODE 1 109 110 /////////////////////////////////////////////////////////////////////////////// 111 // Constant & Macro Definition 112 /////////////////////////////////////////////////////////////////////////////// 113 //--------------------------------------------------------------------------- 114 // Base Address 115 //--------------------------------------------------------------------------- 116 #define AUDIO_REG_BASE 0x2C00 // 0x2C00 - 0x2DFF 117 #define MIU0_REG_BASE 0x1200 118 #define MIU1_REG_BASE 0x0600 119 120 //--------------------------------------------------------------------------- 121 // AUDIO SIF Register 122 //--------------------------------------------------------------------------- 123 #define REG_AUDIO_ASIF_CONFIG0 0x2CC0 124 #define REG_AUDIO_ASIF_CONFIG1 0x2CC2 125 #define REG_AUDIO_ASIF_CONFIG2 0x2CC4 126 #define REG_AUDIO_ASIF_CONFIG3 0x2CC6 127 #define REG_AUDIO_ASIF_CONFIG4 0x2CC8 128 #define REG_AUDIO_ASIF_ICTRL 0x2CCA 129 #define REG_AUDIO_ASIF_AMUX 0x2CCC 130 #define REG_AUDIO_ASIF_TST 0x2CCE 131 #define REG_AUDIO_ASIF_ADCREF 0x2CD0 132 #define REG_AUDIO_SIFPLL_CTRL 0x2CD2 133 #define REG_AUDIO_SIFPLL_MN 0x2CD4 134 #define REG_AUDIO_SIFPLL_TEST 0x2CD6 135 #define REG_AUDIO_SIFPLL_EXT 0x2CD8 136 #define REG_AUDIO_SIFPLL_STATUS 0x2CDA 137 #define REG_AUDIO_ASIF_TST_EXT 0x2CDC 138 #define REG_AUDIO_VIF_CONFIG0 0x2CDE 139 //-------------------------------- 140 // AUDIO SIF Register Value 141 //-------------------------------- 142 #define VAL0_REG_AUDIO_ASIF_CONFIG0 0x0200 143 #define VAL0_REG_AUDIO_ASIF_CONFIG1 0x0070 144 #define VAL0_REG_AUDIO_ASIF_CONFIG2 0x1200 145 #define VAL0_REG_AUDIO_ASIF_CONFIG3 0x1000 146 #define VAL0_REG_AUDIO_ASIF_CONFIG4 0x0090 147 #define VAL0_REG_AUDIO_ASIF_ICTRL 0x1555 148 #define VAL0_REG_AUDIO_ASIF_AMUX 0x00EA 149 #define VAL0_REG_AUDIO_ASIF_TST 0x0004 150 #define VAL0_REG_AUDIO_ASIF_ADCREF 0x6C00 151 #define VAL0_REG_AUDIO_SIFPLL_CTRL 0x1009 152 #define VAL0_REG_AUDIO_SIFPLL_MN 0x1109 153 #define VAL0_REG_AUDIO_SIFPLL_TEST 0x0000 154 #define VAL0_REG_AUDIO_SIFPLL_EXT 0x0001 155 #define VAL0_REG_AUDIO_SIFPLL_STATUS 0x2CDA 156 #define VAL0_REG_AUDIO_ASIF_TST_EXT 0x0000 157 #define VAL0_REG_AUDIO_VIF_CONFIG0 0x0000 158 #define MASK_REG_AUDIO_VIF_CONFIG0 0x0040 159 #define VAL1_REG_AUDIO_VIF_CONFIG0 0x0040 160 #define VAL2_REG_AUDIO_VIF_CONFIG0 0x0000 161 162 //--------------------------------------------------------------------------- 163 // AUDIO Advance Sound Register 164 //--------------------------------------------------------------------------- 165 #define REG_SOUND_ADV_CFG0 M2S_MBOX_ADVSND_EN+0 166 #define REG_SOUND_ADV_CFG1 M2S_MBOX_ADVSND_EN+1 167 #define REG_SOUND_ADV_CFG2 M2S_MBOX_ADVSND_EN+2 168 #define REG_SOUND_ADV_CFG3 M2S_MBOX_ADVSND_EN+3 169 170 //--------------------------------------------------------------------------- 171 // AUDIO 0x1E00 BANK Register 172 //--------------------------------------------------------------------------- 173 #define REG_CHIP_ID_MAJOR 0x1ECC 174 #define REG_CHIP_ID_MINOR 0x1ECD 175 #define REG_CHIP_VERSION 0x1ECE 176 #define REG_CHIP_REVISION 0x1ECF 177 178 //--------------------------------------------------------------------------- 179 // AUDIO 0x2A00 BANK Register 180 //--------------------------------------------------------------------------- 181 #define REG_DEC_IDMA_CTRL0 0x2A00 182 183 #define REG_DEC_DSP_BRG_DATA_L 0x2A02 184 #define REG_DEC_DSP_BRG_DATA_H 0x2A03 185 #define REG_DEC_IDMA_WRBASE_ADDR_L 0x2A04 186 #define REG_DEC_IDMA_WRBASE_ADDR_H 0x2A05 187 188 #define REG_DEC_IDMA_RDBASE_ADDR_L 0x2A08 189 #define REG_DEC_IDMA_RDBASE_ADDR_H 0x2A09 190 191 #define REG_DEC_IDMA_RDDATA_H_0 0x2A0C 192 #define REG_DEC_IDMA_RDDATA_H_1 0x2A0D 193 #define REG_DEC_IDMA_RDDATA_L 0x2A0E 194 195 #define REG_DEC_DSP_ICACHE_BASE_L 0x2A10 196 #define REG_DEC_DSP_ICACHE_BASE_H 0x2A11 197 198 #define REG_DEC_AUD_DTRL 0x2A20 199 #define REG_DEC_MAD_OFFSET_BASE_L 0x2A22 200 #define REG_DEC_MAD_OFFSET_BASE_H 0x2A24 201 #define REG_DEC_MBASE_H 0x2A26 202 #define REG_DEC_MSIZE_H 0x2A28 203 #define REG_DEC_DECODE_CMD 0x2A2C 204 #define REG_DEC_ENCODE_CMD 0x2A2D // kochien added for MPEG encoder 205 #define REG_DEC_MCFG 0x2A2A 206 207 #define REG_DEC_DSPDMA_CFG 0x2A36 208 209 #define REG_DEC_BDMA_CFG 0x2A40 210 #define REG_DEC_MAD_OFFSET_BASE_EXT 0x2A48 211 212 #define REG_MAD_DMA_IDLE_RESET 0x2A59 213 214 #define REG_FD230_SELECT 0x2A7E 215 216 #define REG_SE_IDMA_CTRL0 0x2A80 217 218 #define REG_SE_DSP_BRG_DATA_L 0x2A82 219 #define REG_SE_DSP_BRG_DATA_H 0x2A83 220 #define REG_SE_IDMA_WRBASE_ADDR_L 0x2A84 221 #define REG_SE_IDMA_WRBASE_ADDR_H 0x2A85 222 223 #define REG_SE_IDMA_RDBASE_ADDR_L 0x2A88 224 #define REG_SE_IDMA_RDBASE_ADDR_H 0x2A89 225 226 #define REG_SE_IDMA_RDDATA_H_0 0x2A8C 227 #define REG_SE_IDMA_RDDATA_H_1 0x2A8D 228 #define REG_SE_IDMA_RDDATA_L 0x2A8E 229 230 #define REG_SE_DSP_ICACHE_BASE_L 0x2A90 231 #define REG_SE_DSP_ICACHE_BASE_H 0x2A91 232 233 #define REG_SE_AUD_DTRL 0x2AA0 234 #define REG_SE_MAD_OFFSET_BASE_L 0x2AA2 235 #define REG_SE_MAD_OFFSET_BASE_H 0x2AA4 236 #define REG_SE_MBASE_H 0x2AA6 237 #define REG_SE_MSIZE_H 0x2AA8 238 #define REG_SE_DECODE_CMD 0x2AAC 239 #define REG_SE_MCFG 0x2AAA 240 241 #define REG_SE_DSPDMA_CFG 0x2AB6 242 243 #define REG_SE_BDMA_CFG 0x2AC0 244 #define REG_SE_MAD_OFFSET_BASE_EXT 0x2AC8 245 246 #define REG_SE_DMA_IDLE_RESET 0x2AD9 247 248 //--------------------------------------------------------------------------- 249 // AUDIO 0x2B00 BANK Register 250 //--------------------------------------------------------------------------- 251 #define REG_RIU_MAIL_00 0x2B40 252 253 #define REG_AUDIO_DMA_RD_CTRL_0 0x2B80 254 #define REG_AUDIO_DMA_RD_CTRL_1 0x2B82 255 #define REG_AUDIO_DMA_RD_CTRL_2 0x2B84 256 #define REG_AUDIO_DMA_RD_CTRL_3 0x2B86 257 #define REG_AUDIO_DMA_RD_CTRL_4 0x2B88 258 #define REG_AUDIO_DMA_RD_CTRL_5 0x2B8A 259 #define REG_AUDIO_DMA_RD_CTRL_6 0x2B8C 260 #define REG_AUDIO_DMA_RD_CTRL_7 0x2B8E 261 #define REG_AUDIO_DMA_RD_CTRL_8 0x2B90 262 #define REG_AUDIO_DMA_RD_CTRL_9 0x2B92 263 #define REG_AUDIO_DMA_RD_CTRL_10 0x2B94 264 #define REG_AUDIO_DMA_RD_CTRL_11 0x2B96 265 #define REG_AUDIO_DMA_RD_CTRL_12 0x2B98 266 #define REG_AUDIO_DMA_RD_CTRL_13 0x2B9A 267 #define REG_AUDIO_DMA_RD_CTRL_14 0x2B9C 268 #define REG_AUDIO_DMA_RD_CTRL_15 0x2B9E 269 #define REG_AUDIO_DMA_RD_CTRL_16 0x2BA0 270 #define REG_AUDIO_DMA_RD_CTRL_17 0x2BA2 271 #define REG_AUDIO_DMA_RD_CTRL_18 0x2BA4 272 #define REG_AUDIO_DMA_RD_CTRL_19 0x2BA6 273 274 //--------------------------------------------------------------------------- 275 // AUDIO 0x2C00 BANK Register 276 // AUDIO Common Register 277 //--------------------------------------------------------------------------- 278 #define REG_AUDIO_SOFT_RESET 0x2C00 279 #define REG_AUDIO_INPUT_CFG 0x2C02 280 #define REG_AUDIO_STATUS_DVB_FREQ 0x2C04 281 #define REG_AUDIO_AUDIO_INIT_CHECK 0x2C05 //dummy reg check audio_init is DONE 282 #define REG_AUDIO_STATUS_I2S_FREQ 0x2C06 283 #define REG_AUDIO_STATUS_SIF_FREQ 0x2C08 284 #define REG_AUDIO_SPDIF_IN_CFG 0x2C0A 285 #define REG_AUDIO_STATUS_INPUT 0x2C0C 286 #define REG_AUDIO_STATUS_SPDIF_IN_FREQ 0x2C0E 287 #define REG_AUDIO_STATUS_SPDIF_IN_CS0 0x2C10 288 #define REG_AUDIO_STATUS_SPDIF_IN_CS1 0x2C12 289 #define REG_AUDIO_STATUS_SPDIF_IN_CS2 0x2C14 290 #define REG_AUDIO_STATUS_SPDIF_IN_CS3 0x2C16 291 #define REG_AUDIO_STATUS_SPDIF_IN_CS4 0x2C18 292 #define REG_AUDIO_STATUS_SPDIF_IN_PC 0x2C1A 293 #define REG_AUDIO_STATUS_SPDIF_IN_PD 0x2C1C 294 295 #define REG_AUDIO_DMA_RD_SYNTH_NF 0x2C20 296 #define REG_AUDIO_STATUS_SYNTH 0x2C2C 297 #define REG_AUDIO_STATUS_HDMI_PC 0x2C40 298 #define REG_AUDIO_STATUS_HDMI_PD 0x2C42 299 #define REG_AUDIO_HDMI_MATRIX0 0x2C44 300 #define REG_AUDIO_HDMI_MATRIX1 0x2C46 301 #define REG_AUDIO_DOWN_SAMPLE 0x2C48 302 303 #define REG_AUDIO_BT_CTRL1 0x2C50 304 #define REG_AUDIO_BT_CTRL2 0x2C52 305 #define REG_AUDIO_BT_CTRL3 0x2C54 306 #define REG_AUDIO_BT_CTRL4 0x2C56 307 308 #define REG_AUDIO_DECIMATION_CFG 0x2C58 309 310 #define REG_AUDIO_DECODER1_CFG 0x2C60 311 #define REG_AUDIO_DECODER2_CFG 0x2C62 312 #define REG_AUDIO_DECODER3_CFG 0x2C61 313 #define REG_AUDIO_DECODER4_CFG 0x2C63 314 #define REG_AUDIO_DECODER5_CFG 0x2C25 315 #define REG_AUDIO_CH1_CFG 0x2C64 316 #define REG_AUDIO_CH2_CFG 0x2C66 317 #define REG_AUDIO_CH3_CFG 0x2C68 318 #define REG_AUDIO_CH4_CFG 0x2C6A 319 #define REG_AUDIO_CH5_CFG 0x2C65 320 #define REG_AUDIO_CH6_CFG 0x2C67 321 #define REG_AUDIO_CH7_CFG 0x2C69 322 #define REG_AUDIO_CH8_CFG 0x2C6B 323 324 #define REG_AUDIO_INPUT_REGEN_CFG 0x2C6C 325 326 #define REG_AUDIO_DOUT_FIX_VAL1 0x2C70 327 #define REG_AUDIO_DOUT_FIX_VAL2 0x2C72 328 #define REG_AUDIO_DOUT_FIX_VAL3 0x2C74 329 330 #define REG_AUDIO_SPDIF_OUT_CS0 0x2C80 331 #define REG_AUDIO_SPDIF_OUT_CS1 0x2C82 332 #define REG_AUDIO_SPDIF_OUT_CS2 0x2C84 333 #define REG_AUDIO_SPDIF_OUT_CS3 0x2C86 334 #define REG_AUDIO_SPDIF_OUT_CS4 0x2C88 335 #define REG_AUDIO_SPDIF_OUT_CFG 0x2C8A 336 #define REG_AUDIO_SPDIF2_OUT_CS0 0x2C81 337 #define REG_AUDIO_SPDIF2_OUT_CS1 0x2C83 338 #define REG_AUDIO_SPDIF2_OUT_CS2 0x2C85 339 #define REG_AUDIO_SPDIF2_OUT_CS3 0x2C87 340 #define REG_AUDIO_SPDIF2_OUT_CS4 0x2C89 341 #define REG_AUDIO_SPDIF2_OUT_CFG 0x2C5E 342 #define REG_AUDIO_I2S_OUT1_CFG 0x2C8C 343 344 #define REG_AUDIO_PAD_CFG 0x2C90 345 #define REG_AUDIO_MUTE_CFG 0x2C92 346 #define REG_AUDIO_MUTE_CTRL1 0x2C94 347 #define REG_AUDIO_MUTE_CTRL2 0x2C96 348 #define REG_AUDIO_MUTE_CTRL3 0x2C98 349 #define REG_AUDIO_MUTE_CTRL4 0x2C9A 350 351 #define REG_AUDIO_CODEC_SYNTH 0x2CA0 352 #define REG_CODEC_SYNTH_H 0x2CA1 353 #define REG_AUDIO_PLL_REF_CFG 0x2CA2 354 #define REG_AUDIO_CLK_CFG0 0x2CA4 355 #define REG_CLK_CFG0 0x2CA4 356 #define REG_AUDIO_CLK_CFG1 0x2CA6 357 #define REG_AUDIO_CLK_CFG2 0x2CA8 358 #define REG_AUDIO_CLK_CFG3 0x2CAA 359 #define REG_AUDIO_CLK_CFG4 0x2CAC 360 #define REG_AUDIO_CLK_CFG5 0x2CAE 361 #define REG_AUDIO_CLK_CFG6 0x2CB0 362 #define REG_AUDIO_SYNTH_EXPANDER 0x2CB2 363 #define REG_AUDIO_SYNTH_768_CFG0 0x2CB4 364 #define REG_AUDIO_SYNTH_768_CFG1 0x2CB6 365 #define REG_AUDIO_SYNTH_768_FREQ 0x2CB8 366 #define REG_AUDIO_OUT_256FS_SEL 0x2CBA 367 368 #define REG_AUDIO_CODEC_CFG0 0x2CE0 369 #define REG_AUDIO_CODEC_CFG1 0x2CE2 370 #define REG_AUDIO_CODEC_CFG2 0x2CE4 371 #define REG_AUDIO_CODEC_CFG3 0x2CE6 372 #define REG_AUDIO_CODEC_CFG4 0x2CE8 373 #define REG_AUDIO_CODEC_CFG5 0x2CEA 374 #define REG_AUDIO_CODEC_CFG6 0x2CEC 375 #define REG_AUDIO_CODEC_CFG7 0x2CEE 376 #define REG_AUDIO_DC_OFFSET 0x2CFA 377 378 #define REG_AUDIO_I2S_TRX_TIMING_GEN 0x2FA8 379 380 /* SPDIF REGISTER */ 381 #define REG_SPDIF_NPCM_SYNTH_NF_H 0x2BB8 382 #define REG_SPDIF_NPCM_SYNTH_NF_L 0x2BBA 383 #define REG_SPDIFTX_CHANNEL_STATUS_TOGGLE 0x2FFC 384 385 //--------------------------------------------------------------------------- 386 // AUDIO 0x163C BANK Register 387 // AUDIO DFS Register 388 //------------------------------------------------------------------------- 389 #define REG_DSP_DFS_REG 0x163C60 390 #define REG_R2_DFS_REG 0x163C62 391 392 //--------------------------------------------------------------------------- 393 // AUDIO 0x163B BANK Register 394 // AUDIO HDMI Status Register 395 //------------------------------------------------------------------------- 396 #define REG_HDMI_STATUS_REG0 0x163B00 397 #define REG_HDMI_STATUS_REG1 0x163B02 398 #define REG_HDMI_STATUS_REG2 0x163B04 399 #define REG_HDMI_STATUS_REG3 0x163B06 400 #define REG_HDMI_STATUS_REG4 0x163B08 401 #define REG_HDMI_STATUS_REG5 0x163B0A 402 #define REG_HDMI_STATUS_REG6 0x163B0C 403 #define REG_HDMI_STATUS_REG7 0x163B0E 404 #define REG_HDMI_STATUS_REG8 0x163B10 405 #define REG_HDMI_STATUS_REG9 0x163B12 406 #define REG_HDMI_STATUS_REG10 0x163B14 407 #define REG_HDMI_STATUS_REG11 0x163B16 408 #define REG_HDMI_STATUS_REG12 0x163B18 //[5:4] 00:valid status, 01:user status, 10: channel status 409 410 //--------------------------------------------------------------------------- 411 // AUDIO Sound Effect Register 412 //--------------------------------------------------------------------------- 413 #define REG_SOUND_MAIN_PERSCALE M2S_MBOX_PRESCALE 414 415 #define REG_SOUND_AUOUT0_VOLUME M2S_MBOX_AUOUT0_VOL+1 416 #define REG_SOUND_AUOUT1_VOLUME M2S_MBOX_AUOUT1_VOL+1 417 #define REG_SOUND_AUOUT2_VOLUME M2S_MBOX_AUOUT2_VOL+1 418 #define REG_SOUND_AUOUT3_VOLUME M2S_MBOX_AUOUT3_VOL+1 419 #define REG_SOUND_I2S_VOLUME M2S_MBOX_I2S_VOL+1 420 #define REG_SOUND_SPDIF_VOLUME M2S_MBOX_SPDIF_VOL+1 421 #define REG_SOUND_HDMI_TX_VOLUME M2S_MBOX_HDMI_VOL+1 422 #define REG_SOUND_AUOUT0_VOL_FRAC M2S_MBOX_AUOUT0_VOL 423 #define REG_SOUND_AUOUT1_VOL_FRAC M2S_MBOX_AUOUT1_VOL 424 #define REG_SOUND_AUOUT2_VOL_FRAC M2S_MBOX_AUOUT2_VOL 425 #define REG_SOUND_AUOUT3_VOL_FRAC M2S_MBOX_AUOUT3_VOL 426 #define REG_SOUND_I2S_VOL_FRAC M2S_MBOX_I2S_VOL 427 #define REG_SOUND_SPDIF_VOL_FRAC M2S_MBOX_SPDIF_VOL 428 #define REG_SOUND_HDMI_TX_VOL_FRAC M2S_MBOX_HDMI_VOL 429 430 #define REG_SOUND_AD_VOLUME M2S_MBOX_AD_CONTROL 431 #define REG_SOUND_AD_VOLUME_HI M2S_MBOX_AD_CONTROL+1 432 433 434 #define REG_SOUND_EQ_BASE M2S_MBOX_BASS_CTRL+1 435 #define REG_SOUND_EQ1 M2S_MBOX_EQ1_GAIN+1 436 #define REG_SOUND_EQ2 M2S_MBOX_EQ2_GAIN+1 437 #define REG_SOUND_EQ3 M2S_MBOX_EQ3_GAIN+1 438 #define REG_SOUND_EQ4 M2S_MBOX_EQ4_GAIN+1 439 #define REG_SOUND_EQ5 M2S_MBOX_EQ5_GAIN+1 440 441 #define REG_SOUND_BASS M2S_MBOX_BASS_CTRL 442 #define REG_SOUND_TREBLE M2S_MBOX_TREBLE_CTRL 443 #define REG_SOUND_BALANCEL M2S_MBOX_BAL_CTRL+1 444 #define REG_SOUND_BALANCER M2S_MBOX_BAL_CTRL 445 446 #define REG_SOUND_AVC_AT M2S_MBOX_AVC_CTRL+1 447 #define REG_SOUND_AVC_RT M2S_MBOX_AVC_CTRL+1 448 #define REG_SOUND_AVC_MODE M2S_MBOX_AVC_CTRL+1 449 #define REG_SOUND_AVC_THRESHOLD M2S_MBOX_AVC_CTRL 450 #define REG_SOUND_DRC_THRESHOLD M2S_MBOX_DRC_CTRL 451 #define REG_SOUND_NR_THRESHOLD M2S_MBOX_NR_CTRL 452 453 #define REG_SOUND_MAIN_SNDEFFECT M2S_MBOX_SNDEFF_EN 454 455 #define REG_SOUND_MAIN_COUNTER S2M_MBOX_WHILE1_CNTR 456 #define REG_SOUND_TIMER_COUNTER S2M_MBOX_TIMER_CNTR+1 457 #define REG_SOUND_ISR_COUNTER S2M_MBOX_ISR_CNTR+1 458 459 #define REG_SOUND_UPLOAD_COUNTER S2M_MBOX_PCM_UPLOAD_CNT 460 461 #define REG_SOUND_CH5_MIX_VOL_INT M2S_MBOX_KTV5_VOL+1 462 #define REG_SOUND_CH5_MIX_VOL_FRC M2S_MBOX_KTV5_VOL 463 #define REG_SOUND_CH6_MIX_VOL_INT M2S_MBOX_KTV6_VOL+1 464 #define REG_SOUND_CH6_MIX_VOL_FRC M2S_MBOX_KTV6_VOL 465 #define REG_SOUND_CH8_MIX_VOL_INT M2S_MBOX_KTV8_VOL+1 466 #define REG_SOUND_CH8_MIX_VOL_FRC M2S_MBOX_KTV8_VOL 467 468 //--------------------------------------------------------------------------- 469 // AUDIO COMMON MAIL BOX REGISTER 470 //--------------------------------------------------------------------------- 471 #define REG_M2D_MAILBOX_0_L 0x2D20 472 #define REG_M2D_MAILBOX_0_H 0x2D21 473 474 #define REG_M2D_MAILBOX_1_L 0x2D22 475 #define REG_M2D_MAILBOX_1_H 0x2D23 476 477 #define REG_M2D_MAILBOX_5_L 0x2D2A 478 #define REG_M2D_MAILBOX_5_H 0x2D2B 479 480 #define REG_M2D_MAILBOX_7_L 0x2D2E 481 #define REG_M2D_MAILBOX_7_H 0x2D2F 482 483 #define REG_DEC2_DECODE_CMD 0x2D2C 484 485 #define REG_DBG_DATA_L 0x2D2E 486 487 #define REG_DEBUG_REG_3_H 0x2D37 488 #define REG_DEBUG_REG_4_L 0x2D38 489 #define REG_DEBUG_REG_4_H 0x2D39 490 #define REG_DEBUG_REG_5_L 0x2D3A 491 #define REG_DEBUG_REG_5_H 0x2D3B 492 #define REG_DBG_CMD 0x2D3D 493 494 #define REG_MB_MODE_SELECT M2S_MBOX_SOUND_MODE_SEL 495 #define REG_MB_POWER_DOWN M2S_MBOX_POWER_DOWN 496 #define REG_MB_TIME_STAMP_SEC D2M_MBOX_MM_PTS_IN_SEC 497 #define REG_MB_TIME_STAMP_4ms D2M_MBOX_MM_PTS_IN_MSEC 498 499 #define REG_D2M_MAILBOX_SE_POWERCTRL M2S_MBOX_POWER_DOWN+1 500 501 #define REG_MB_PCMUPLOAD_CMD M2S_MBOX_BT_CTRL 502 #define REG_MB_PCMUPLOAD_ADDR 0x2D4E 503 504 #define REG_D2M_MAILBOX_3_L 0x2D46 505 #define REG_D2M_MAILBOX_3_H 0x2D47 506 507 #define REG_D2M_MAILBOX_4_L 0x2D48 508 #define REG_D2M_MAILBOX_4_H 0x2D49 509 510 #define REG_D2M_MAILBOX_6_L 0x2D4C 511 #define REG_D2M_MAILBOX_6_H 0x2D4D 512 513 #define REG_D2M_MAILBOX_7_L 0x2D4E 514 #define REG_D2M_MAILBOX_7_H 0x2D4F 515 516 #define REG_D2M_MAILBOX_8_L 0x2D50 517 #define REG_D2M_MAILBOX_8_H 0x2D51 518 519 #define REG_D2M_MAILBOX_9_L 0x2D52 520 #define REG_D2M_MAILBOX_9_H 0x2D53 521 522 #define REG_D2M_MAILBOX_A_L 0x2D54 523 #define REG_D2M_MAILBOX_A_H 0x2D55 524 525 #define REG_D2M_MAILBOX_B_L 0x2D56 526 #define REG_D2M_MAILBOX_B_H 0x2D57 527 528 #define REG_D2M_MAILBOX_C_L 0x2D58 529 #define REG_D2M_MAILBOX_C_H 0x2D59 530 531 #define REG_D2M_MAILBOX_D_L 0x2D5A 532 #define REG_D2M_MAILBOX_D_H 0x2D5B 533 #define REG_DBG_DATA_HI 0x2D5C 534 #define REG_DBG_DATA_LO 0x2D5E 535 536 //--------------------------------------------------------------------------- 537 // AUDIO MM MAIL BOX REGISTER 538 //--------------------------------------------------------------------------- 539 #define REG_DEC1_DDR_ES_BUF_SIZE D2M_MBOX_ES_MEMCNT 540 #define REG_DEC1_DDR_PCM_BUF_SIZE D2M_MBOX_PCM_MEMCNT 541 #define REG_DEC1_TIME_STAMP_SEC D2M_MBOX_MM_PTS_IN_SEC 542 #define REG_DEC1_TIME_STAMP_MS D2M_MBOX_MM_PTS_IN_MSEC 543 #define REG_DEC1_TS_PTS_H D2M_MBOX_MM_PTS_HI 544 #define REG_DEC1_LINE_BUF_ADDR D2M_MBOX_MM_FILE_REQ_ADDR 545 #define REG_DEC1_TS_PTS_M D2M_MBOX_MM_PTS_ME 546 #define REG_DEC1_LINE_BUF_SIZE D2M_MBOX_MM_FILE_REQ_SIZE 547 #define REG_DEC1_TS_PTS_L D2M_MBOX_MM_PTS_LO 548 #define REG_DEC1_RESIDUAL_PCM D2M_MBOX_MM_FILE_PLAY_END 549 550 #define REG_AUDIO_IRQ_CONTROL1 0x2D62 551 #define REG_AUDIO_IRQ_CONTROL1_2 0x2D63 552 #define REG_AUDIO_IRQ_CONTROL2 0x2D64 553 #define REG_AUDIO_DEMODULATOR_CTRL 0x2D66 554 #define REG_AUDIO_FIFO_STATUS 0x2D68 555 556 //--------------------------------------------------------------------------- 557 // AUDIO DEC_DSP MAIL BOX REGISTER 558 //--------------------------------------------------------------------------- 559 #define REG_MAD_MAIN_COUNTER D2M_MBOX_TIMER_CNTR + 1 560 #define REG_MAD_TIMER_COUNTER D2M_MBOX_TIMER_CNTR 561 562 #define REG_DEC_M2D_MAIL_BOX_BASE 0x2D80 563 #define REG_DEC_D2M_MAIL_BOX_BASE 0x2DA0 564 #define REG_DEC_D2M_MAIL_BOX_ENC_LINEADDR D2M_MBOX_ENC_LINEADDR 565 #define REG_DEC_D2M_MAIL_BOX_ENC_LINESIZE D2M_MBOX_ENC_LINESIZE 566 #define REG_DEC_M2D_MAIL_BOX_ENC_CONTROL M2D_MBOX_ENC_CONTROL 567 568 #define REG_DEC1_UNI_PCM_OUTCNT M2D_MBOX_UNI_PCMOUT_CNT 569 #define REG_DEC1_UNI_PCM3_WPTR M2D_MBOX_UNI_PCM3_WRPTR 570 #define REG_DEC1_UNI_NEED_DEC_FRMNUM M2D_MBOX_UNI_NEED_DECODE_FRMCNT 571 #define REG_DEC1_UNI_ES_WPTR M2D_MBOX_UNI_INPUT_ES_WPTR 572 #define REG_DEC1_UNI_ES_MEMCNT D2M_MBOX_ES_MEMCNT 573 #define REG_DEC1_UNI_PCM_WPTR D2M_MBOX_UNI_PCM_WPTR 574 #define REG_DEC1_UNI_PCM_OUTSIZE D2M_MBOX_UNI_PCM_SIZE 575 #define REG_DEC1_UNI_PCM3_LEVEL D2M_MBOX_UNI_PCM_BUFFEBT 576 #define REG_DEC1_UNI_DECODE_TAG D2M_MBOX_UNI_FRAME_CNT 577 578 #define REG_DEC1_OMX_SPDIF_PARAM DSP1DmAddr_dec1_omx_param 579 #define REG_DEC1_OMX_PCM_DIFF DSP1DmAddr_dec1_omx_param+1 580 581 #define REG_DEC2_UNI_PCM_OUTCNT M2S_MBOX_UNI_PCMOUT_CNT 582 #define REG_DEC2_UNI_PCM3_WPTR M2S_MBOX_UNI_PCM3_WRPTR 583 #define REG_DEC2_UNI_NEED_DEC_FRMNUM M2S_MBOX_UNI_NEED_DECODE_FRMCNT 584 #define REG_DEC2_UNI_ES_WPTR M2S_MBOX_UNI_INPUT_ES_WPTR 585 #define REG_DEC2_UNI_ES_MEMCNT S2M_MBOX_ES_MEMCNT 586 #define REG_DEC2_UNI_PCM_WPTR S2M_MBOX_UNI_PCM_WPTR 587 #define REG_DEC2_UNI_PCM_OUTSIZE S2M_MBOX_UNI_PCM_SIZE 588 #define REG_DEC2_UNI_PCM3_LEVEL S2M_MBOX_UNI_PCM_BUFFEBT 589 #define REG_DEC2_UNI_DECODE_TAG S2M_MBOX_UNI_FRAME_CNT 590 591 #define REG_DEC2_OMX_SPDIF_PARAM DSP2DmAddr_dec1_omx_param 592 #define REG_DEC2_OMX_PCM_DIFF DSP2DmAddr_dec1_omx_param+1 593 594 #define REG_MB_DEC_CTRL M2D_MBOX_DEC_CTRL 595 #define REG_MB_DEC_PIO_ID M2D_MBOX_PIO_ID 596 #define REG_MB_DEC1_MM_INT_TAG M2D_MBOX_MM_FILEIN_TAG 597 #define REG_MB_DEC_CMD1 M2D_MBOX_DBG_CMD1 598 #define REG_MB_DEC_CMD2 M2D_MBOX_DBG_CMD2 599 #define REG_MB_DEC_ID_STATUS D2M_MBOX_DEC_DECSTATUS 600 #define REG_MB_ENC_ID_STATUS 0x2DBA 601 #define REG_MB_DE_ACK1 D2M_MBOX_DBG_RESULT1 + 1 602 #define REG_MB_DE_ACK2 D2M_MBOX_DBG_RESULT2 603 604 #define REG_AUDIO_STATUS_HDMI_LOCK D2M_MBOX_HDMI_NPCM_LOCK 605 606 // DDP 607 #define REG_MB_AC3P_SMPRATE D2M_MBOX_SAMPLERATE 608 #define REG_MB_AC3P_LOW_HIGH_CUT M2D_MBOX_LOW_HIGH_CUT 609 610 // DTS 611 #define REG_MB_DTS_SMPRATE D2M_MBOX_SAMPLERATE 612 #define REG_MB_DEC1_DTS_CH_CTRL 0x2D96 613 #define REG_SPDIF_DTS_NONPCM_LEV 0x2DB6 614 615 // MS10 616 #define REG_MB_MS10_DDT_DUAL_CTRL 0x2D80 617 #define REG_MB_MS10_DDT_ENC_CTRL 0x2D92 618 619 #define REG_MB_DOLBY_LOUDNESS_INFO M2S_MBOX_DOLBY_LOUDNESS_INFO 620 621 /* MCU to DSP */ 622 #define REG_M2D_MAILBOX_PIO_ID M2D_MBOX_PIO_ID+1 623 #define REG_M2D_MAILBOX_SPDIF_CTRL M2S_MBOX_SPDIF_SETTING 624 #define REG_M2D_MAILBOX_DEC_DBGCMD M2D_MBOX_DBG_CMD1+1 625 #define REG_M2D_MAILBOX_DEC_DBGPARAM1 M2D_MBOX_DBG_CMD1 626 #define REG_M2D_MAILBOX_DEC_DBGPARAM2 M2D_MBOX_DBG_CMD2+1 627 #define REG_M2D_MAILBOX_DEC_DBGPARAM3 M2D_MBOX_DBG_CMD2 628 629 /* DSP to MCU */ 630 #define REG_D2M_MAILBOX_DEC_ISRCMD D2M_MBOX_INTR_CMDTYPE 631 #define REG_DEC1_INT_ID D2M_MBOX_INTR_CMDTYPE 632 633 //--------------------------------------------------------------------------- 634 // AUDIO MPEG ENCODER in DEC_DSP MAIL BOX REGISTER 635 //--------------------------------------------------------------------------- 636 #define REG_MB_MPEG_INFO 0x2DAA 637 #define REG_MB_MPEG_INFO_L 0x2DAA 638 #define REG_MB_MPEG_INFO_H 0x2DAB 639 #define REG_MPEG_VERSION DSP1DmAddr_mpegVer 640 #define REG_MPEG_FRAMENUM DSP1DmAddr_mpg_frmNum 641 642 //--------------------------------------------------------------------------- 643 // AUDIO SND_DSP MAIL BOX REGISTER 644 //--------------------------------------------------------------------------- 645 #define REG_MB_SE_PIO_ID M2S_MBOX_MM_FILEIN_TAG 646 #define REG_MB_DEC2_MM_INT_TAG M2S_MBOX_MM_FILEIN_TAG 647 #define REG_MB_DEC3_CTRL M2S_MBOX_AD_CONTROL 648 #define REG_MB_SE_CMD1 M2S_MBOX_DBG_CMD1 649 #define REG_MB_SE_CMD2 M2S_MBOX_DBG_CMD2 650 #define REG_MB_DEC2_ID_STATUS S2M_MBOX_DEC_STATUS+1 651 #define REG_MB_SE_ACK1 S2M_MBOX_DBG_RESULT1 652 #define REG_MB_SE_ACK2 S2M_MBOX_DBG_RESULT2 653 654 #define REG_AUD_MADBASE_SEL 0x2DE0 655 #define REG_AUD_DIS_DMA 0x2DE0 656 #define REG_AUD_RST_MAD 0x2DE0 657 658 #define REG_MCUDSP_CNT_CFG 0x2DE2 659 #define REG_MAD_BUF_BASE 0x2DE3 660 661 #define REG_MAD_OFFSET_BASE_L 0x2DE4 662 #define REG_MAD_OFFSET_BASE_H 0x2DE5 663 664 #define REG_MBASE_L 0x2DE6 665 #define REG_MBASE_H 0x2DE7 666 #define REG_MSIZE_L 0x2DE8 667 #define REG_MSIZE_H 0x2DE9 668 669 #define REG_MEM_CFG 0x2DEA 670 671 #define REG_SE_M2D_MAIL_BOX_BASE 0x2DC0 672 #define REG_SE_D2M_MAIL_BOX_BASE 0x2DE0 673 674 #define REG_D2M_MAILBOX_SE_ISRCMD S2M_MBOX_INTR_CMDTYPE+1 675 676 //--------------------------------------------------------------------------- 677 // Audio SND-DSP XBOX REGISTER 678 //--------------------------------------------------------------------------- 679 #define REG_DSP_XBOX_ADDRESS 0x2E30 680 #define REG_DSP_XBOX_WR_DATA_H 0x2E32 681 #define REG_DSP_XBOX_WR_DATA_L 0x2E34 682 #define REG_DSP_XBOX_MISC 0x2E36 683 #define REG_DSP_XBOX_RD_DATA_H 0x2E38 684 #define REG_DSP_XBOX_RD_DATA_L 0x2E3A 685 686 //--------------------------------------------------------------------------- 687 // AUDIO MAD DECODER1 PM Address 688 //--------------------------------------------------------------------------- 689 // Decoder REG DM address 690 #define REG_DEC1_INFO_BASE DSP1DmAddr_dec1_info 691 #define REG_DEC1_PARAM_BASE DSP1DmAddr_dec1_param 692 693 // Decoder REG PM address 694 #define REG_AUDIO_IPAUTH 0 695 #define REG_AUDIO_PTS_H DSP1PmAddr_audio_PTS_H 696 #define REG_AUDIO_PTS_L DSP1PmAddr_audio_PTS_L 697 #define REG_PtsStcDelta_H DSP1PmAddr_audio_Td_H 698 #define REG_PtsStcDelta_L DSP1PmAddr_audio_Td_L 699 #define REG_DEC_SampleRate DSP1PmAddr_smpRate 700 #define REG_DEC_SoundMode DSP1PmAddr_soundMode 701 #define REG_MHEG5_SIZE DSP1PmAddr_reqMHEG5_size 702 #define REG_ErrorCount DSP1PmAddr_decErrorCnt 703 #define REG_AC3_AVdelay DSP1PmAddr_ac3_avDelay 704 #define REG_AAC_AVdelay DSP1PmAddr_aac_avDelay 705 #define REG_MPG_AVdelay DSP1PmAddr_mpg_avDelay 706 707 //--------------------------------------------------------------------------- 708 // AUDIO MAD DECODER2 PM Address 709 //--------------------------------------------------------------------------- 710 // Decoder2 REG DM address 711 #define REG_DEC2_INFO_BASE DSP2DmAddr_dec1_info 712 #define REG_DEC2_PARAM_BASE DSP2DmAddr_dec1_param 713 714 // Decoder2 REG PM address for T3 (to do, move to ADEC) 715 #define REG_DEC2_AUDIO_IPAUTH DSP2XboxAddr_ipSecurity 716 #define REG_DEC2_AUDIO_PTS_H DSP2PmAddr_audio_PTS_H 717 #define REG_DEC2_AUDIO_PTS_L DSP2PmAddr_audio_PTS_L 718 #define REG_DEC2_PtsStcDelta_H DSP2PmAddr_audio_Td_H 719 #define REG_DEC2_PtsStcDelta_L DSP2PmAddr_audio_Td_L 720 #define REG_DEC2_SampleRate DSP2PmAddr_smpRate 721 #define REG_DEC2_SoundMode DSP2PmAddr_soundMode 722 #define REG_DEC2_MHEG5_SIZE DSP2PmAddr_reqMHEG5_size 723 #define REG_DEC2_ErrorCount DSP2PmAddr_decErrorCnt 724 725 //--------------------------------------------------------------------------- 726 // AUDIO MAD DECODER2 DM Address 727 //--------------------------------------------------------------------------- 728 #define REG_DEC2_DDR_ES_BUF_SIZE S2M_MBOX_ES_MEMCNT 729 #define REG_DEC2_DDR_PCM_BUF_SIZE S2M_MBOX_PCM_MEMCNT 730 #define REG_DEC2_TIME_STAMP_SEC S2M_MBOX_MM_PTS_IN_SEC 731 #define REG_DEC2_TIME_STAMP_MS S2M_MBOX_MM_PTS_IN_MSEC 732 #define REG_DEC2_TS_PTS_H S2M_MBOX_MM_PTS_HI 733 #define REG_DEC2_LINE_BUF_ADDR S2M_MBOX_MM_FILE_REQ_ADDR 734 #define REG_DEC2_TS_PTS_M S2M_MBOX_MM_PTS_ME 735 #define REG_DEC2_LINE_BUF_SIZE S2M_MBOX_MM_FILE_REQ_SIZE 736 #define REG_DEC2_TS_PTS_L S2M_MBOX_MM_PTS_LO 737 #define REG_DEC2_RESIDUAL_PCM S2M_MBOX_MM_FILE_PLAY_END 738 739 #define REG_ALSA_MODE DSP2DmAddr_IO_Info2+IO_INFO2_ALSA_MODE 740 741 //--------------------------------------------------------------------------- 742 // DEC-R2/SND_R2 register base 743 //--------------------------------------------------------------------------- 744 #define REG_SDR_SWITCH_CTRL 0x163C44 // [0]: 0x1129 SDR BASE, 0, SDR1; 1, SDR2 745 // [1]: 0x1630 SDR BASE, 0, SDR1; 1, SDR2 746 // R2_0 base 747 #define REG_R2_0_CTRL_BASE 0x112900 748 #define REG_R2_0_MAILBOX_BASE 0x112E00 749 #define REG_R2_0_CTRL_BANK_SW_BIT_MASK 0x01 750 751 // R2_1 base 752 #define REG_R2_1_CTRL_BASE 0x163000 753 #define REG_R2_1_MAILBOX_BASE 0x160300 754 #define REG_R2_1_CTRL_BANK_SW_BIT_MASK 0x02 755 756 // DEC-R2 base 757 #define REG_DECR2_DDR_BASE (HAL_AUDIO_GetDspMadBaseAddr(2)) // DEC-R2 DDR base 758 #define REG_DECR2_CTRL_BASE (REG_R2_0_CTRL_BASE) 759 #define REG_DECR2_MAILBOX_BASE (REG_R2_0_MAILBOX_BASE) 760 #define REG_DECR2_CTRL_BANK_SW_BIT_MASK (REG_R2_0_CTRL_BANK_SW_BIT_MASK) 761 762 // SND_R2 base 763 #define REG_SNDR2_DDR_BASE (HAL_AUDIO_GetDspMadBaseAddr(2)+ADEC__R2_DDR_SIZE) //SND_R2 base 764 #define REG_SNDR2_CTRL_BASE (REG_R2_1_CTRL_BASE) 765 #define REG_SNDR2_MAILBOX_BASE (REG_R2_1_MAILBOX_BASE) 766 #define REG_SNDR2_CTRL_BANK_SW_BIT_MASK (REG_R2_1_CTRL_BANK_SW_BIT_MASK) 767 768 //--------------------------------------------------------------------------- 769 // Audio DEC-R2 REGISTER SETTING 770 //--------------------------------------------------------------------------- 771 // DEC_R2 control Bank 772 #define REG_DECR2_CTRL (REG_DECR2_CTRL_BASE + 0x80) 773 774 //SDR1 775 #define REG_DECR2_ICMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x82) 776 #define REG_DECR2_ICMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x84) 777 778 //SDR2 779 #define REG_DECR2_ICMEM2_BASE_LO (REG_DECR2_CTRL_BASE + 0x8C) 780 #define REG_DECR2_ICMEM2_BASE_HI (REG_DECR2_CTRL_BASE + 0x8E) 781 782 #define REG_DECR2_DCMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x86) 783 #define REG_DECR2_DCMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x88) 784 785 #define REG_DECR2_DQMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x9A) 786 #define REG_DECR2_DQMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x9C) 787 #define REG_DECR2_DQMEM_SIZE_MASK_LO (REG_DECR2_CTRL_BASE + 0x9E) 788 #define REG_DECR2_DQMEM_SIZE_MASK_HI (REG_DECR2_CTRL_BASE + 0xA0) 789 790 #define REG_DECR2_IO0_MAPPING_BASE_HI (REG_DECR2_CTRL_BASE + 0xA8) 791 #define REG_DECR2_IO1_MAPPING_BASE_HI (REG_DECR2_CTRL_BASE + 0xAA) 792 #define REG_DECR2_IO2_MAPPING_BASE_HI (REG_DECR2_CTRL_BASE + 0xAC) 793 #define REG_DECR2_IO3_MAPPING_BASE_HI (REG_DECR2_CTRL_BASE + 0xAE) 794 #define REG_DECR2_MEM_CTRL (REG_DECR2_CTRL_BASE + 0xB0) 795 #define REG_DECR2_RESET_CTRL (REG_DECR2_CTRL_BASE + 0x80) 796 #define REG_DECR2_SWITCH_CTRL (REG_DECR2_CTRL_BASE + 0xD6) 797 798 // DEC_R2 mailbox Bank 799 #define REG_DECR2_PARAM_TYPE (REG_DECR2_MAILBOX_BASE + 0x80) 800 #define REG_DECR2_ID_SELECT (REG_DECR2_MAILBOX_BASE + 0x82) 801 #define REG_DECR2_PARAM_VAL1 (REG_DECR2_MAILBOX_BASE + 0x84) 802 #define REG_DECR2_PARAM_VAL2 (REG_DECR2_MAILBOX_BASE + 0x86) 803 #define REG_DECR2_CMD_TOKEN (REG_DECR2_MAILBOX_BASE + 0xA3) 804 #define REG_DECR2_INFO1 (REG_DECR2_MAILBOX_BASE + 0xA4) 805 #define REG_DECR2_INFO2 (REG_DECR2_MAILBOX_BASE + 0xA6) 806 807 #define REG_DECR2_SYSTEM_START (REG_DECR2_MAILBOX_BASE + 0x9C) 808 #define REG_DECR2_ACK1 (REG_DECR2_MAILBOX_BASE + 0xAE) 809 #define REG_DECR2_BOOTCODE_DONE_ACK (REG_DECR2_MAILBOX_BASE + 0xB0) 810 #define REG_DECR2_DSPRELOAD_DONE_ACK (REG_DECR2_MAILBOX_BASE + 0xB0) 811 #define REG_DECR2_MAIN_COUNTER (REG_DECR2_MAILBOX_BASE + 0xB2) 812 #define REG_DECR2_TIMER_COUNTER (REG_DECR2_MAILBOX_BASE + 0xB3) 813 #define REG_DECR2_VERSION (REG_DECR2_MAILBOX_BASE + 0xAA) 814 815 #define REG_R2_ASNDDSP_TYPE (REG_DECR2_MAILBOX_BASE + 0x94) 816 #define REG_R2_HDMI_NONPCM_PATH (REG_DECR2_MAILBOX_BASE + 0x96) 817 #define REG_R2_DECODE1_TYPE (REG_DECR2_MAILBOX_BASE + 0x98) 818 #define REG_R2_DECODE2_TYPE (REG_DECR2_MAILBOX_BASE + 0x9A) 819 #define REG_R2_DECODE3_TYPE (REG_DECR2_MAILBOX_BASE + 0x9C) 820 #define REG_R2_DECODE1_CMD (REG_DECR2_MAILBOX_BASE + 0x98 + 0x1) 821 #define REG_R2_DECODE2_CMD (REG_DECR2_MAILBOX_BASE + 0x9A + 0x1) 822 #define REG_R2_DECODE3_CMD (REG_DECR2_MAILBOX_BASE + 0x9C + 0x1) 823 824 //--------------------------------------------------------------------------- 825 // Audio SND-R2 REGISTER SETTING 826 //--------------------------------------------------------------------------- 827 // SND_R2 control Bank 828 #define REG_SNDR2_CTRL (REG_SNDR2_CTRL_BASE + 0x80) 829 830 //SDR1 831 #define REG_SNDR2_ICMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x82) 832 #define REG_SNDR2_ICMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x84) 833 834 //SDR2 835 #define REG_SNDR2_ICMEM2_BASE_LO (REG_SNDR2_CTRL_BASE + 0x8C) 836 #define REG_SNDR2_ICMEM2_BASE_HI (REG_SNDR2_CTRL_BASE + 0x8E) 837 838 #define REG_SNDR2_DCMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x86) 839 #define REG_SNDR2_DCMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x88) 840 841 #define REG_SNDR2_DQMEM_BASE_LO (REG_SNDR2_CTRL_BASE + 0x9A) 842 #define REG_SNDR2_DQMEM_BASE_HI (REG_SNDR2_CTRL_BASE + 0x9C) 843 #define REG_SNDR2_DQMEM_SIZE_MASK_LO (REG_SNDR2_CTRL_BASE + 0x9E) 844 #define REG_SNDR2_DQMEM_SIZE_MASK_HI (REG_SNDR2_CTRL_BASE + 0xA0) 845 846 #define REG_SNDR2_IO0_MAPPING_BASE_HI (REG_SNDR2_CTRL_BASE + 0xA8) 847 #define REG_SNDR2_IO1_MAPPING_BASE_HI (REG_SNDR2_CTRL_BASE + 0xAA) 848 #define REG_SNDR2_IO2_MAPPING_BASE_HI (REG_SNDR2_CTRL_BASE + 0xAC) 849 #define REG_SNDR2_IO3_MAPPING_BASE_HI (REG_SNDR2_CTRL_BASE + 0xAE) 850 #define REG_SNDR2_MEM_CTRL (REG_SNDR2_CTRL_BASE + 0xB0) 851 #define REG_SNDR2_RESET_CTRL (REG_SNDR2_CTRL_BASE + 0x80) 852 #define REG_SNDR2_SWITCH_CTRL (REG_SNDR2_CTRL_BASE + 0xD6) 853 854 // SND_R2 mailbox Bank 855 #define REG_SNDR2_PARAM_TYPE (REG_SNDR2_MAILBOX_BASE + 0x80) 856 #define REG_SNDR2_ID_SELECT (REG_SNDR2_MAILBOX_BASE + 0x82) 857 #define REG_SNDR2_PARAM_VAL1 (REG_SNDR2_MAILBOX_BASE + 0x84) 858 #define REG_SNDR2_PARAM_VAL2 (REG_SNDR2_MAILBOX_BASE + 0x86) 859 #define REG_SNDR2_CMD_TOKEN (REG_SNDR2_MAILBOX_BASE + 0xA3) 860 #define REG_SNDR2_INFO1 (REG_SNDR2_MAILBOX_BASE + 0xA4) 861 #define REG_SNDR2_INFO2 (REG_SNDR2_MAILBOX_BASE + 0xA6) 862 863 #define REG_SNDR2_SYSTEM_START (REG_SNDR2_MAILBOX_BASE + 0x9C) 864 #define REG_SNDR2_ADVSND_SEL (REG_SNDR2_MAILBOX_BASE + 0x8E) 865 #define REG_SNDR2_MBOX_BYTE_SRS_SEL (REG_SNDR2_MAILBOX_BASE + 0x94) 866 #define REG_SNDR2_MBOX_BYTE_DAP_SEL (REG_SNDR2_MAILBOX_BASE + 0x88) //TODO: need a mechanism to auto-synchronized ifnormtion b/w R2/Driver 867 #define REG_SNDR2_ACK1 (REG_SNDR2_MAILBOX_BASE + 0xAE) 868 #define REG_SNDR2_BOOTCODE_DONE_ACK (REG_SNDR2_MAILBOX_BASE + 0xB0) 869 #define REG_SNDR2_MAIN_COUNTER (REG_SNDR2_MAILBOX_BASE + 0xB2) 870 #define REG_SNDR2_TIMER_COUNTER (REG_SNDR2_MAILBOX_BASE + 0xB3) 871 #define REG_SNDR2_VERSION (REG_SNDR2_MAILBOX_BASE + 0xAA) 872 873 //--------------------------------------------------------------------------- 874 // Audio R2-DMA REGISTER SETTING 875 //--------------------------------------------------------------------------- 876 #define R2_DMARDR1_REG_BASE 0x160300 877 #define R2_DMARDR1_REG_SYNTH_H 0x112BA8 878 #define R2_DMARDR1_REG_SYNTH_L 0x112BAA 879 #define R2_DMARDR1_EN 0x1603C0 880 #define R2_DMARDR1_DPGA_REG_L_CTRL 0x1603C6 881 #define R2_DMARDR1_DPGA_REG_R_CTRL 0x1603CC 882 883 #define R2_DMARDR_REG_SYNTH_UPDATE 0x112BCE 884 #define R2_DMARDR2_REG_BASE 0x160320 885 #define R2_DMARDR2_REG_SYNTH_H 0x112BB0 886 #define R2_DMARDR2_REG_SYNTH_L 0x112BB2 887 #define R2_DMARDR2_EN 0x1603E0 888 #define R2_DMARDR2_DPGA_REG_L_CTRL 0x1603E6 889 #define R2_DMARDR2_DPGA_REG_R_CTRL 0x1603EC 890 //--------------------------------------------------------------------------- 891 // Audio NewDMAreader REGISTER SETTING 892 //--------------------------------------------------------------------------- 893 #define NewDMAreader_ctrl 0x163E40 894 #define NewDMAreader_BaseAddress_Lo 0x163E42 895 #define NewDMAreader_BaseAddress_Hi 0x163E44 896 #define NewDMAreader_DRAM_size 0x163E46 897 #define NewDMAreader_CPU_triggersize 0x163E48 898 #define NewDMAreader_DRAM_underrun_threshold 0x163E4A 899 #define NewDMAreader_Enable_ctrl 0x163E4C 900 #define NewDMAreader_Syth 0x163E4E 901 #define NewDMAreader_DRAM_levelcnt 0x163E54 902 #define NewDMAreader_DRAM_flag 0x163E56 903 904 //--------------------------------------------------------------------------- 905 // Audio NewDMAWriter REGISTER SETTING 906 //--------------------------------------------------------------------------- 907 #define NewDMAwriter_ctrl 0x163E60 908 #define NewDMAwriter_BaseAddress_Lo 0x163E62 909 #define NewDMAwriter_BaseAddress_Hi 0x163E64 910 #define NewDMAwriter_DRAM_size 0x163E66 911 #define NewDMAwriter_CPU_triggersize 0x163E68 912 #define NewDMAwriter_DRAM_underrun_threshold 0x163E6A 913 #define NewDMAwriter_DRAM_levelcnt 0x163E74 914 #endif // _REG_AUDIO_H_ 915