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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regSEAL.h 98 /// @brief SEAL Control Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_SEAL_H_ 103 #define _REG_SEAL_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 #define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) 115 #define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) 116 117 #define SEAL_SECURE0_RANGE0 (0x00023700UL) 118 #define SEAL_SECURE1_RANGE0 (0x00023800UL) 119 #define SEAL_TZPC_NONPM (0x00023900UL) 120 #define SEAL_TZPC_PM (0x00003900UL) 121 122 #define RANGE_ADDR_OFFSET (0x10UL) 123 124 //Secure range0 125 #define REG_SECURE0_RANGE0_START_ADDR (SEAL_SECURE0_RANGE0+0x00UL) 126 #define REG_SECURE0_RANGE0_END_ADDR (SEAL_SECURE0_RANGE0+0x08UL) 127 #define REG_SECURE0_RANGE0_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x0EUL) 128 129 #define REG_SECURE0_RANGE1_START_ADDR (SEAL_SECURE0_RANGE0+0x10UL) 130 #define REG_SECURE0_RANGE1_END_ADDR (SEAL_SECURE0_RANGE0+0x18UL) 131 #define REG_SECURE0_RANGE1_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x1EUL) 132 133 #define REG_SECURE0_RANGE2_START_ADDR (SEAL_SECURE0_RANGE0+0x20UL) 134 #define REG_SECURE0_RANGE2_END_ADDR (SEAL_SECURE0_RANGE0+0x28UL) 135 #define REG_SECURE0_RANGE2_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x2EUL) 136 137 #define REG_SECURE0_RANGE3_START_ADDR (SEAL_SECURE0_RANGE0+0x30UL) 138 #define REG_SECURE0_RANGE3_END_ADDR (SEAL_SECURE0_RANGE0+0x38UL) 139 #define REG_SECURE0_RANGE3_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x3EUL) 140 141 #define REG_SECURE0_RANGE4_START_ADDR (SEAL_SECURE0_RANGE0+0x40UL) 142 #define REG_SECURE0_RANGE4_END_ADDR (SEAL_SECURE0_RANGE0+0x48UL) 143 #define REG_SECURE0_RANGE4_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x4EUL) 144 145 #define REG_SECURE0_RANGE5_START_ADDR (SEAL_SECURE0_RANGE0+0x50UL) 146 #define REG_SECURE0_RANGE5_END_ADDR (SEAL_SECURE0_RANGE0+0x58UL) 147 #define REG_SECURE0_RANGE5_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x5EUL) 148 149 #define REG_SECURE0_RANGE6_START_ADDR (SEAL_SECURE0_RANGE0+0x60UL) 150 #define REG_SECURE0_RANGE6_END_ADDR (SEAL_SECURE0_RANGE0+0x68UL) 151 #define REG_SECURE0_RANGE6_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x6EUL) 152 153 #define REG_SECURE0_RANGE7_START_ADDR (SEAL_SECURE0_RANGE0+0x70UL) 154 #define REG_SECURE0_RANGE7_END_ADDR (SEAL_SECURE0_RANGE0+0x78UL) 155 #define REG_SECURE0_RANGE7_ATTRIBUTE (SEAL_SECURE0_RANGE0+0x7EUL) 156 157 /* this register is for PC range protection; currently PC range protection is not used, so we use this register as a dummy register */ 158 #define REG_SECURE0_DUMMY0 (SEAL_SECURE0_RANGE0+0x80UL) 159 160 #define REG_SECURE0_DETECT_ENABLE (SEAL_SECURE0_RANGE0+0xECUL) 161 //Secure range 1 162 #define REG_SECURE1_RANGE0_START_ADDR (SEAL_SECURE1_RANGE0+0x00UL) 163 #define REG_SECURE1_RANGE0_END_ADDR (SEAL_SECURE1_RANGE0+0x08UL) 164 #define REG_SECURE1_RANGE0_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x0EUL) 165 166 #define REG_SECURE1_RANGE1_START_ADDR (SEAL_SECURE1_RANGE0+0x10UL) 167 #define REG_SECURE1_RANGE1_END_ADDR (SEAL_SECURE1_RANGE0+0x18UL) 168 #define REG_SECURE1_RANGE1_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x1EUL) 169 170 #define REG_SECURE1_RANGE2_START_ADDR (SEAL_SECURE1_RANGE0+0x20UL) 171 #define REG_SECURE1_RANGE2_END_ADDR (SEAL_SECURE1_RANGE0+0x28UL) 172 #define REG_SECURE1_RANGE2_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x2EUL) 173 174 #define REG_SECURE1_RANGE3_START_ADDR (SEAL_SECURE1_RANGE0+0x30UL) 175 #define REG_SECURE1_RANGE3_END_ADDR (SEAL_SECURE1_RANGE0+0x38UL) 176 #define REG_SECURE1_RANGE3_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x3EUL) 177 178 #define REG_SECURE1_RANGE4_START_ADDR (SEAL_SECURE1_RANGE0+0x40UL) 179 #define REG_SECURE1_RANGE4_END_ADDR (SEAL_SECURE1_RANGE0+0x48UL) 180 #define REG_SECURE1_RANGE4_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x4EUL) 181 182 #define REG_SECURE1_RANGE5_START_ADDR (SEAL_SECURE1_RANGE0+0x50UL) 183 #define REG_SECURE1_RANGE5_END_ADDR (SEAL_SECURE1_RANGE0+0x58UL) 184 #define REG_SECURE1_RANGE5_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x5EUL) 185 186 #define REG_SECURE1_RANGE6_START_ADDR (SEAL_SECURE1_RANGE0+0x60UL) 187 #define REG_SECURE1_RANGE6_END_ADDR (SEAL_SECURE1_RANGE0+0x68UL) 188 #define REG_SECURE1_RANGE6_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x6EUL) 189 190 #define REG_SECURE1_RANGE7_START_ADDR (SEAL_SECURE1_RANGE0+0x70UL) 191 #define REG_SECURE1_RANGE7_END_ADDR (SEAL_SECURE1_RANGE0+0x78UL) 192 #define REG_SECURE1_RANGE7_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x7EUL) 193 194 /* this register is for PC range protection; currently PC range protection is not used, so we use this register as a dummy register */ 195 #define REG_SECURE1_DUMMY0 (SEAL_SECURE1_RANGE0+0x80UL) 196 197 #define REG_SECURE1_DETECT_ENABLE (SEAL_SECURE1_RANGE0+0xECUL) 198 199 //Secure range hitted log 200 #define REG_SECURE0_HITTED_STATUS (SEAL_SECURE0_RANGE0+0xE0UL) 201 #define REG_SECURE1_HITTED_STATUS (SEAL_SECURE1_RANGE0+0xE0UL) 202 #define REG_SECURE0_HITTED_ADDR (SEAL_SECURE0_RANGE0+0xE2UL) 203 #define REG_SECURE1_HITTED_ADDR (SEAL_SECURE1_RANGE0+0xE2UL) 204 #define REG_SECURE0_HITTED_AUXI_STATUS (SEAL_SECURE0_RANGE0+0xECUL) 205 #define REG_SECURE1_HITTED_AUXI_STATUS (SEAL_SECURE1_RANGE0+0xECUL) 206 #define REG_SECURE_HITTED_LOG_CLR (BIT0) 207 #define REG_SECURE_HITTED_IRQ_MASK (BIT1) 208 #define REG_SECURE_HITTED_FALG (BIT2) 209 #define REG_SECURE_HITTED_IS_WRITE (BIT15) 210 #define REG_SECURE_HITTED_CLIENT_ID 14:8 211 #define REG_SECURE_HITTED_RANGE_ID 6:3 212 #define GET_HIT_RANGE_ID(regval) BITS_RANGE_VAL(regval, REG_SECURE_HITTED_RANGE_ID) 213 #define GET_HIT_CLIENT_ID(regval) BITS_RANGE_VAL(regval, REG_SECURE_HITTED_CLIENT_ID) 214 215 //Secure range lock 216 #define REG_SECURE0_LOCK (SEAL_SECURE0_RANGE0+0xFEUL) 217 #define REG_SECURE1_LOCK (SEAL_SECURE1_RANGE0+0xFEUL) 218 #define REG_SECURE2_LOCK (SEAL_SECURE2_RANGE0+0xFEUL) 219 #define REG_SECURE3_LOCK (SEAL_SECURE3_RANGE0+0xFEUL) 220 #define REG_SECURE4_LOCK (SEAL_SECURE3_RANGE0+0xFEUL) 221 #define REG_SECURE5_LOCK (SEAL_SECURE3_RANGE0+0xFEUL) 222 #define REG_SECURE6_LOCK (SEAL_SECURE3_RANGE0+0xFEUL) 223 #define REG_SECURE7_LOCK (SEAL_SECURE3_RANGE0+0xFEUL) 224 225 //Non secure processor 226 #define REG_TZPC_NONSECURE_PROCESSOR (SEAL_TZPC_NONPM+0x02UL) 227 #define REG_TZPC_NONPM_SECURE_SLAVE (SEAL_TZPC_NONPM+0x20UL) 228 #define REG_TZPC_PM_SECURE_SLAVE (SEAL_TZPC_PM+0x20UL) 229 #define REG_TZPC_NONPM_SECURE_MASTER (SEAL_TZPC_NONPM+0x80UL) 230 #define REG_TZPC_NONSECURE_HEMCU (SEAL_TZPC_NONPM+0x61UL) 231 #define REG_TZPC_PROTECT_CTL (SEAL_TZPC_NONPM+0x60UL) 232 233 //IMI secure range 234 #define REG_IMI_RANGE_START_ADDR (SEAL_TZPC_NONPM+0xE0UL) 235 #define REG_IMI_RANGE_END_ADDR (SEAL_TZPC_NONPM+0xE4UL) 236 237 //Buffer lock 238 #define REG_TZPC_BUFFER_LOCK (SEAL_TZPC_NONPM+0xC8UL) 239 //------------------------------------------------------------------------------------------------- 240 // Type and Structure 241 //------------------------------------------------------------------------------------------------- 242 243 244 #endif // _REG_SEAL_H_ 245 246