1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __INC_HALMAC_REG_8822B_H 3 #define __INC_HALMAC_REG_8822B_H 4 5 #define REG_SYS_ISO_CTRL_8822B 0x0000 6 #define REG_SYS_FUNC_EN_8822B 0x0002 7 #define REG_SYS_PW_CTRL_8822B 0x0004 8 #define REG_SYS_CLK_CTRL_8822B 0x0008 9 #define REG_SYS_EEPROM_CTRL_8822B 0x000A 10 #define REG_EE_VPD_8822B 0x000C 11 #define REG_SYS_SWR_CTRL1_8822B 0x0010 12 #define REG_SYS_SWR_CTRL2_8822B 0x0014 13 #define REG_SYS_SWR_CTRL3_8822B 0x0018 14 #define REG_RSV_CTRL_8822B 0x001C 15 #define REG_RF_CTRL_8822B 0x001F 16 #define REG_AFE_LDO_CTRL_8822B 0x0020 17 #define REG_AFE_CTRL1_8822B 0x0024 18 #define REG_AFE_CTRL2_8822B 0x0028 19 #define REG_AFE_CTRL3_8822B 0x002C 20 #define REG_EFUSE_CTRL_8822B 0x0030 21 #define REG_LDO_EFUSE_CTRL_8822B 0x0034 22 #define REG_PWR_OPTION_CTRL_8822B 0x0038 23 #define REG_CAL_TIMER_8822B 0x003C 24 #define REG_ACLK_MON_8822B 0x003E 25 #define REG_GPIO_MUXCFG_8822B 0x0040 26 #define REG_GPIO_PIN_CTRL_8822B 0x0044 27 #define REG_GPIO_INTM_8822B 0x0048 28 #define REG_LED_CFG_8822B 0x004C 29 #define REG_FSIMR_8822B 0x0050 30 #define REG_FSISR_8822B 0x0054 31 #define REG_HSIMR_8822B 0x0058 32 #define REG_HSISR_8822B 0x005C 33 #define REG_GPIO_EXT_CTRL_8822B 0x0060 34 #define REG_PAD_CTRL1_8822B 0x0064 35 #define REG_WL_BT_PWR_CTRL_8822B 0x0068 36 #define REG_SDM_DEBUG_8822B 0x006C 37 #define REG_SYS_SDIO_CTRL_8822B 0x0070 38 #define REG_HCI_OPT_CTRL_8822B 0x0074 39 #define REG_AFE_CTRL4_8822B 0x0078 40 #define REG_LDO_SWR_CTRL_8822B 0x007C 41 #define REG_MCUFW_CTRL_8822B 0x0080 42 #define REG_MCU_TST_CFG_8822B 0x0084 43 #define REG_HMEBOX_E0_E1_8822B 0x0088 44 #define REG_HMEBOX_E2_E3_8822B 0x008C 45 #define REG_WLLPS_CTRL_8822B 0x0090 46 #define REG_AFE_CTRL5_8822B 0x0094 47 #define REG_GPIO_DEBOUNCE_CTRL_8822B 0x0098 48 #define REG_RPWM2_8822B 0x009C 49 #define REG_SYSON_FSM_MON_8822B 0x00A0 50 #define REG_AFE_CTRL6_8822B 0x00A4 51 #define REG_PMC_DBG_CTRL1_8822B 0x00A8 52 #define REG_AFE_CTRL7_8822B 0x00AC 53 #define REG_HIMR0_8822B 0x00B0 54 #define REG_HISR0_8822B 0x00B4 55 #define REG_HIMR1_8822B 0x00B8 56 #define REG_HISR1_8822B 0x00BC 57 #define REG_DBG_PORT_SEL_8822B 0x00C0 58 #define REG_PAD_CTRL2_8822B 0x00C4 59 #define REG_PMC_DBG_CTRL2_8822B 0x00CC 60 #define REG_BIST_CTRL_8822B 0x00D0 61 #define REG_BIST_RPT_8822B 0x00D4 62 #define REG_MEM_CTRL_8822B 0x00D8 63 #define REG_AFE_CTRL8_8822B 0x00DC 64 #define REG_USB_SIE_INTF_8822B 0x00E0 65 #define REG_PCIE_MIO_INTF_8822B 0x00E4 66 #define REG_PCIE_MIO_INTD_8822B 0x00E8 67 #define REG_WLRF1_8822B 0x00EC 68 #define REG_SYS_CFG1_8822B 0x00F0 69 #define REG_SYS_STATUS1_8822B 0x00F4 70 #define REG_SYS_STATUS2_8822B 0x00F8 71 #define REG_SYS_CFG2_8822B 0x00FC 72 #define REG_SYS_CFG3_8822B 0x1000 73 #define REG_SYS_CFG4_8822B 0x1034 74 #define REG_SYS_CFG5_8822B 0x1070 75 #define REG_CPU_DMEM_CON_8822B 0x1080 76 #define REG_BOOT_REASON_8822B 0x1088 77 #define REG_NFCPAD_CTRL_8822B 0x10A8 78 #define REG_HIMR2_8822B 0x10B0 79 #define REG_HISR2_8822B 0x10B4 80 #define REG_HIMR3_8822B 0x10B8 81 #define REG_HISR3_8822B 0x10BC 82 #define REG_SW_MDIO_8822B 0x10C0 83 #define REG_SW_FLUSH_8822B 0x10C4 84 #define REG_H2C_PKT_READADDR_8822B 0x10D0 85 #define REG_H2C_PKT_WRITEADDR_8822B 0x10D4 86 #define REG_MEM_PWR_CRTL_8822B 0x10D8 87 #define REG_FW_DBG0_8822B 0x10E0 88 #define REG_FW_DBG1_8822B 0x10E4 89 #define REG_FW_DBG2_8822B 0x10E8 90 #define REG_FW_DBG3_8822B 0x10EC 91 #define REG_FW_DBG4_8822B 0x10F0 92 #define REG_FW_DBG5_8822B 0x10F4 93 #define REG_FW_DBG6_8822B 0x10F8 94 #define REG_FW_DBG7_8822B 0x10FC 95 #define REG_CR_8822B 0x0100 96 #define REG_TSF_CLK_STATE_8822B 0x0108 97 #define REG_TXDMA_PQ_MAP_8822B 0x010C 98 #define REG_TRXFF_BNDY_8822B 0x0114 99 #define REG_PTA_I2C_MBOX_8822B 0x0118 100 #define REG_RXFF_BNDY_8822B 0x011C 101 #define REG_FE1IMR_8822B 0x0120 102 #define REG_FE1ISR_8822B 0x0124 103 #define REG_CPWM_8822B 0x012C 104 #define REG_FWIMR_8822B 0x0130 105 #define REG_FWISR_8822B 0x0134 106 #define REG_FTIMR_8822B 0x0138 107 #define REG_FTISR_8822B 0x013C 108 #define REG_PKTBUF_DBG_CTRL_8822B 0x0140 109 #define REG_PKTBUF_DBG_DATA_L_8822B 0x0144 110 #define REG_PKTBUF_DBG_DATA_H_8822B 0x0148 111 #define REG_CPWM2_8822B 0x014C 112 #define REG_TC0_CTRL_8822B 0x0150 113 #define REG_TC1_CTRL_8822B 0x0154 114 #define REG_TC2_CTRL_8822B 0x0158 115 #define REG_TC3_CTRL_8822B 0x015C 116 #define REG_TC4_CTRL_8822B 0x0160 117 #define REG_TCUNIT_BASE_8822B 0x0164 118 #define REG_TC5_CTRL_8822B 0x0168 119 #define REG_TC6_CTRL_8822B 0x016C 120 #define REG_MBIST_FAIL_8822B 0x0170 121 #define REG_MBIST_START_PAUSE_8822B 0x0174 122 #define REG_MBIST_DONE_8822B 0x0178 123 #define REG_MBIST_FAIL_NRML_8822B 0x017C 124 #define REG_AES_DECRPT_DATA_8822B 0x0180 125 #define REG_AES_DECRPT_CFG_8822B 0x0184 126 #define REG_TMETER_8822B 0x0190 127 #define REG_OSC_32K_CTRL_8822B 0x0194 128 #define REG_32K_CAL_REG1_8822B 0x0198 129 #define REG_C2HEVT_8822B 0x01A0 130 #define REG_SW_DEFINED_PAGE1_8822B 0x01B8 131 #define REG_MCUTST_I_8822B 0x01C0 132 #define REG_MCUTST_II_8822B 0x01C4 133 #define REG_FMETHR_8822B 0x01C8 134 #define REG_HMETFR_8822B 0x01CC 135 #define REG_HMEBOX0_8822B 0x01D0 136 #define REG_HMEBOX1_8822B 0x01D4 137 #define REG_HMEBOX2_8822B 0x01D8 138 #define REG_HMEBOX3_8822B 0x01DC 139 #define REG_LLT_INIT_8822B 0x01E0 140 #define REG_LLT_INIT_ADDR_8822B 0x01E4 141 #define REG_BB_ACCESS_CTRL_8822B 0x01E8 142 #define REG_BB_ACCESS_DATA_8822B 0x01EC 143 #define REG_HMEBOX_E0_8822B 0x01F0 144 #define REG_HMEBOX_E1_8822B 0x01F4 145 #define REG_HMEBOX_E2_8822B 0x01F8 146 #define REG_HMEBOX_E3_8822B 0x01FC 147 #define REG_CR_EXT_8822B 0x1100 148 #define REG_FWFF_8822B 0x1114 149 #define REG_RXFF_PTR_V1_8822B 0x1118 150 #define REG_RXFF_WTR_V1_8822B 0x111C 151 #define REG_FE2IMR_8822B 0x1120 152 #define REG_FE2ISR_8822B 0x1124 153 #define REG_FE3IMR_8822B 0x1128 154 #define REG_FE3ISR_8822B 0x112C 155 #define REG_FE4IMR_8822B 0x1130 156 #define REG_FE4ISR_8822B 0x1134 157 #define REG_FT1IMR_8822B 0x1138 158 #define REG_FT1ISR_8822B 0x113C 159 #define REG_SPWR0_8822B 0x1140 160 #define REG_SPWR1_8822B 0x1144 161 #define REG_SPWR2_8822B 0x1148 162 #define REG_SPWR3_8822B 0x114C 163 #define REG_POWSEQ_8822B 0x1150 164 #define REG_TC7_CTRL_V1_8822B 0x1158 165 #define REG_TC8_CTRL_V1_8822B 0x115C 166 #define REG_FT2IMR_8822B 0x11E0 167 #define REG_FT2ISR_8822B 0x11E4 168 #define REG_MSG2_8822B 0x11F0 169 #define REG_MSG3_8822B 0x11F4 170 #define REG_MSG4_8822B 0x11F8 171 #define REG_MSG5_8822B 0x11FC 172 #define REG_FIFOPAGE_CTRL_1_8822B 0x0200 173 #define REG_FIFOPAGE_CTRL_2_8822B 0x0204 174 #define REG_AUTO_LLT_V1_8822B 0x0208 175 #define REG_TXDMA_OFFSET_CHK_8822B 0x020C 176 #define REG_TXDMA_STATUS_8822B 0x0210 177 #define REG_TX_DMA_DBG_8822B 0x0214 178 #define REG_TQPNT1_8822B 0x0218 179 #define REG_TQPNT2_8822B 0x021C 180 #define REG_TQPNT3_8822B 0x0220 181 #define REG_TQPNT4_8822B 0x0224 182 #define REG_RQPN_CTRL_1_8822B 0x0228 183 #define REG_RQPN_CTRL_2_8822B 0x022C 184 #define REG_FIFOPAGE_INFO_1_8822B 0x0230 185 #define REG_FIFOPAGE_INFO_2_8822B 0x0234 186 #define REG_FIFOPAGE_INFO_3_8822B 0x0238 187 #define REG_FIFOPAGE_INFO_4_8822B 0x023C 188 #define REG_FIFOPAGE_INFO_5_8822B 0x0240 189 #define REG_H2C_HEAD_8822B 0x0244 190 #define REG_H2C_TAIL_8822B 0x0248 191 #define REG_H2C_READ_ADDR_8822B 0x024C 192 #define REG_H2C_WR_ADDR_8822B 0x0250 193 #define REG_H2C_INFO_8822B 0x0254 194 #define REG_RXDMA_AGG_PG_TH_8822B 0x0280 195 #define REG_RXPKT_NUM_8822B 0x0284 196 #define REG_RXDMA_STATUS_8822B 0x0288 197 #define REG_RXDMA_DPR_8822B 0x028C 198 #define REG_RXDMA_MODE_8822B 0x0290 199 #define REG_C2H_PKT_8822B 0x0294 200 #define REG_FWFF_C2H_8822B 0x0298 201 #define REG_FWFF_CTRL_8822B 0x029C 202 #define REG_FWFF_PKT_INFO_8822B 0x02A0 203 #define REG_DDMA_CH0SA_8822B 0x1200 204 #define REG_DDMA_CH0DA_8822B 0x1204 205 #define REG_DDMA_CH0CTRL_8822B 0x1208 206 #define REG_DDMA_CH1SA_8822B 0x1210 207 #define REG_DDMA_CH1DA_8822B 0x1214 208 #define REG_DDMA_CH1CTRL_8822B 0x1218 209 #define REG_DDMA_CH2SA_8822B 0x1220 210 #define REG_DDMA_CH2DA_8822B 0x1224 211 #define REG_DDMA_CH2CTRL_8822B 0x1228 212 #define REG_DDMA_CH3SA_8822B 0x1230 213 #define REG_DDMA_CH3DA_8822B 0x1234 214 #define REG_DDMA_CH3CTRL_8822B 0x1238 215 #define REG_DDMA_CH4SA_8822B 0x1240 216 #define REG_DDMA_CH4DA_8822B 0x1244 217 #define REG_DDMA_CH4CTRL_8822B 0x1248 218 #define REG_DDMA_CH5SA_8822B 0x1250 219 #define REG_DDMA_CH5DA_8822B 0x1254 220 #define REG_REG_DDMA_CH5CTRL_8822B 0x1258 221 #define REG_DDMA_INT_MSK_8822B 0x12E0 222 #define REG_DDMA_CHSTATUS_8822B 0x12E8 223 #define REG_DDMA_CHKSUM_8822B 0x12F0 224 #define REG_DDMA_MONITOR_8822B 0x12FC 225 #define REG_PCIE_CTRL_8822B 0x0300 226 #define REG_INT_MIG_8822B 0x0304 227 #define REG_BCNQ_TXBD_DESA_8822B 0x0308 228 #define REG_MGQ_TXBD_DESA_8822B 0x0310 229 #define REG_VOQ_TXBD_DESA_8822B 0x0318 230 #define REG_VIQ_TXBD_DESA_8822B 0x0320 231 #define REG_BEQ_TXBD_DESA_8822B 0x0328 232 #define REG_BKQ_TXBD_DESA_8822B 0x0330 233 #define REG_RXQ_RXBD_DESA_8822B 0x0338 234 #define REG_HI0Q_TXBD_DESA_8822B 0x0340 235 #define REG_HI1Q_TXBD_DESA_8822B 0x0348 236 #define REG_HI2Q_TXBD_DESA_8822B 0x0350 237 #define REG_HI3Q_TXBD_DESA_8822B 0x0358 238 #define REG_HI4Q_TXBD_DESA_8822B 0x0360 239 #define REG_HI5Q_TXBD_DESA_8822B 0x0368 240 #define REG_HI6Q_TXBD_DESA_8822B 0x0370 241 #define REG_HI7Q_TXBD_DESA_8822B 0x0378 242 #define REG_MGQ_TXBD_NUM_8822B 0x0380 243 #define REG_RX_RXBD_NUM_8822B 0x0382 244 #define REG_VOQ_TXBD_NUM_8822B 0x0384 245 #define REG_VIQ_TXBD_NUM_8822B 0x0386 246 #define REG_BEQ_TXBD_NUM_8822B 0x0388 247 #define REG_BKQ_TXBD_NUM_8822B 0x038A 248 #define REG_HI0Q_TXBD_NUM_8822B 0x038C 249 #define REG_HI1Q_TXBD_NUM_8822B 0x038E 250 #define REG_HI2Q_TXBD_NUM_8822B 0x0390 251 #define REG_HI3Q_TXBD_NUM_8822B 0x0392 252 #define REG_HI4Q_TXBD_NUM_8822B 0x0394 253 #define REG_HI5Q_TXBD_NUM_8822B 0x0396 254 #define REG_HI6Q_TXBD_NUM_8822B 0x0398 255 #define REG_HI7Q_TXBD_NUM_8822B 0x039A 256 #define REG_TSFTIMER_HCI_8822B 0x039C 257 #define REG_BD_RWPTR_CLR_8822B 0x039C 258 #define REG_VOQ_TXBD_IDX_8822B 0x03A0 259 #define REG_VIQ_TXBD_IDX_8822B 0x03A4 260 #define REG_BEQ_TXBD_IDX_8822B 0x03A8 261 #define REG_BKQ_TXBD_IDX_8822B 0x03AC 262 #define REG_MGQ_TXBD_IDX_8822B 0x03B0 263 #define REG_RXQ_RXBD_IDX_8822B 0x03B4 264 #define REG_HI0Q_TXBD_IDX_8822B 0x03B8 265 #define REG_HI1Q_TXBD_IDX_8822B 0x03BC 266 #define REG_HI2Q_TXBD_IDX_8822B 0x03C0 267 #define REG_HI3Q_TXBD_IDX_8822B 0x03C4 268 #define REG_HI4Q_TXBD_IDX_8822B 0x03C8 269 #define REG_HI5Q_TXBD_IDX_8822B 0x03CC 270 #define REG_HI6Q_TXBD_IDX_8822B 0x03D0 271 #define REG_HI7Q_TXBD_IDX_8822B 0x03D4 272 #define REG_DBG_SEL_V1_8822B 0x03D8 273 #define REG_PCIE_HRPWM1_V1_8822B 0x03D9 274 #define REG_PCIE_HCPWM1_V1_8822B 0x03DA 275 #define REG_PCIE_CTRL2_8822B 0x03DB 276 #define REG_PCIE_HRPWM2_V1_8822B 0x03DC 277 #define REG_PCIE_HCPWM2_V1_8822B 0x03DE 278 #define REG_PCIE_H2C_MSG_V1_8822B 0x03E0 279 #define REG_PCIE_C2H_MSG_V1_8822B 0x03E4 280 #define REG_DBI_WDATA_V1_8822B 0x03E8 281 #define REG_DBI_RDATA_V1_8822B 0x03EC 282 #define REG_DBI_FLAG_V1_8822B 0x03F0 283 #define REG_MDIO_V1_8822B 0x03F4 284 #define REG_PCIE_MIX_CFG_8822B 0x03F8 285 #define REG_HCI_MIX_CFG_8822B 0x03FC 286 #define REG_STC_INT_CS_8822B 0x1300 287 #define REG_ST_INT_CFG_8822B 0x1304 288 #define REG_CMU_DLY_CTRL_8822B 0x1310 289 #define REG_CMU_DLY_CFG_8822B 0x1314 290 #define REG_H2CQ_TXBD_DESA_8822B 0x1320 291 #define REG_H2CQ_TXBD_NUM_8822B 0x1328 292 #define REG_H2CQ_TXBD_IDX_8822B 0x132C 293 #define REG_H2CQ_CSR_8822B 0x1330 294 #define REG_Q0_INFO_8822B 0x0400 295 #define REG_Q1_INFO_8822B 0x0404 296 #define REG_Q2_INFO_8822B 0x0408 297 #define REG_Q3_INFO_8822B 0x040C 298 #define REG_MGQ_INFO_8822B 0x0410 299 #define REG_HIQ_INFO_8822B 0x0414 300 #define REG_BCNQ_INFO_8822B 0x0418 301 #define REG_TXPKT_EMPTY_8822B 0x041A 302 #define REG_CPU_MGQ_INFO_8822B 0x041C 303 #define REG_FWHW_TXQ_CTRL_8822B 0x0420 304 #define REG_DATAFB_SEL_8822B 0x0423 305 #define REG_BCNQ_BDNY_V1_8822B 0x0424 306 #define REG_LIFETIME_EN_8822B 0x0426 307 #define REG_SPEC_SIFS_8822B 0x0428 308 #define REG_RETRY_LIMIT_8822B 0x042A 309 #define REG_TXBF_CTRL_8822B 0x042C 310 #define REG_DARFRC_8822B 0x0430 311 #define REG_RARFRC_8822B 0x0438 312 #define REG_RRSR_8822B 0x0440 313 #define REG_ARFR0_8822B 0x0444 314 #define REG_ARFR1_V1_8822B 0x044C 315 #define REG_CCK_CHECK_8822B 0x0454 316 #define REG_AMPDU_MAX_TIME_V1_8822B 0x0455 317 #define REG_BCNQ1_BDNY_V1_8822B 0x0456 318 #define REG_AMPDU_MAX_LENGTH_8822B 0x0458 319 #define REG_ACQ_STOP_8822B 0x045C 320 #define REG_NDPA_RATE_8822B 0x045D 321 #define REG_TX_HANG_CTRL_8822B 0x045E 322 #define REG_NDPA_OPT_CTRL_8822B 0x045F 323 #define REG_RD_RESP_PKT_TH_8822B 0x0463 324 #define REG_CMDQ_INFO_8822B 0x0464 325 #define REG_Q4_INFO_8822B 0x0468 326 #define REG_Q5_INFO_8822B 0x046C 327 #define REG_Q6_INFO_8822B 0x0470 328 #define REG_Q7_INFO_8822B 0x0474 329 #define REG_WMAC_LBK_BUF_HD_V1_8822B 0x0478 330 #define REG_MGQ_BDNY_V1_8822B 0x047A 331 #define REG_TXRPT_CTRL_8822B 0x047C 332 #define REG_INIRTS_RATE_SEL_8822B 0x0480 333 #define REG_BASIC_CFEND_RATE_8822B 0x0481 334 #define REG_STBC_CFEND_RATE_8822B 0x0482 335 #define REG_DATA_SC_8822B 0x0483 336 #define REG_MACID_SLEEP3_8822B 0x0484 337 #define REG_MACID_SLEEP1_8822B 0x0488 338 #define REG_ARFR2_V1_8822B 0x048C 339 #define REG_ARFR3_V1_8822B 0x0494 340 #define REG_ARFR4_8822B 0x049C 341 #define REG_ARFR5_8822B 0x04A4 342 #define REG_TXRPT_START_OFFSET_8822B 0x04AC 343 #define REG_POWER_STAGE1_8822B 0x04B4 344 #define REG_POWER_STAGE2_8822B 0x04B8 345 #define REG_SW_AMPDU_BURST_MODE_CTRL_8822B 0x04BC 346 #define REG_PKT_LIFE_TIME_8822B 0x04C0 347 #define REG_STBC_SETTING_8822B 0x04C4 348 #define REG_STBC_SETTING2_8822B 0x04C5 349 #define REG_QUEUE_CTRL_8822B 0x04C6 350 #define REG_SINGLE_AMPDU_CTRL_8822B 0x04C7 351 #define REG_PROT_MODE_CTRL_8822B 0x04C8 352 #define REG_BAR_MODE_CTRL_8822B 0x04CC 353 #define REG_RA_TRY_RATE_AGG_LMT_8822B 0x04CF 354 #define REG_MACID_SLEEP2_8822B 0x04D0 355 #define REG_MACID_SLEEP_8822B 0x04D4 356 #define REG_HW_SEQ0_8822B 0x04D8 357 #define REG_HW_SEQ1_8822B 0x04DA 358 #define REG_HW_SEQ2_8822B 0x04DC 359 #define REG_HW_SEQ3_8822B 0x04DE 360 #define REG_NULL_PKT_STATUS_V1_8822B 0x04E0 361 #define REG_PTCL_ERR_STATUS_8822B 0x04E2 362 #define REG_NULL_PKT_STATUS_EXTEND_8822B 0x04E3 363 #define REG_VIDEO_ENHANCEMENT_FUN_8822B 0x04E4 364 #define REG_BT_POLLUTE_PKT_CNT_8822B 0x04E8 365 #define REG_PTCL_DBG_8822B 0x04EC 366 #define REG_CPUMGQ_TIMER_CTRL2_8822B 0x04F4 367 #define REG_DUMMY_PAGE4_V1_8822B 0x04FC 368 #define REG_MOREDATA_8822B 0x04FE 369 #define REG_Q0_Q1_INFO_8822B 0x1400 370 #define REG_Q2_Q3_INFO_8822B 0x1404 371 #define REG_Q4_Q5_INFO_8822B 0x1408 372 #define REG_Q6_Q7_INFO_8822B 0x140C 373 #define REG_MGQ_HIQ_INFO_8822B 0x1410 374 #define REG_CMDQ_BCNQ_INFO_8822B 0x1414 375 #define REG_USEREG_SETTING_8822B 0x1420 376 #define REG_AESIV_SETTING_8822B 0x1424 377 #define REG_BF0_TIME_SETTING_8822B 0x1428 378 #define REG_BF1_TIME_SETTING_8822B 0x142C 379 #define REG_BF_TIMEOUT_EN_8822B 0x1430 380 #define REG_MACID_RELEASE0_8822B 0x1434 381 #define REG_MACID_RELEASE1_8822B 0x1438 382 #define REG_MACID_RELEASE2_8822B 0x143C 383 #define REG_MACID_RELEASE3_8822B 0x1440 384 #define REG_MACID_RELEASE_SETTING_8822B 0x1444 385 #define REG_FAST_EDCA_VOVI_SETTING_8822B 0x1448 386 #define REG_FAST_EDCA_BEBK_SETTING_8822B 0x144C 387 #define REG_MACID_DROP0_8822B 0x1450 388 #define REG_MACID_DROP1_8822B 0x1454 389 #define REG_MACID_DROP2_8822B 0x1458 390 #define REG_MACID_DROP3_8822B 0x145C 391 #define REG_R_MACID_RELEASE_SUCCESS_0_8822B 0x1460 392 #define REG_R_MACID_RELEASE_SUCCESS_1_8822B 0x1464 393 #define REG_R_MACID_RELEASE_SUCCESS_2_8822B 0x1468 394 #define REG_R_MACID_RELEASE_SUCCESS_3_8822B 0x146C 395 #define REG_MGG_FIFO_CRTL_8822B 0x1470 396 #define REG_MGG_FIFO_INT_8822B 0x1474 397 #define REG_MGG_FIFO_LIFETIME_8822B 0x1478 398 #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C 399 #define REG_MACID_SHCUT_OFFSET_8822B 0x1480 400 #define REG_MU_TX_CTL_8822B 0x14C0 401 #define REG_MU_STA_GID_VLD_8822B 0x14C4 402 #define REG_MU_STA_USER_POS_INFO_8822B 0x14C8 403 #define REG_MU_TRX_DBG_CNT_8822B 0x14D0 404 #define REG_EDCA_VO_PARAM_8822B 0x0500 405 #define REG_EDCA_VI_PARAM_8822B 0x0504 406 #define REG_EDCA_BE_PARAM_8822B 0x0508 407 #define REG_EDCA_BK_PARAM_8822B 0x050C 408 #define REG_BCNTCFG_8822B 0x0510 409 #define REG_PIFS_8822B 0x0512 410 #define REG_RDG_PIFS_8822B 0x0513 411 #define REG_SIFS_8822B 0x0514 412 #define REG_TSFTR_SYN_OFFSET_8822B 0x0518 413 #define REG_AGGR_BREAK_TIME_8822B 0x051A 414 #define REG_SLOT_8822B 0x051B 415 #define REG_TX_PTCL_CTRL_8822B 0x0520 416 #define REG_TXPAUSE_8822B 0x0522 417 #define REG_DIS_TXREQ_CLR_8822B 0x0523 418 #define REG_RD_CTRL_8822B 0x0524 419 #define REG_MBSSID_CTRL_8822B 0x0526 420 #define REG_P2PPS_CTRL_8822B 0x0527 421 #define REG_PKT_LIFETIME_CTRL_8822B 0x0528 422 #define REG_P2PPS_SPEC_STATE_8822B 0x052B 423 #define REG_BAR_TX_CTRL_8822B 0x0530 424 #define REG_QUEUE_INCOL_THR_8822B 0x0538 425 #define REG_QUEUE_INCOL_EN_8822B 0x053C 426 #define REG_TBTT_PROHIBIT_8822B 0x0540 427 #define REG_P2PPS_STATE_8822B 0x0543 428 #define REG_RD_NAV_NXT_8822B 0x0544 429 #define REG_NAV_PROT_LEN_8822B 0x0546 430 #define REG_BCN_CTRL_8822B 0x0550 431 #define REG_BCN_CTRL_CLINT0_8822B 0x0551 432 #define REG_MBID_NUM_8822B 0x0552 433 #define REG_DUAL_TSF_RST_8822B 0x0553 434 #define REG_MBSSID_BCN_SPACE_8822B 0x0554 435 #define REG_DRVERLYINT_8822B 0x0558 436 #define REG_BCNDMATIM_8822B 0x0559 437 #define REG_ATIMWND_8822B 0x055A 438 #define REG_USTIME_TSF_8822B 0x055C 439 #define REG_BCN_MAX_ERR_8822B 0x055D 440 #define REG_RXTSF_OFFSET_CCK_8822B 0x055E 441 #define REG_RXTSF_OFFSET_OFDM_8822B 0x055F 442 #define REG_TSFTR_8822B 0x0560 443 #define REG_FREERUN_CNT_8822B 0x0568 444 #define REG_ATIMWND1_V1_8822B 0x0570 445 #define REG_TBTT_PROHIBIT_INFRA_8822B 0x0571 446 #define REG_CTWND_8822B 0x0572 447 #define REG_BCNIVLCUNT_8822B 0x0573 448 #define REG_BCNDROPCTRL_8822B 0x0574 449 #define REG_HGQ_TIMEOUT_PERIOD_8822B 0x0575 450 #define REG_TXCMD_TIMEOUT_PERIOD_8822B 0x0576 451 #define REG_MISC_CTRL_8822B 0x0577 452 #define REG_BCN_CTRL_CLINT1_8822B 0x0578 453 #define REG_BCN_CTRL_CLINT2_8822B 0x0579 454 #define REG_BCN_CTRL_CLINT3_8822B 0x057A 455 #define REG_EXTEND_CTRL_8822B 0x057B 456 #define REG_P2PPS1_SPEC_STATE_8822B 0x057C 457 #define REG_P2PPS1_STATE_8822B 0x057D 458 #define REG_P2PPS2_SPEC_STATE_8822B 0x057E 459 #define REG_P2PPS2_STATE_8822B 0x057F 460 #define REG_PS_TIMER0_8822B 0x0580 461 #define REG_PS_TIMER1_8822B 0x0584 462 #define REG_PS_TIMER2_8822B 0x0588 463 #define REG_TBTT_CTN_AREA_8822B 0x058C 464 #define REG_FORCE_BCN_IFS_8822B 0x058E 465 #define REG_TXOP_MIN_8822B 0x0590 466 #define REG_PRE_BKF_TIME_8822B 0x0592 467 #define REG_CROSS_TXOP_CTRL_8822B 0x0593 468 #define REG_ATIMWND2_8822B 0x05A0 469 #define REG_ATIMWND3_8822B 0x05A1 470 #define REG_ATIMWND4_8822B 0x05A2 471 #define REG_ATIMWND5_8822B 0x05A3 472 #define REG_ATIMWND6_8822B 0x05A4 473 #define REG_ATIMWND7_8822B 0x05A5 474 #define REG_ATIMUGT_8822B 0x05A6 475 #define REG_HIQ_NO_LMT_EN_8822B 0x05A7 476 #define REG_DTIM_COUNTER_ROOT_8822B 0x05A8 477 #define REG_DTIM_COUNTER_VAP1_8822B 0x05A9 478 #define REG_DTIM_COUNTER_VAP2_8822B 0x05AA 479 #define REG_DTIM_COUNTER_VAP3_8822B 0x05AB 480 #define REG_DTIM_COUNTER_VAP4_8822B 0x05AC 481 #define REG_DTIM_COUNTER_VAP5_8822B 0x05AD 482 #define REG_DTIM_COUNTER_VAP6_8822B 0x05AE 483 #define REG_DTIM_COUNTER_VAP7_8822B 0x05AF 484 #define REG_DIS_ATIM_8822B 0x05B0 485 #define REG_EARLY_128US_8822B 0x05B1 486 #define REG_P2PPS1_CTRL_8822B 0x05B2 487 #define REG_P2PPS2_CTRL_8822B 0x05B3 488 #define REG_TIMER0_SRC_SEL_8822B 0x05B4 489 #define REG_NOA_UNIT_SEL_8822B 0x05B5 490 #define REG_P2POFF_DIS_TXTIME_8822B 0x05B7 491 #define REG_MBSSID_BCN_SPACE2_8822B 0x05B8 492 #define REG_MBSSID_BCN_SPACE3_8822B 0x05BC 493 #define REG_ACMHWCTRL_8822B 0x05C0 494 #define REG_ACMRSTCTRL_8822B 0x05C1 495 #define REG_ACMAVG_8822B 0x05C2 496 #define REG_VO_ADMTIME_8822B 0x05C4 497 #define REG_VI_ADMTIME_8822B 0x05C6 498 #define REG_BE_ADMTIME_8822B 0x05C8 499 #define REG_EDCA_RANDOM_GEN_8822B 0x05CC 500 #define REG_TXCMD_NOA_SEL_8822B 0x05CF 501 #define REG_NOA_PARAM_8822B 0x05E0 502 #define REG_P2P_RST_8822B 0x05F0 503 #define REG_SCHEDULER_RST_8822B 0x05F1 504 #define REG_SCH_TXCMD_8822B 0x05F8 505 #define REG_PAGE5_DUMMY_8822B 0x05FC 506 #define REG_CPUMGQ_TX_TIMER_8822B 0x1500 507 #define REG_PS_TIMER_A_8822B 0x1504 508 #define REG_PS_TIMER_B_8822B 0x1508 509 #define REG_PS_TIMER_C_8822B 0x150C 510 #define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B 0x1510 511 #define REG_CPUMGQ_TX_TIMER_EARLY_8822B 0x1514 512 #define REG_PS_TIMER_A_EARLY_8822B 0x1515 513 #define REG_PS_TIMER_B_EARLY_8822B 0x1516 514 #define REG_PS_TIMER_C_EARLY_8822B 0x1517 515 #define REG_WMAC_CR_8822B 0x0600 516 #define REG_WMAC_FWPKT_CR_8822B 0x0601 517 #define REG_BWOPMODE_8822B 0x0603 518 #define REG_TCR_8822B 0x0604 519 #define REG_RCR_8822B 0x0608 520 #define REG_RX_PKT_LIMIT_8822B 0x060C 521 #define REG_RX_DLK_TIME_8822B 0x060D 522 #define REG_RX_DRVINFO_SZ_8822B 0x060F 523 #define REG_MACID_8822B 0x0610 524 #define REG_BSSID_8822B 0x0618 525 #define REG_MAR_8822B 0x0620 526 #define REG_MBIDCAMCFG_1_8822B 0x0628 527 #define REG_MBIDCAMCFG_2_8822B 0x062C 528 #define REG_WMAC_TCR_TSFT_OFS_8822B 0x0630 529 #define REG_UDF_THSD_8822B 0x0632 530 #define REG_ZLD_NUM_8822B 0x0633 531 #define REG_STMP_THSD_8822B 0x0634 532 #define REG_WMAC_TXTIMEOUT_8822B 0x0635 533 #define REG_MCU_TEST_2_V1_8822B 0x0636 534 #define REG_USTIME_EDCA_8822B 0x0638 535 #define REG_MAC_SPEC_SIFS_8822B 0x063A 536 #define REG_RESP_SIFS_CCK_8822B 0x063C 537 #define REG_RESP_SIFS_OFDM_8822B 0x063E 538 #define REG_ACKTO_8822B 0x0640 539 #define REG_CTS2TO_8822B 0x0641 540 #define REG_EIFS_8822B 0x0642 541 #define REG_NAV_CTRL_8822B 0x0650 542 #define REG_BACAMCMD_8822B 0x0654 543 #define REG_BACAMCONTENT_8822B 0x0658 544 #define REG_LBDLY_8822B 0x0660 545 #define REG_WMAC_BACAM_RPMEN_8822B 0x0661 546 #define REG_TX_RX_8822B 0x0662 547 #define REG_RXERR_RPT_8822B 0x0664 548 #define REG_WMAC_TRXPTCL_CTL_8822B 0x0668 549 #define REG_CAMCMD_8822B 0x0670 550 #define REG_CAMWRITE_8822B 0x0674 551 #define REG_CAMREAD_8822B 0x0678 552 #define REG_CAMDBG_8822B 0x067C 553 #define REG_SECCFG_8822B 0x0680 554 #define REG_RXFILTER_CATEGORY_1_8822B 0x0682 555 #define REG_RXFILTER_ACTION_1_8822B 0x0683 556 #define REG_RXFILTER_CATEGORY_2_8822B 0x0684 557 #define REG_RXFILTER_ACTION_2_8822B 0x0685 558 #define REG_RXFILTER_CATEGORY_3_8822B 0x0686 559 #define REG_RXFILTER_ACTION_3_8822B 0x0687 560 #define REG_RXFLTMAP3_8822B 0x0688 561 #define REG_RXFLTMAP4_8822B 0x068A 562 #define REG_RXFLTMAP5_8822B 0x068C 563 #define REG_RXFLTMAP6_8822B 0x068E 564 #define REG_WOW_CTRL_8822B 0x0690 565 #define REG_NAN_RX_TSF_FILTER_8822B 0x0691 566 #define REG_PS_RX_INFO_8822B 0x0692 567 #define REG_WMMPS_UAPSD_TID_8822B 0x0693 568 #define REG_LPNAV_CTRL_8822B 0x0694 569 #define REG_WKFMCAM_CMD_8822B 0x0698 570 #define REG_WKFMCAM_RWD_8822B 0x069C 571 #define REG_RXFLTMAP0_8822B 0x06A0 572 #define REG_RXFLTMAP1_8822B 0x06A2 573 #define REG_RXFLTMAP_8822B 0x06A4 574 #define REG_BCN_PSR_RPT_8822B 0x06A8 575 #define REG_FLC_RPC_8822B 0x06AC 576 #define REG_FLC_RPCT_8822B 0x06AD 577 #define REG_FLC_PTS_8822B 0x06AE 578 #define REG_FLC_TRPC_8822B 0x06AF 579 #define REG_RXPKTMON_CTRL_8822B 0x06B0 580 #define REG_STATE_MON_8822B 0x06B4 581 #define REG_ERROR_MON_8822B 0x06B8 582 #define REG_SEARCH_MACID_8822B 0x06BC 583 #define REG_BT_COEX_TABLE_8822B 0x06C0 584 #define REG_RXCMD_0_8822B 0x06D0 585 #define REG_RXCMD_1_8822B 0x06D4 586 #define REG_WMAC_RESP_TXINFO_8822B 0x06D8 587 #define REG_BBPSF_CTRL_8822B 0x06DC 588 #define REG_P2P_RX_BCN_NOA_8822B 0x06E0 589 #define REG_ASSOCIATED_BFMER0_INFO_8822B 0x06E4 590 #define REG_ASSOCIATED_BFMER1_INFO_8822B 0x06EC 591 #define REG_TX_CSI_RPT_PARAM_BW20_8822B 0x06F4 592 #define REG_TX_CSI_RPT_PARAM_BW40_8822B 0x06F8 593 #define REG_TX_CSI_RPT_PARAM_BW80_8822B 0x06FC 594 #define REG_BCN_PSR_RPT2_8822B 0x1600 595 #define REG_BCN_PSR_RPT3_8822B 0x1604 596 #define REG_BCN_PSR_RPT4_8822B 0x1608 597 #define REG_A1_ADDR_MASK_8822B 0x160C 598 #define REG_MACID2_8822B 0x1620 599 #define REG_BSSID2_8822B 0x1628 600 #define REG_MACID3_8822B 0x1630 601 #define REG_BSSID3_8822B 0x1638 602 #define REG_MACID4_8822B 0x1640 603 #define REG_BSSID4_8822B 0x1648 604 #define REG_NOA_REPORT_8822B 0x1650 605 #define REG_PWRBIT_SETTING_8822B 0x1660 606 #define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0 607 #define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8 608 #define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0 609 #define REG_TRANSMIT_ADDRSS_3_8822B 0x16B8 610 #define REG_TRANSMIT_ADDRSS_4_8822B 0x16C0 611 #define REG_MACID1_8822B 0x0700 612 #define REG_BSSID1_8822B 0x0708 613 #define REG_BCN_PSR_RPT1_8822B 0x0710 614 #define REG_ASSOCIATED_BFMEE_SEL_8822B 0x0714 615 #define REG_SND_PTCL_CTRL_8822B 0x0718 616 #define REG_RX_CSI_RPT_INFO_8822B 0x071C 617 #define REG_NS_ARP_CTRL_8822B 0x0720 618 #define REG_NS_ARP_INFO_8822B 0x0724 619 #define REG_BEAMFORMING_INFO_NSARP_V1_8822B 0x0728 620 #define REG_BEAMFORMING_INFO_NSARP_8822B 0x072C 621 #define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B 0x0750 622 #define REG_WMAC_SWAES_CFG_8822B 0x0760 623 #define REG_BT_COEX_V2_8822B 0x0762 624 #define REG_BT_COEX_8822B 0x0764 625 #define REG_WLAN_ACT_MASK_CTRL_8822B 0x0768 626 #define REG_BT_COEX_ENHANCED_INTR_CTRL_8822B 0x076E 627 #define REG_BT_ACT_STATISTICS_8822B 0x0770 628 #define REG_BT_STATISTICS_CONTROL_REGISTER_8822B 0x0778 629 #define REG_BT_STATUS_REPORT_REGISTER_8822B 0x077C 630 #define REG_BT_INTERRUPT_CONTROL_REGISTER_8822B 0x0780 631 #define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B 0x0784 632 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B 0x0785 633 #define REG_BT_INTERRUPT_STATUS_REGISTER_8822B 0x078F 634 #define REG_BT_TDMA_TIME_REGISTER_8822B 0x0790 635 #define REG_BT_ACT_REGISTER_8822B 0x0794 636 #define REG_OBFF_CTRL_BASIC_8822B 0x0798 637 #define REG_OBFF_CTRL2_TIMER_8822B 0x079C 638 #define REG_LTR_CTRL_BASIC_8822B 0x07A0 639 #define REG_LTR_CTRL2_TIMER_THRESHOLD_8822B 0x07A4 640 #define REG_LTR_IDLE_LATENCY_V1_8822B 0x07A8 641 #define REG_LTR_ACTIVE_LATENCY_V1_8822B 0x07AC 642 #define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B 0x07B0 643 #define REG_WMAC_PKTCNT_RWD_8822B 0x07B8 644 #define REG_WMAC_PKTCNT_CTRL_8822B 0x07BC 645 #define REG_IQ_DUMP_8822B 0x07C0 646 #define REG_WMAC_FTM_CTL_8822B 0x07CC 647 #define REG_WMAC_IQ_MDPK_FUNC_8822B 0x07CE 648 #define REG_WMAC_OPTION_FUNCTION_8822B 0x07D0 649 #define REG_RX_FILTER_FUNCTION_8822B 0x07DA 650 #define REG_NDP_SIG_8822B 0x07E0 651 #define REG_TXCMD_INFO_FOR_RSP_PKT_8822B 0x07E4 652 #define REG_RTS_ADDRESS_0_8822B 0x07F0 653 #define REG_RTS_ADDRESS_1_8822B 0x07F8 654 #define REG__RPFM_MAP1_8822B 0x07FE 655 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B 0x1700 656 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B 0x1704 657 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B 0x1708 658 #define REG_SDIO_TX_CTRL_8822B 0x10250000 659 #define REG_SDIO_HIMR_8822B 0x10250014 660 #define REG_SDIO_HISR_8822B 0x10250018 661 #define REG_SDIO_RX_REQ_LEN_8822B 0x1025001C 662 #define REG_SDIO_FREE_TXPG_SEQ_V1_8822B 0x1025001F 663 #define REG_SDIO_FREE_TXPG_8822B 0x10250020 664 #define REG_SDIO_FREE_TXPG2_8822B 0x10250024 665 #define REG_SDIO_OQT_FREE_TXPG_V1_8822B 0x10250028 666 #define REG_SDIO_HTSFR_INFO_8822B 0x10250030 667 #define REG_SDIO_HCPWM1_V2_8822B 0x10250038 668 #define REG_SDIO_HCPWM2_V2_8822B 0x1025003A 669 #define REG_SDIO_INDIRECT_REG_CFG_8822B 0x10250040 670 #define REG_SDIO_INDIRECT_REG_DATA_8822B 0x10250044 671 #define REG_SDIO_H2C_8822B 0x10250060 672 #define REG_SDIO_C2H_8822B 0x10250064 673 #define REG_SDIO_HRPWM1_8822B 0x10250080 674 #define REG_SDIO_HRPWM2_8822B 0x10250082 675 #define REG_SDIO_HPS_CLKR_8822B 0x10250084 676 #define REG_SDIO_BUS_CTRL_8822B 0x10250085 677 #define REG_SDIO_HSUS_CTRL_8822B 0x10250086 678 #define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088 679 #define REG_SDIO_CMD_CRC_8822B 0x1025008A 680 #define REG_SDIO_HSISR_8822B 0x10250090 681 #define REG_SDIO_HSIMR_8822B 0x10250091 682 #define REG_SDIO_ERR_RPT_8822B 0x102500C0 683 #define REG_SDIO_CMD_ERRCNT_8822B 0x102500C1 684 #define REG_SDIO_DATA_ERRCNT_8822B 0x102500C2 685 #define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4 686 #define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9 687 #define REG_SDIO_DATA_CRC_8822B 0x102500CA 688 #define REG_SDIO_DATA_REPLY_TIME_8822B 0x102500CB 689 690 #endif 691