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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 /////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_PCMCIA_H_ 96 #define _REG_PCMCIA_H_ 97 98 //----------------------------------------------------------------------------- 99 // Hardware Capability 100 //----------------------------------------------------------------------------- 101 // Base address should be initial. 102 #define PCMCIA_RIU_MAP u32PCMCIA_RIU_BaseAdd //obtain in init 103 104 //----------------------------------------------------------------------------- 105 // Macro and Define 106 //----------------------------------------------------------------------------- 107 //hardware spec 108 109 110 111 #define PCMBURST_WRITE 0x0001 112 #define PCMBURST_READ 0x0010 113 #define PCMBURST_STATUS 0x0100 114 115 116 #define REG_COMPANION_TOP_BANK 0x101E00 117 #define REG_CHIPTOP_ALLPAD_IN REG_COMPANION_TOP_BANK + 0xA1UL 118 #define ALL_PAD_IN_MASK 0x80UL 119 #define ALL_PAD_IN_DISABLE 0x00UL 120 #define REG_CHIPTOP_PCM_EN REG_COMPANION_TOP_BANK + 0xA3UL 121 #define PCM_ENABLE_MASK 0x03UL 122 #define PCM_ENABLE 0x03UL 123 #define REG_CHIPTOP_PCM_PE REG_COMPANION_TOP_BANK + 0x81UL 124 #define PE_ENABLE 0xFFUL 125 126 #define REG_COMPANION_CLKGEN0_BANK 0x100B00 127 #define REG_CLKGEN0_PCM REG_COMPANION_CLKGEN0_BANK + 0x34UL 128 #define CLK_ON 0x00UL 129 #define CLK_OFF 0x01UL 130 131 #define REG_COMPANION_INTR_CTRL_BANK 0x101900 132 #define REG_COMPANION_PCM_BANK 0x103500 133 #define REG_COMPANION_PCM2_BANK 0x103600 134 #define REG_COMPANION_PCMBURST_BANK 0x103700 135 136 #define REG_COMPANION_PCMBURST_ADDR 0x800002F4 // bank 1037, addr 0x7A) 137 #define REG_COMPANION_PCMBURST_WFIFO 0x80000300 138 #define REG_COMPANION_PCMBURST_RFIFO 0x80000A00 139 140 141 #define MSPI_CMD_RIU_W1 0x1D 142 // W : | RIU_W (1byte) | ADDR (2byte) | data ... 143 #define MSPI_CMD_RIU_RIT1 0x15 144 // W : | RIU_RT1 (1byte) | ADDR (2byte) | TA (turn around, 1byte) | 145 #define MSPI_CMD_MIU_W 0x25 146 // W : | MIU_W (1byte) | ADDR (4byte) | data ... 147 #define MSPI_CMD_MIU_R 0x20 148 // W : | MIU_R (1byte) | ADDR (4byte) | len = 0 (1byte) 149 #define MSPI_CMD_MIU_ST 0x21 150 // W : | MIU_ST (1byte) | 0 (1byte) 151 #define MSPI_CMD_CFG_W 0x05 152 153 #define MSPI_MIU_STATUS_NONE 0x00 // Initial status 154 #define MSPI_MIU_STATUS_WBUSY 0x01 // FIFO is not empty or MIU IF is busy 155 #define MSPI_MIU_STATUS_RBUSY 0x02 // FIFO is not empty or MIU IF is busy 156 #define MSPI_MIU_STATUS_OV 0x03 // FIFO overflow 157 #define MSPI_MIU_STATUS_COL 0x04 // SSPI and MIU interface collision 158 #define MSPI_MIU_STATUS_DONE 0x0A // RIU_W or RIU_R done 159 160 161 162 #define MAX_MSPI_BURST_WRITE_SIZE 65536 163 #define MAX_MSPI_BURST_READ_SIZE 32 164 #define MAX_PCMCIA_BURST_WRITE_SIZE 128 165 #define MAX_PCMCIA_BURST_READ_SIZE 128 166 167 #define MAX_MSPI_STATUS_COUNT 0x1024 168 169 #define REG_PCMCIA_BASE 0x3500UL 170 #define REG_CLKGEN0_BASE 0x0B00UL 171 172 #define REG_PCMCIA_PCM_MEM_IO_CMD REG_COMPANION_PCM_BANK + 0x00UL 173 #define REG_PCMCIA_ADDR0 REG_COMPANION_PCM_BANK + 0x02UL 174 #define REG_PCMCIA_ADDR1 REG_COMPANION_PCM_BANK + 0x03UL 175 #define REG_PCMCIA_WRITE_DATA REG_COMPANION_PCM_BANK + 0x04UL 176 #define REG_PCMCIA_FIRE_READ_DATA_CLEAR REG_COMPANION_PCM_BANK + 0x06UL 177 #define REG_PCMCIA_READ_DATA REG_COMPANION_PCM_BANK + 0x08UL 178 #define REG_PCMCIA_READ_DATA_DONE_BUS_IDLE REG_COMPANION_PCM_BANK + 0x09UL 179 #define REG_PCMCIA_INT_MASK_CLEAR REG_COMPANION_PCM_BANK + 0x0AUL 180 #define REG_PCMCIA_INT_MASK_CLEAR1 REG_COMPANION_PCM_BANK + 0x0BUL 181 #define REG_PCMCIA_STAT_INT_RAW_INT REG_COMPANION_PCM_BANK + 0x0EUL 182 #define REG_PCMCIA_STAT_INT_RAW_INT1 REG_COMPANION_PCM_BANK + 0x0FUL 183 #define REG_PCMCIA_MODULE_VCC_OOB REG_COMPANION_PCM_BANK + 0x10UL 184 185 #define REG_PCM_BURST_CTRL REG_COMPANION_PCMBURST_BANK + 0x00UL 186 #define REG_PCM_BURST_SW_RST_ON 0x01UL 187 #define REG_PCM_BURST_SW_RST_OFF 0x00UL 188 #define REG_PCM_BURST_SW_RST_MASK 0x01UL 189 190 #define REG_PCM_BURST_STATUS_CLR REG_COMPANION_PCMBURST_BANK + 0x8UL 191 #define REG_PCM_WRITE_FINISH_CLR 0x01UL 192 #define REG_PCM_READ_FINISH_CLR 0x02UL 193 #define REG_PCM_STATUS_READ_FINISH_CLR 0x04UL 194 195 #define REG_PCM_BURST_STATUS_0 REG_COMPANION_PCMBURST_BANK + 0x14UL 196 #define REG_PCM_BURST_WRITE_DONE 0x01UL 197 #define REG_PCM_BURST_READ_DONE 0x02UL 198 #define REG_PCM_BURST_READ_STATUS_DONE 0x04UL 199 200 #define REG_PCM_BURST_STATUS_1 REG_COMPANION_PCMBURST_BANK + 0x16UL 201 #define REG_PCM_WFIFO_EMPTY 0x01UL 202 #define REG_PCM_WFIFO_FULL 0x02UL 203 #define REG_PCM_RFIFO_EMPTY 0x40UL 204 #define REG_PCM_RFIFO_FULL 0x80UL 205 206 #define REG_PCM_BURST_WFIFO_RMN REG_COMPANION_PCMBURST_BANK + 0x18UL // [6:0] max 127 207 #define REG_PCM_BURST_RFIFO_RMN REG_COMPANION_PCMBURST_BANK + 0x19UL // [6:0] max 127 208 209 #define REG_HST0_IRQ_MASK_15_0 REG_COMPANION_INTR_CTRL_BANK + 0x29UL 210 #define REG_PCM_IRQ_BIT_SHFT 2UL 211 #define REG_PCM_IRQ_BIT_MASK (0x1UL << REG_PCM_IRQ_BIT_SHFT) 212 #define IRQ_MASK (1UL << REG_PCM_IRQ_BIT_SHFT) 213 #define IRQ_UNMASK (0UL << REG_PCM_IRQ_BIT_SHFT) 214 215 #define PCMCIA_ATTRIBMEMORY_READ 0x03UL 216 #define PCMCIA_ATTRIBMEMORY_WRITE 0x04UL 217 #define PCMCIA_IO_READ 0x05UL 218 #define PCMCIA_IO_WRITE 0x06UL 219 220 #define PCM_OOB_BIT_MASK 0x03UL 221 #define PCM_OOB_BIT_SHFT 6UL 222 223 #define PCM_OOB_CYCLE_EXTEND 0x3UL 224 // 00:th(CE)=4T (extend 3 active cycle) 225 // 01:th(CE)=3T (extend 2 active cycle) 226 // 10:th(CE)=2T (extend 1 active cycle) 227 // 11:th(CE)=1T 228 229 //----------------------------------------------------------------------------- 230 // Type and Structure 231 //----------------------------------------------------------------------------- 232 233 #endif // _REG_PCMCIA_H_ 234