1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_VOP_H_ 96 #define _REG_VOP_H_ 97 98 99 //------------------------------------------------------------------------------------------------- 100 // Hardware Capability 101 //------------------------------------------------------------------------------------------------- 102 103 104 //------------------------------------------------------------------------------------------------- 105 // Macro and Define 106 //------------------------------------------------------------------------------------------------- 107 108 109 //------------------------------------------------------------------------------ 110 // Base Address 111 //------------------------------------------------------------------------------ 112 #define MVOP_REG_BASE 0x1400 // 0x1400 - 0x14FF 113 #define MVOP_SUB_REG_BASE 0x3D00 // 0x1300 - 0x13FF 114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 115 #define CLKGEN1_REG_BASE 0x3300 //chiptop CLKGEN01 116 #define MFDEC_REG_BASE 0x00012200 //mfdec bank 117 118 //------------------------------------------------------------------------------ 119 // MVOP Reg 120 //------------------------------------------------------------------------------ 121 #define VOP_FRAME_VCOUNT (MVOP_REG_BASE + 0x00) 122 #define VOP_FRAME_HCOUNT (MVOP_REG_BASE + 0x02) 123 #define VOP_VB0_STR (MVOP_REG_BASE + 0x04) 124 #define VOP_VB0_END (MVOP_REG_BASE + 0x06) 125 #define VOP_VB1_STR (MVOP_REG_BASE + 0x08) 126 #define VOP_VB1_END (MVOP_REG_BASE + 0x0A) 127 #define VOP_TF_STR (MVOP_REG_BASE + 0x0C) 128 #define VOP_BF_STR (MVOP_REG_BASE + 0x0E) 129 #define VOP_HACT_STR (MVOP_REG_BASE + 0x10) 130 #define VOP_IMG_HSTR (MVOP_REG_BASE + 0x12) 131 #define VOP_IMG_VSTR0 (MVOP_REG_BASE + 0x14) 132 #define VOP_IMG_VSTR1 (MVOP_REG_BASE + 0x16) 133 #define VOP_TF_VS (MVOP_REG_BASE + 0x18) 134 #define VOP_BF_VS (MVOP_REG_BASE + 0x1A) 135 136 137 ///TOP field Vsync start line number to MVD 138 #define VOP_TF_VS_MVD (MVOP_REG_BASE + 0x1C) //u3 new 139 ///Bottom field Vsync start line number to MVD 140 #define VOP_BF_VS_MVD (MVOP_REG_BASE + 0x1E) //u3 new 141 142 #define VOP_FSYNC_EN BIT4 //frame sync enable 143 #define VOP_CTRL0 (MVOP_REG_BASE + 0x22) 144 #define VOP_EXTFLD_EN BIT6 145 146 #define VOP_FLIP_UV BIT0 147 #define VOP_FLIP_YC BIT1 148 #define VOP_FLD_INV BIT2 149 #define VOP_OFLD_INV BIT4 150 #define VOP_CCIR_MD BIT5 151 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd) 152 #define VOP_MVD_VS_SEL BIT7 153 #define VOP_CTRL1 (MVOP_REG_BASE + 0x23) 154 155 #define VOP_TST_IMG (MVOP_REG_BASE + 0x24) 156 #define VOP_UV_SWAP BIT4 157 #define VOP_SC_VS_INV BIT7 158 159 #define VOP_U_PAT (MVOP_REG_BASE + 0x26) 160 161 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4) 162 //DMA FIFO threshold 163 //= reg_dma_thd x 2 (reg_miu128b=1) 164 //= reg_dma_thd x 4 (reg_miu128b=0) 165 #define VOP_BURST_ST_SEL BIT7 166 //Timing to calculate burst length (only valid when reg_burst_ext = all) 167 //0: at mi2dc_rdy; 1: at dc2mi_rdy 168 #define VOP_DMA0 (MVOP_REG_BASE + 0x28) //t3 new 169 170 #define VOP_BURST_EXT (BIT0|BIT1|BIT2) 171 //DMA burst length 172 //0: 4 (reg_miu128b=1), 8 (reg_miu128b=0) 173 //1: 8 (reg_miu128b=1), 16 (reg_miu128b=0) 174 //2: 16 (reg_miu128b=1), 32 (reg_miu128b=0) 175 //3: 24 (reg_miu128b=1), 48 (reg_miu128b=0) 176 //4: 32 (reg_miu128b=1), 64 (reg_miu128b=0) 177 //5: 48 (reg_miu128b=1), 96 (reg_miu128b=0) 178 //6: 64 (reg_miu128b=1), 128 (reg_miu128b=0) 179 //7: all 180 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold 181 //(assert high priority if data count less then reg_hi_tsh x 8) 182 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority 183 #define VOP_DMA1 (MVOP_REG_BASE + 0x29) //t3 new 184 #define VOP_BURST_CTRL0 (MVOP_REG_BASE + 0x2A) //monaco new 185 #define VOP_BURST_CTRL1 (MVOP_REG_BASE + 0x2B) //monaco new 186 187 #define VOP_DC_STRIP_H (MVOP_REG_BASE + 0x30) 188 #define VOP_SRAM_SD_MASK BIT3 189 #define MFDEC_SRAM_SD_MASK BIT4 190 191 192 #define VOP_INT_MASK (MVOP_REG_BASE + 0x3E) 193 #define VOP_MPG_JPG_SWITCH (MVOP_REG_BASE + 0x40) 194 #define VOP_DRAM_RD_MODE BIT5 195 #define VOP_DC_STRIP (MVOP_REG_BASE + 0x41) 196 #define VOP_JPG_YSTR0_L (MVOP_REG_BASE + 0x42) 197 #define VOP_JPG_YSTR0_H (MVOP_REG_BASE + 0x44) 198 #define VOP_JPG_UVSTR0_L (MVOP_REG_BASE + 0x46) 199 #define VOP_JPG_UVSTR0_H (MVOP_REG_BASE + 0x48) 200 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24) 201 202 #define VOP_JPG_HSIZE (MVOP_REG_BASE + 0x4A) 203 #define VOP_JPG_VSIZE (MVOP_REG_BASE + 0x4C) 204 205 #define VOP_LOAD_REG BIT0 //load new value into active registers 0x20-0x26 206 #define VOP_TILE_FORMAT BIT1 //0: 8x32, 1: 16x32 207 #define VOP_BUF_DUAL BIT2 208 #define VOP_FORCELOAD_REG BIT4 //force load registers 209 #define VOP_REG_WR (MVOP_REG_BASE + 0x4E) 210 211 #define VOP_INPUT_SWITCH0 (MVOP_REG_BASE + 0x50) 212 #define VOP_TILE_32x32 BIT5 213 #define VOP_R2_WISHBONE BIT6 214 #define EVD_ENABLE BIT7 215 216 #define VOP_INPUT_SWITCH1 (MVOP_REG_BASE + 0x51) 217 #define VOP_MVD_EN BIT0 //t8 new 218 #define VOP_H264_PUREY BIT1 219 //#define VOP_RVD_EN BIT2 //a3: removed 220 #define VOP_HVD_EN BIT3 221 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1 222 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select 223 224 #define VOP_RAMAP_LUMA_VAL 0x1f 225 #define VOP_RAMAP_LUMA_EN BIT7 226 #define VOP_RAMAP_LUMA (MVOP_REG_BASE + 0x52) 227 //u3 new: Luma range mapping for VC1 (value = 8~16) 228 229 #define VOP_RAMAP_CHROMA_VAL 0x1f 230 #define VOP_RAMAP_CHROMA_EN BIT7 231 #define VOP_RAMAP_CHROMA (MVOP_REG_BASE + 0x53) 232 //u3 new: Chroma range mapping for VC1 (value = 8~16) 233 234 // [T3 new 235 #define VOP_DEBUG_2A (MVOP_REG_BASE + 0x54) //2-byte 236 #define VOP_DEBUG_2B (MVOP_REG_BASE + 0x56) 237 #define VOP_DEBUG_2B_H (MVOP_REG_BASE + 0x57) 238 #define VOP_SEND_DATA_FLAG BIT7 239 #define VOP_DEBUG_2C (MVOP_REG_BASE + 0x58) 240 #define VOP_DEBUG_2D (MVOP_REG_BASE + 0x5A) 241 #define VOP_DEBUG_2D_H (MVOP_REG_BASE + 0x5B) 242 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4) 243 #define VOP_DEBUG_2E (MVOP_REG_BASE + 0x5C) 244 245 #define VOP_UF BIT0 //buf underflow 246 #define VOP_OF BIT1 //buf overflow 247 #define VOP_DEBUG_2F_L (MVOP_REG_BASE + 0x5E) 248 249 #define VOP_BIST_FAIL BIT0 //YUV fifo bist fail 250 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select 251 #define VOP_DEBUG_2F_H (MVOP_REG_BASE + 0x5F) 252 // ] 253 254 #define VOP_UV_SHIFT (MVOP_REG_BASE + 0x60) 255 256 #define VOP_GCLK_MIU_ON BIT2 //clk_miu use 0: free-run clock; 1: gated clock 257 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock 258 #define VOP_GCLK (MVOP_REG_BASE + 0x60) //u3 new 259 260 #define VOP_MIU_IF (MVOP_REG_BASE + 0x60) 261 #define VOP_MIU_128BIT BIT4 //MIU bus use 0: 64bit 1:128bit 262 #define VOP_MIU_128B_I64 BIT5 263 #define VOP_MIU_REQ_DIS BIT6 264 265 #define VOP_MIU_BUS (MVOP_REG_BASE + 0x60) //t3 new 266 #define VOP_FD_MASK (MVOP_REG_BASE + 0x61) //kappa new 267 #define VOP_FD_MASK_CLR BIT2 268 #define VOP_FD_MASK_INV BIT3 269 270 #define VOP_MIU_SEL (MVOP_REG_BASE + 0x61) //kaiser new 271 #define VOP_MSB_MIU_DIFF BIT0 272 #define VOP_LSB_MIU_DIFF BIT1 273 #define VOP_MSB_BUF0_MIU_SEL (BIT4|BIT5) // Y miu select: miu0~3 = 0x0~0x3 274 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3 275 276 #define VOP_JPG_YSTR1_L (MVOP_REG_BASE + 0x62) 277 #define VOP_JPG_YSTR1_H (MVOP_REG_BASE + 0x64) 278 #define VOP_JPG_UVSTR1_L (MVOP_REG_BASE + 0x66) 279 #define VOP_JPG_UVSTR1_H (MVOP_REG_BASE + 0x68) 280 281 #define VOP_SYNC_FRAME_V (MVOP_REG_BASE + 0x6A) 282 #define VOP_SYNC_FRAME_H (MVOP_REG_BASE + 0x6C) 283 284 #define VOP_INFO_FROM_CODEC_L (MVOP_REG_BASE + 0x70) 285 #define VOP_INFO_FROM_CODEC_BASE_ADDR (BIT0) //base address 286 #define VOP_INFO_FROM_CODEC_PITCH (BIT1) //pitch 287 #define VOP_INFO_FROM_CODEC_SIZE (BIT2) //size 288 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence 289 #define VOP_INFO_FROM_CODEC_FIELD (BIT4) //field 290 #define VOP_INFO_FROM_CODEC_RANGE_MAP (BIT5) //range map 291 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode 292 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format 293 294 #define VOP_INFO_FROM_CODEC_H (MVOP_REG_BASE + 0x71) 295 #define VOP_INFO_FROM_CODEC_DUAL_BUFF (BIT0) //dual buffer flag 296 #define VOP_INFO_FROM_CODEC_BPIC_REDUCT (BIT1) //bpic reduction 297 #define VOP_INFO_FROM_CODEC_MIU_BUF0_SEL (BIT4) //MSB miu select 298 #define VOP_INFO_FROM_CODEC_MIU_BUF1_SEL (BIT5) //LSB miu select 299 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable 300 #define VOP_INFO_FROM_CODEC_DS_IDX (BIT7) //dynamic scaling index 301 302 #define VOP_EVD_10B_EN (MVOP_REG_BASE + 0x73) 303 #define VOP_INT_TYPE (MVOP_REG_BASE + 0x73) 304 #define VOP_EVD_INT_SEP (BIT0) 305 #define VOP_EVD_10B_Y_EN (BIT1) //Enable EVD Y 10 bits mode 306 #define VOP_EVD_10B_UV_EN (BIT2) //Enable EVD UV 10 bits mode 307 308 #define VOP_NOT_WAIT_READ_DATA (MVOP_REG_BASE + 0x72) 309 #define VOP_NOT_WAIT_RDLAT (BIT0|BIT1|BIT2) 310 311 #define VOP_MIU_SEL_LSB (MVOP_REG_BASE + 0x75) 312 #define VOP_LSB_BUF0_MIU_SEL (BIT4|BIT5) // LSB Y miu select: miu0~3 = 0x0~0x3 313 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3 314 315 #define VOP_MIRROR_CFG (MVOP_REG_BASE + 0x76) 316 #define VOP_MIRROR_CFG_VEN (BIT0) //vertical mirror enable 317 #define VOP_MIRROR_CFG_HEN (BIT1) //horizontal mirror enable 318 #define VOP_FIELD_FROM_ADDR (BIT3) //decide top or bot by diu addr 319 #define VOP_HW_FLD_BASE (BIT5) //Hardware calculate field jump base address 320 #define VOP_MASK_BASE_LSB (BIT7) //mask LSB of base address from Codec (always get top field base address) 321 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7) 322 323 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) 324 #define VOP_REF_SELF_FLD (BIT1) //source field flag set by internal timing generator 325 #define VOP_HK_MASK (BIT4) // HSK show back ground as vdec not ready 326 327 #define VOP_MULTI_WIN_CFG0 (MVOP_REG_BASE + 0x78) 328 #define VOP_LR_BUF_MODE (BIT0) //3D L/R dual buffer mode 329 #define VOP_P2I_MODE (BIT1) //progressive input, interlace output 330 //to SC vsync is twice of to MVD vsync 331 #define VOP_LR_LA_OUT (BIT2) //3D L/R dual buffer line alternative output 332 #define VOP_LR_LA2SBS_OUT (BIT3) //3D L/R dual buffer line alternative read, side-by-side output 333 #define VOP_LR_DIFF_SIZE (BIT7) //3D L/R dual buffer with difference size 334 335 #define VOP_RGB_FMT (MVOP_REG_BASE + 0x79) 336 #define VOP_RGB_FMT_565 (BIT0) //RGB 565 337 #define VOP_RGB_FMT_888 (BIT1) //RGB 888 338 #define VOP_RGB_FMT_SEL (BIT0 | BIT1) //RGB format selection 339 340 #define VOP_REG_DUMMY_3D_0 (MVOP_REG_BASE + 0x7A) 341 #define VOP_REG_DUMMY_3D_1 (MVOP_REG_BASE + 0x7B) 342 #define VOP_RGB_FILED_BYPASS (BIT3) // TOP/BOT bypass to xc 343 #define VOP_REG_DUMMY (MVOP_REG_BASE + 0x7B) 344 #define VOP_32x32_WB (BIT6) //32x32 from vdec: Reg_evd_en = 0 + reg_diu_sel = 1 345 #define VOP_420_BW_SAVE (BIT7) //420 bw saving mode 346 347 #define VOP_HANDSHAKE (MVOP_REG_BASE + 0x7C) 348 #define VOP_HANDSHAKE_MODE (BIT0) //Handshake interface output 349 #define VOP_TRIG_FROM_XC (BIT1) //Trigger start from Scaler 350 #define VOP_VSUNC_FROM_XC (BIT2) //Vsync from Scaler 351 #define VOP_HANDSHAKE_ENABLE (BIT0 | BIT1 | BIT2) 352 353 #define VOP_REG_STRIP_ALIGN (MVOP_REG_BASE + 0x7E) 354 #define VOP_REG_WEIGHT_CTRL (MVOP_REG_BASE + 0x7E) 355 #define VOP_REG_422_OUT_EN (MVOP_REG_BASE + 0x7F) //BIT 8 356 #define VOP_REG_FD_MASK_SEL (MVOP_REG_BASE + 0x7F) //BIT 8 357 #define VOP_REG_FRAME_RST (MVOP_REG_BASE + 0x7E) //BIT15 358 #define VOP_REG_CSC_EN (MVOP_REG_BASE + 0x7E) //BIT15 359 360 #define VOP_REG_CROP_HSTART (MVOP_REG_BASE + 0x80) 361 #define VOP_REG_CROP_VSTART (MVOP_REG_BASE + 0x82) 362 #define VOP_REG_CROP_HSIZE (MVOP_REG_BASE + 0x84) 363 #define VOP_REG_CROP_VSIZE (MVOP_REG_BASE + 0x86) 364 #define VOP_REG_SINGLE_3D_L (MVOP_REG_BASE + 0x88) 365 #define VOP_FORCE_SKIP BIT2 366 #define VOP_SKIP_SIZE_LVIEW (BIT4 | BIT5 | BIT6 | BIT7) 367 #define VOP_REG_SINGLE_3D_H (MVOP_REG_BASE + 0x89) 368 #define VOP_SKIP_SIZE_RVIEW (BIT0 | BIT1 | BIT2 | BIT3) 369 #define VOP_REG_ENABLE_SKIP (MVOP_REG_BASE + 0x8D) 370 #define VOP_SKIP_LVIEW BIT6 371 #define VOP_SKIP_RVIEW BIT7 372 373 #define VOP_REG_MASK (MVOP_REG_BASE + 0x8E) 374 #define VOP_LSB_REQ_MASK (BIT0 | BIT1) //RGB format selection 375 376 #define VOP_LSB_YSTR0_L (MVOP_REG_BASE + 0x94) 377 #define VOP_LSB_YSTR0_H (MVOP_REG_BASE + 0x96) 378 #define VOP_LSB_UVSTR0_L (MVOP_REG_BASE + 0x98) 379 #define VOP_LSB_UVSTR0_H (MVOP_REG_BASE + 0x9A) 380 #define VOP_LSB_YSTR1_L (MVOP_REG_BASE + 0x9C) 381 #define VOP_LSB_YSTR1_H (MVOP_REG_BASE + 0x9E) 382 #define VOP_LSB_UVSTR1_L (MVOP_REG_BASE + 0xA0) 383 #define VOP_LSB_UVSTR1_H (MVOP_REG_BASE + 0xA2) 384 385 #define VOP_DC_STRIP_LSB (MVOP_REG_BASE + 0xA4) 386 387 #define VOP_REG_4K2K_2P (MVOP_REG_BASE + 0xA6) 388 #define VOP_4K2K_2P BIT1 389 390 #define VOP_REG_MFDEC_0_L (MVOP_REG_BASE + 0xA8) 391 #define VOP_MFDEC_EN BIT0 392 #define VOP_MFDEC_SEL BIT1 393 #define VOP_MF0_BURST (BIT4 | BIT5) 394 #define VOP_MF1_BURST (BIT6 | BIT7) 395 396 #define VOP_REG_MFDEC_2_L (MVOP_REG_BASE + 0xAC) 397 #define VOP_BIT_MIU_SEL (BIT2 | BIT3) 398 #define VOP_UNCOMP_MODE (BIT4 | BIT5) 399 #define VOP_MF_FROM_WB BIT6 400 401 #define VOP_REG_BITLEN_ADD_L (MVOP_REG_BASE + 0xAE) 402 #define VOP_REG_BITLEN_ADD_H (MVOP_REG_BASE + 0xB0) 403 #define VOP_REG_BW_SAVE (MVOP_REG_BASE + 0xC0) 404 #define VOP_420_BW_SAVE_EX BIT0 405 406 #define VOP_REG_DUMMY_5D (MVOP_REG_BASE + 0xBA) 407 #define VOP_SRAM_CLK_AUTO BIT2 408 #define VOP_LSB_422_BW_SAVE BIT4 409 410 #define VOP_REG_MFDEC_5E (MVOP_REG_BASE + 0xBC) 411 #define VOP_BITLEN_SHT BIT0 412 #define VOP_REG_MFDEC_BIT_PITCH (MVOP_REG_BASE + 0xBD) 413 #define VOP_REG_BLK_VCNT_L (MVOP_REG_BASE + 0xC4) 414 #define VOP_REG_BLK_VCNT_H (MVOP_REG_BASE + 0xC5) 415 416 #define VOP_REG_MRQ (MVOP_REG_BASE + 0xC9) 417 #define VOP_LST_CTRL_DCTOP (BIT3 | BIT4 | BIT5) 418 #define VOP_MRQ_EN BIT6 419 //------------------------------------------------------------------------------ 420 // mfdec Reg 421 //------------------------------------------------------------------------------ 422 423 #define REG_MF_BASIC_L (MFDEC_REG_BASE + 0x00) 424 #define MF_MFDEC_EN BIT0 425 #define MF_UNCOMP_MODE BIT5 426 427 #define REG_MF_BASIC_H (MFDEC_REG_BASE + 0x01) 428 #define MF_RIU_MODE BIT4 429 #define MF_RIU1_MODE BIT5 430 431 #define REG_MF_MIU (MFDEC_REG_BASE + 0x02) 432 #define MF_LUMA_MIU (BIT0 | BIT1) 433 #define MF_CHROMA_MIU (BIT2 | BIT3) 434 #define MF_BITLEN_MIU (BIT4 | BIT5) 435 436 #define REG_MF_FB_WIDTH (MFDEC_REG_BASE + 0x08) 437 #define REG_MF_FB_HEIGHT (MFDEC_REG_BASE + 0x0A) 438 #define REG_MF_FB_PITCH (MFDEC_REG_BASE + 0x0C) 439 440 #define REG_MF_BT_PITCH (MFDEC_REG_BASE + 0x0E) 441 442 #define REG_MF_BT_ADDR_L (MFDEC_REG_BASE + 0x18) 443 #define REG_MF_BT_ADDR_H (MFDEC_REG_BASE + 0x1A) 444 445 //// huffman table //// 446 #define REG_MF_CW_LEN2(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x20<<1) ) 447 #define MF_CW_LEN2_MASK BMASK(11:0) 448 449 #define REG_MF_CW_LEN3(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x21<<1) ) 450 #define MF_CW_LEN3_MASK BMASK(11:0) 451 452 #define REG_MF_CW_LEN4(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x22<<1) ) 453 #define MF_CW_LEN4_MASK BMASK(11:0) 454 455 #define REG_MF_CW_LEN5(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x23<<1) ) 456 #define MF_CW_LEN5_MASK BMASK(11:0) 457 458 #define REG_MF_CW_BASE(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x24<<1) ) 459 #define MF_CW_BASE BMASK(11:0) 460 461 #define REG_MF_CW_MAX(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x25<<1) ) 462 #define MF_CW_MAX BMASK(11:0) 463 464 #define REG_MF_SYMB_BASE(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x26<<1) ) 465 #define MF_SYMB_BASE BMASK(4:0) 466 #define MF_SYMB_MAX BMASK(12:8) 467 468 #define REG_MF_HUF_TAB(id) (MFDEC_REG_BASE + ((0x40<<1)*id) + (0x27<<1) ) 469 470 #define MFEDC_TABLE_INDEX_NUM 48 471 472 //------------------------------------------------------------------------------ 473 // chip top 474 //------------------------------------------------------------------------------ 475 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98) 476 #define CKG_DC0_GATED BIT0 477 #define CKG_DC0_INVERT BIT1 478 #define CKG_DC0_MASK (BIT4 | BIT3 | BIT2) //select clk src 479 #define CKG_DC0_SYNCHRONOUS (0 << 2) 480 #define CKG_DC0_FREERUN (1 << 2) 481 #define CKG_DC0_320MHZ (2 << 2) 482 #define CKG_DC0_108MHZ (3 << 2) 483 #define CKG_DC0_123MHZ (4 << 2) //as default 484 #define CKG_DC0_144MHZ (5 << 2) 485 #define CKG_DC0_160MHZ (6 << 2) 486 #define CKG_DC0_192MHZ (7 << 2) 487 488 489 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE) 490 #define CKG_DC0_SRAM (BIT3 | BIT2 | BIT1 | BIT0) 491 #define CKG_DC1_SRAM (BIT7 | BIT6 | BIT5 | BIT4) 492 493 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0xAF) 494 #define CKG_SUB_DC0_GATED BIT0 495 #define CKG_SUB_DC0_INVERT BIT1 496 #define CKG_SUB_DC0_MASK (BIT4 | BIT3 | BIT2) //select clk src 497 #define CKG_SUB_DC0_SYNCHRONOUS (0 << 2) 498 #define CKG_SUB_DC0_FREERUN (1 << 2) 499 #define CKG_SUB_DC0_320MHZ (2 << 2) 500 #define CKG_SUB_DC0_108MHZ (3 << 2) 501 #define CKG_SUB_DC0_123MHZ (4 << 2) //as default 502 #define CKG_SUB_DC0_144MHZ (5 << 2) 503 #define CKG_SUB_DC0_160MHZ (6 << 2) 504 #define CKG_SUB_DC0_192MHZ (7 << 2) 505 506 // For check stc cw 507 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel 508 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x0B) //reg_stc1_cw_sel 509 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C) 510 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E) 511 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x10) 512 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x12) 513 #define REG_TSP_CLK (CHIP_REG_BASE + 0x54) //reg_ckg_tsp 514 515 //For main mvop 516 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0xE0) 517 #define UPDATE_DC0_FREERUN_CW BIT0 518 #define UPDATE_DC0_SYNC_CW BIT1 519 #define REG_DC0_FREERUN_CW_L (CHIP_REG_BASE + 0xE4) 520 #define REG_DC0_FREERUN_CW_H (CHIP_REG_BASE + 0xE6) 521 #define REG_DC0_NUM (CHIP_REG_BASE + 0xE8) 522 #define REG_DC0_DEN (CHIP_REG_BASE + 0xEA) 523 524 //For sub mvop 525 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) 526 #define UPDATE_DC1_FREERUN_CW BIT0 527 #define UPDATE_DC1_SYNC_CW BIT1 528 #define REG_DC1_FREERUN_CW_L (CHIP_REG_BASE + 0xEC) 529 #define REG_DC1_FREERUN_CW_H (CHIP_REG_BASE + 0xEE) 530 #define REG_DC1_NUM (CHIP_REG_BASE + 0xF0) 531 #define REG_DC1_DEN (CHIP_REG_BASE + 0xF2) 532 533 //------------------------------------------------------------------------------ 534 // SC_FE 535 //------------------------------------------------------------------------------ 536 #if 0 537 #define REG_MIU_SEL_FROM_IP (SC_FE_REG_BASE + 0x22) 538 #define MVOP_MIU_IP_SEL BIT2 539 #define MFDEC0_MIU_IP_SEL BIT3 540 #define MFDEC1_MIU_IP_SEL BIT4 541 #endif 542 //----------------------------------------------------------------------------- 543 // CLK_GEN1 544 //----------------------------------------------------------------------------- 545 #define REG_CKG_FBDEC (CLKGEN1_REG_BASE + 0x4A) 546 #define VOP_SEL_CLK_432 (BIT0 | BIT1 | BIT2 | BIT3) 547 548 #endif // _REG_VOP_H_ 549