1 /* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 13 #define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0) 14 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000) 15 16 /* 17 * SMD region assignment 18 * AP accesses devices located in SMD via AP SMD region starting from 19 * 0x4000_0000. 20 */ 21 /* CNTControl frame 64KB */ 22 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0x40000000) 23 /* CNTRead frame 64KB */ 24 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0x40010000) 25 /* SI MHU regions 6MB in total */ 26 #define SI_MHU_REGION_BASE UL(0x40020000) 27 /* AP MHU regions 768KB in total */ 28 #define RDASPEN_CSS_AP_RSE_SECURE_MHU_BASE UL(0x40680000) 29 30 /* AP access AP_REFLCK generic timers via Peripheral Block */ 31 #define PLAT_ARM_SYS_TIMCTL_BASE UL(0x1A810000) 32 #define PLAT_ARM_SYS_CNT_BASE_S UL(0x1A820000) 33 #define PLAT_ARM_SYS_CNT_BASE_NS UL(0x1A830000) 34 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 35 36 #include <plat/arm/common/arm_def.h> 37 #include <plat/arm/css/common/css_def.h> 38 #include <plat/common/common_def.h> 39 40 /* Set default topology value if not passed from platform's makefile */ 41 #ifndef PLATFORM_CORE_COUNT 42 #define PLATFORM_CORE_COUNT U(16) 43 #endif /* PLATFORM_CORE_COUNT */ 44 45 #if (PLATFORM_CORE_COUNT > 16) || (PLATFORM_CORE_COUNT < 1) 46 #error "Invalid number of platform's cores was passed." 47 #endif /* 1 <= PLATFORM_CORE_COUNT <= 16 */ 48 49 #if (PLATFORM_CORE_COUNT <= 4) 50 #define PLATFORM_CLUSTER_0_CORE_COUNT U(PLATFORM_CORE_COUNT) 51 #define PLATFORM_CLUSTER_1_CORE_COUNT U(0) 52 #define PLATFORM_CLUSTER_2_CORE_COUNT U(0) 53 #define PLATFORM_CLUSTER_3_CORE_COUNT U(0) 54 55 #else /* PLATFORM_CORE_COUNT <= 4 */ 56 #define PLATFORM_CLUSTER_0_CORE_COUNT U(4) 57 58 #if (PLATFORM_CORE_COUNT <= 8) 59 #define PLATFORM_CLUSTER_1_CORE_COUNT U(PLATFORM_CORE_COUNT - 4) 60 #define PLATFORM_CLUSTER_2_CORE_COUNT U(0) 61 #define PLATFORM_CLUSTER_3_CORE_COUNT U(0) 62 63 #else /* PLATFORM_CORE_COUNT <= 8 */ 64 #define PLATFORM_CLUSTER_1_CORE_COUNT U(4) 65 66 #if (PLATFORM_CORE_COUNT <= 12) 67 #define PLATFORM_CLUSTER_2_CORE_COUNT U(PLATFORM_CORE_COUNT - 8) 68 #define PLATFORM_CLUSTER_3_CORE_COUNT U(0) 69 70 #else /* PLATFORM_CORE_COUNT <= 12 */ 71 #define PLATFORM_CLUSTER_2_CORE_COUNT U(4) 72 #define PLATFORM_CLUSTER_3_CORE_COUNT U(PLATFORM_CORE_COUNT - 12) 73 74 #endif /* PLATFORM_CORE_COUNT <= 12 */ 75 #endif /* PLATFORM_CORE_COUNT <= 8 */ 76 #endif /* PLATFORM_CORE_COUNT <= 4 */ 77 78 #define PLAT_MAX_CPUS_PER_CLUSTER U(4) 79 #define PLAT_MAX_PE_PER_CPU U(1) 80 #define PLAT_ARM_CLUSTER_COUNT ((PLATFORM_CORE_COUNT + \ 81 PLAT_MAX_CPUS_PER_CLUSTER - 1) / \ 82 PLAT_MAX_CPUS_PER_CLUSTER) 83 84 #define PLATFORM_STACK_SIZE UL(0x1000) 85 86 /* BL1 is not supported */ 87 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x0) 88 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x0) 89 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x0) 90 91 /* USE_ROMLIB is not supported */ 92 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) 93 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) 94 95 #define PLAT_ARM_MAX_BL31_SIZE UL(0xED000) 96 97 #undef ARM_DRAM2_BASE 98 #define ARM_DRAM2_BASE ULL(0x20000000000) 99 #undef ARM_DRAM2_SIZE 100 #define ARM_DRAM2_SIZE SZ_2G 101 102 /* 103 * MHU for SCMI communication with SCP on Safety Island CL0 104 * Offset to SI_MHU_REGION_BASE: 0x0008_0000. 105 */ 106 #define PLAT_CSS_MHU_BASE UL(0x400A0000) 107 108 /* UART Related Constants */ 109 #define SOC_CSS_SEC_UART_BASE UL(0x1A410000) 110 #define SOC_CSS_UART_SIZE SZ_64K 111 #define SOC_CSS_UART_CLK_IN_HZ UL(24000000) 112 #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE 113 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 114 #define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE 115 #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 116 #define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE 117 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 118 119 /* 256 TB */ 120 #define SZ_256T (1ULL << 48) 121 /* Physical and virtual address space limits for MMU */ 122 #define PLAT_PHY_ADDR_SPACE_SIZE SZ_256T 123 #define PLAT_VIRT_ADDR_SPACE_SIZE SZ_256T 124 125 #define PLAT_ARM_GICD_BASE UL(0x20000000) 126 #define PLAT_ARM_GICR_BASE UL(0x200C0000) 127 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 128 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 129 130 /* Secure Watchdog Constants */ 131 #define SBSA_SECURE_WDOG_BASE UL(0x1A460000) 132 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 133 134 /* Virtual address used by dynamic mem_protect for chunk_base */ 135 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) 136 137 /* SCMI Related Constants */ 138 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 139 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 140 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 141 142 #define MAX_IO_DEVICES U(3) 143 #define MAX_IO_HANDLES U(4) 144 145 #if IMAGE_BL2 146 #define PLAT_ARM_MMAP_ENTRIES U(9) 147 #elif IMAGE_BL31 148 #define PLAT_ARM_MMAP_ENTRIES U(8) 149 #endif 150 #define MAX_XLAT_TABLES U(9) 151 152 #define PLAT_FW_CONFIG_MAX_SIZE (ARM_FW_CONFIG_LIMIT - \ 153 ARM_FW_CONFIG_BASE) 154 #define PLAT_FW_CONFIG_BASE ARM_FW_CONFIG_BASE 155 156 /* 157 * Map peripherals till GIC regions and devices in Rest of System 158 */ 159 #define RDASPEN_DEVICE_BASE UL(0x10000000) 160 #define RDASPEN_DEVICE_SIZE UL(0x28000000) 161 #define RDASPEN_MAP_DEVICE MAP_REGION_FLAT(RDASPEN_DEVICE_BASE, \ 162 RDASPEN_DEVICE_SIZE, \ 163 MT_DEVICE | MT_RW | \ 164 MT_SECURE) 165 166 /* Flash in Rest of the System */ 167 #define EXT_FLASH_BASE UL(0x38000000) 168 #define EXT_FLASH_SIZE SZ_128M 169 #define EXT_FLASH_BLOCK_SIZE SZ_256K 170 #define PLAT_ARM_FLASH_IMAGE_BASE EXT_FLASH_BASE 171 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (EXT_FLASH_SIZE - \ 172 EXT_FLASH_BLOCK_SIZE) 173 174 #define RDASPEN_MAP_EXTERNAL_FLASH MAP_REGION_FLAT(EXT_FLASH_BASE, \ 175 PLAT_ARM_FLASH_IMAGE_MAX_SIZE, \ 176 MT_DEVICE | MT_RO | \ 177 MT_SECURE) 178 179 /* SMD region */ 180 #define RDASPEN_SMD_REGION_BASE UL(0x40000000) 181 #define RDASPEN_SMD_REGION_SIZE UL(0x10000000) 182 #define RDASPEN_MAP_SMD_REGION MAP_REGION_FLAT(RDASPEN_SMD_REGION_BASE, \ 183 RDASPEN_SMD_REGION_SIZE, \ 184 MT_DEVICE | MT_RW | \ 185 MT_SECURE) 186 187 /* Trusted OS Config region */ 188 #define PLAT_TOS_FW_CONFIG_BASE UL(0x1800) 189 #define PLAT_TOS_FW_CONFIG_SIZE UL(0x1000) 190 191 /* SPMC region */ 192 #define PLAT_ARM_SPMC_BASE UL(0xFFC00000) 193 #define PLAT_ARM_SPMC_SIZE UL(0x00400000) 194 195 /* 196 * NS DRAM 197 * DRAM1 consists of Non-secure partition and SPMC Secure partition. 198 */ 199 #define NS_DRAM_SIZE (ARM_DRAM1_SIZE - PLAT_ARM_SPMC_SIZE) 200 201 #define RDASPEN_MAP_NS_DRAM1 MAP_REGION_FLAT(ARM_DRAM1_BASE, \ 202 NS_DRAM_SIZE, \ 203 MT_MEMORY | MT_RW | \ 204 MT_NS) 205 206 #define RDASPEN_MAP_NS_DRAM2 MAP_REGION_FLAT(ARM_DRAM2_BASE, \ 207 ARM_DRAM2_SIZE, \ 208 MT_MEMORY | MT_RW | \ 209 MT_NS) 210 211 /* Secure DRAM */ 212 #define RDASPEN_MAP_S_DRAM MAP_REGION_FLAT(PLAT_ARM_SPMC_BASE, \ 213 PLAT_ARM_SPMC_SIZE, \ 214 MT_MEMORY | MT_RW | \ 215 MT_SECURE) 216 217 /* load address of DTB */ 218 #define PLAT_HW_CONFIG_DTB_BASE ARM_DRAM1_BASE 219 #define PLAT_ARM_HW_CONFIG_SIZE UL(0x8000) 220 221 /* 222 * PSCI memory protect definitions: 223 * This variable is stored in a non-secure flash because some ARM reference 224 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 225 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 226 */ 227 #define PLAT_ARM_MEM_PROT_ADDR (EXT_FLASH_BASE + \ 228 EXT_FLASH_SIZE - \ 229 EXT_FLASH_BLOCK_SIZE) 230 231 /* Map mem_protect flash region with read and write permissions */ 232 #define RDASPEN_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 233 EXT_FLASH_BLOCK_SIZE, \ 234 MT_DEVICE | MT_RW | \ 235 MT_SECURE) 236 237 /* Non-volatile counters */ 238 #define RDASPEN_TRUSTED_NVCTR_BASE UL(0x32030000) 239 #define RDASPEN_TRUSTED_NVCTR_SIZE UL(0x10000) 240 #define TFW_NVCTR_BASE RDASPEN_TRUSTED_NVCTR_BASE 241 #define TFW_NVCTR_SIZE 4 242 #define NTFW_CTR_BASE (RDASPEN_TRUSTED_NVCTR_BASE + 0x0004) 243 #define NTFW_CTR_SIZE 4 244 245 #define RDASPEN_MAP_TRUSTED_NVCTR MAP_REGION_FLAT(RDASPEN_TRUSTED_NVCTR_BASE, \ 246 RDASPEN_TRUSTED_NVCTR_SIZE, \ 247 MT_DEVICE | MT_RO | \ 248 MT_SECURE) 249 250 /* 125 MHz REFCLK to System Counter */ 251 #define SYS_COUNTER_FREQ_IN_TICKS UL(125000000) 252 253 /* The index of the primary CPU */ 254 #define RDASPEN_PRIMARY_CPU 0x0 255 256 /* 257 * In the current implementation, the RoT Service request that requires the 258 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 259 * maximum required buffer size is calculated based on the platform-specific 260 * needs of this request. 261 */ 262 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE UL(0x1000) 263 264 /******************************************************************************* 265 * MHUv3 related definitions 266 ******************************************************************************/ 267 268 /* AP - RSE MHUv3 */ 269 #define MHU_V3_MBX_FRAME_OFFSET UL(0x30000) 270 271 /* MHUv3 Postbox and Mailbox register frame base */ 272 #define AP_RSE_SECURE_MHU_V3_PBX RDASPEN_CSS_AP_RSE_SECURE_MHU_BASE 273 #define AP_RSE_SECURE_MHU_V3_MBX RDASPEN_CSS_AP_RSE_SECURE_MHU_BASE + \ 274 MHU_V3_MBX_FRAME_OFFSET 275 276 /* 277 * In the current implementation, the RoT Service request that requires the 278 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 279 * maximum required buffer size is calculated based on the platform-specific 280 * needs of this request. 281 */ 282 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE UL(0x1000) 283 284 /******************************************************************************* 285 * MHUv3 related definitions 286 ******************************************************************************/ 287 288 /* AP - RSE MHUv3 */ 289 #define MHU_V3_MBX_FRAME_OFFSET UL(0x30000) 290 291 /* MHUv3 Postbox and Mailbox register frame base */ 292 #define AP_RSE_SECURE_MHU_V3_PBX RDASPEN_CSS_AP_RSE_SECURE_MHU_BASE 293 #define AP_RSE_SECURE_MHU_V3_MBX RDASPEN_CSS_AP_RSE_SECURE_MHU_BASE + \ 294 MHU_V3_MBX_FRAME_OFFSET 295 296 #endif /* PLATFORM_DEF_H */ 297