1 /* 2 * Copyright (c) 2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 13 /* These are referenced by arm_def.h #included next, so #define first. */ 14 #define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0) 15 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/common/common_def.h> 19 20 #define PLATFORM_CORE_COUNT U(16) 21 #define PLAT_ARM_CLUSTER_COUNT U(16) 22 #define PLAT_MAX_CPUS_PER_CLUSTER U(1) 23 #define PLAT_MAX_PE_PER_CPU U(1) 24 25 #define PLATFORM_STACK_SIZE UL(0x1000) 26 27 /* BL1 is not supported */ 28 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x0) 29 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x0) 30 31 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000) 32 33 /* USE_ROMLIB is not supported */ 34 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) 35 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) 36 37 /* Defined based on actual binary sizes */ 38 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x0 39 #define PLAT_ARM_MAX_BL2_SIZE 0x20000 40 #define PLAT_ARM_MAX_BL31_SIZE 0x70000 41 42 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 43 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 44 45 #define PLAT_CSS_MHU_BASE UL(0x2A920000) 46 #define PLAT_ARM_NSTIMER_FRAME_ID U(0) 47 48 #define PLAT_ARM_SPMC_BASE UL(0xFFC00000) 49 #define PLAT_ARM_SPMC_SIZE UL(0x00400000) 50 51 #define SOC_CSS_SEC_UART_BASE UL(0x2A410000) 52 #define SOC_CSS_NSEC_UART_BASE UL(0x2A400000) 53 #define SOC_CSS_UART_SIZE UL(0x10000) 54 #define SOC_CSS_UART_CLK_IN_HZ UL(7372800) 55 #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE 56 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 57 #define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE 58 #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 59 #define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE 60 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ 61 62 /* Physical and virtual address space limits for MMU */ 63 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) 64 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) 65 66 /* GIC related constants */ 67 #define PLAT_ARM_GICD_BASE UL(0x30000000) 68 #define PLAT_ARM_GICR_BASE UL(0x301C0000) 69 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 70 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 71 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 72 73 /* Virtual address used by dynamic mem_protect for chunk_base */ 74 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) 75 76 /* Secure Watchdog Constants */ 77 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 78 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 79 80 #define V2M_SYS_LED_SS_SHIFT U(0) 81 #define V2M_SYS_LED_EL_SHIFT U(1) 82 #define V2M_SYS_LED_EC_SHIFT U(3) 83 84 #define V2M_SYS_LED_SS_MASK U(0x01) 85 #define V2M_SYS_LED_EL_MASK U(0x03) 86 #define V2M_SYS_LED_EC_MASK U(0x1f) 87 88 #define V2M_SYSREGS_BASE UL(0x0C010000) 89 #define V2M_SYS_LED U(0x8) 90 91 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 92 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 93 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 94 95 #define MAX_IO_DEVICES U(3) 96 #define MAX_IO_HANDLES U(4) 97 98 #ifdef IMAGE_BL2 99 #define PLAT_ARM_MMAP_ENTRIES U(5) 100 #else 101 #define PLAT_ARM_MMAP_ENTRIES U(6) 102 #endif 103 #define MAX_XLAT_TABLES U(6) 104 105 #define V2M_FLASH0_BASE UL(0x08000000) 106 #define V2M_FLASH0_SIZE UL(0x04000000) 107 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 108 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 109 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 110 111 #define PLAT_FW_CONFIG_MAX_SIZE (ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE) 112 #define PLAT_FW_CONFIG_BASE ARM_FW_CONFIG_BASE 113 114 /* RD1AE-specific memory mappings */ 115 #define RD1AE_EXTERNAL_FLASH MAP_REGION_FLAT(V2M_FLASH0_BASE, \ 116 V2M_FLASH0_SIZE, \ 117 MT_DEVICE | MT_RO | \ 118 MT_SECURE) 119 120 #define RD1AE_MAP_NS_DRAM1 MAP_REGION_FLAT(ARM_DRAM1_BASE, \ 121 ARM_DRAM1_SIZE - PLAT_ARM_SPMC_SIZE, \ 122 MT_MEMORY | MT_RW | \ 123 MT_NS) 124 125 #define RD1AE_MAP_S_DRAM1 MAP_REGION_FLAT(PLAT_ARM_SPMC_BASE, \ 126 PLAT_ARM_SPMC_SIZE, \ 127 MT_MEMORY | MT_RW | MT_SECURE) 128 129 #define RD1AE_DEVICE_BASE (0x20000000) 130 #define RD1AE_DEVICE_SIZE (0x20000000) 131 #define RD1AE_MAP_DEVICE MAP_REGION_FLAT(RD1AE_DEVICE_BASE, \ 132 RD1AE_DEVICE_SIZE, \ 133 MT_DEVICE | MT_RW | \ 134 MT_SECURE) 135 136 #define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000) 137 #define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000) 138 #define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT(SOC_PLATFORM_PERIPH_BASE, \ 139 SOC_PLATFORM_PERIPH_SIZE, \ 140 MT_DEVICE | MT_RW | MT_SECURE) 141 142 /* Non-volatile counters */ 143 #define TRUSTED_NVCTR_BASE_OFFSET UL(0x00E70000) 144 #define TFW_NVCTR_BASE_OFFSET 0x0000 145 #define NTFW_CTR_BASE_OFFSET 0x0004 146 #define SOC_TRUSTED_NVCTR_BASE (SOC_PLATFORM_PERIPH_BASE + TRUSTED_NVCTR_BASE_OFFSET) 147 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + TFW_NVCTR_BASE_OFFSET) 148 #define TFW_NVCTR_SIZE U(4) 149 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + NTFW_CTR_BASE_OFFSET) 150 #define NTFW_CTR_SIZE U(4) 151 152 /******************************************************************************* 153 * Memprotect definitions 154 ******************************************************************************/ 155 /* PSCI memory protect definitions: 156 * This variable is stored in a non-secure flash because some ARM reference 157 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 158 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 159 */ 160 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 161 V2M_FLASH0_SIZE - \ 162 V2M_FLASH_BLOCK_SIZE) 163 164 #endif /* PLATFORM_DEF_H */ 165