1 /* 2 * (C) Copyright 2016 Google, Inc 3 * (C) Copyright 2008-2014 Rockchip Electronics 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_PWM_H 9 #define _ASM_ARCH_PWM_H 10 11 struct rockchip_pwm_regs { 12 unsigned long duty; 13 unsigned long period; 14 unsigned long cntr; 15 unsigned long ctrl; 16 }; 17 18 #define PWM_CTRL_TIMER_EN (1 << 0) 19 #define PWM_CTRL_OUTPUT_EN (1 << 3) 20 21 #define RK_PWM_DISABLE (0 << 0) 22 #define RK_PWM_ENABLE (1 << 0) 23 24 #define PWM_ONE_SHOT (0 << 1) 25 #define PWM_CONTINUOUS (1 << 1) 26 #define RK_PWM_CAPTURE (1 << 2) 27 28 #define PWM_DUTY_POSTIVE (1 << 3) 29 #define PWM_DUTY_NEGATIVE (0 << 3) 30 #define PWM_DUTY_MASK (1 << 3) 31 32 #define PWM_INACTIVE_POSTIVE (1 << 4) 33 #define PWM_INACTIVE_NEGATIVE (0 << 4) 34 #define PWM_INACTIVE_MASK (1 << 4) 35 36 #define PWM_OUTPUT_LEFT (0 << 5) 37 #define PWM_OUTPUT_CENTER (1 << 5) 38 39 #define PWM_LOCK (1 << 6) 40 #define PWM_UNLOCK (0 << 6) 41 42 #define PWM_LP_ENABLE (1 << 8) 43 #define PWM_LP_DISABLE (0 << 8) 44 45 #define PWM_SEL_SCALE_CLK (1 << 9) 46 #define PWM_SEL_SRC_CLK (0 << 9) 47 48 #endif 49