xref: /rk3399_ARM-atf/plat/mediatek/drivers/ptp3/ptp3_plat_common.h (revision 59ac0e5e0c52825092931c0b1ae9743fcf2ce035)
1 /*
2  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PTP3_PLAT_COMMON_H
8 #define PTP3_PLAT_COMMON_H
9 
10 #include <lib/mmio.h>
11 #include <lib/utils_def.h>
12 #include <ptp3_common.h>
13 
14 /* CPU Info */
15 #define NR_PTP3_CFG_CPU			U(8)
16 #define PTP3_CFG_CPU_START_ID_L		U(0)
17 #define PTP3_CFG_CPU_END_ID		U(7)
18 
19 #define NR_PTP3_CFG1_DATA		U(2)
20 #define PTP3_CFG1_MASK			0x3000
21 
22 #define NR_PTP3_CFG2_DATA		U(5)
23 
24 #define PTP3_CFG3_MASK1			0x1180
25 #define PTP3_CFG3_MASK2			0x35C0
26 #define PTP3_CFG3_MASK3			0x3DC0
27 
28 /* Central control */
29 static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = {
30 	{0x0C53A2A0, 0x1000},
31 	{0x0C53A2A4, 0x1000}
32 };
33 
34 static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = {
35 	{0x0C530404, 0x3A1000},
36 	{0x0C530428, 0x13E0408},
37 	{0x0C530434, 0xB22800},
38 	{0x0C53043C, 0x750},
39 	{0x0C530440, 0x0222c4cc}
40 };
41 
42 static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00};
43 
44 #endif /* PTP3_PLAT_COMMON_H */
45