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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvPNL.h 98 /// @brief Panel Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_PNL_H_ 103 #define _DRV_PNL_H_ 104 105 #ifdef _DRVPNL_C_ 106 #define DRV_PNL_INTERFACE 107 #else 108 #define DRV_PNL_INTERFACE extern 109 #endif 110 111 #include "ULog.h" 112 //------------------------------------------------------------------------------------------------- 113 // Driver Capability 114 //------------------------------------------------------------------------------------------------- 115 116 //------------------------------------------------------------------------------------------------- 117 // Macro and Define 118 //------------------------------------------------------------------------------------------------- 119 #define PNL_LIB_VERSION "000.000.000.000" 120 121 //clock hz define, the unit is 0.1hz 122 #define DCLK_1MHZ_X10 0010000000 123 #define DCLK_25MHZ_X10 0250000000 124 #define DCLK_50MHZ_X10 0500000000 125 #define DCLK_75MHZ_X10 0750000000 126 #define DCLK_100MHZ_X10 1000000000 127 #define DCLK_150MHZ_X10 1500000000 128 129 #define KERNEL_DRIVER_PATCH 1 130 #ifdef CONFIG_MS_DEBUG_XC_LOG 131 #ifndef PNL_LOG_DBG 132 #define PNL_LOG_DBG 133 #endif 134 #endif 135 // OS related 136 //#define PNL_LOG_DBG 1 137 #define KERNEL_DRIVER_PNL_STR_PATCH 0 138 139 // Debug related 140 #ifdef PNL_LOG_DBG 141 #if (defined CONFIG_MLOG) 142 #define PNL_DBG(_dbgSwitch_, _fmt, _args...) \ 143 { \ 144 if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) \ 145 {\ 146 ULOGD("PNL_DBG","[%s,%5d] ",__FUNCTION__,__LINE__);\ 147 ULOGD("PNL_DBG","PNL:"_fmt, ##_args); \ 148 }\ 149 } 150 #else 151 #define PNL_DBG(_dbgSwitch_, _fmt, _args...) \ 152 { \ 153 if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) \ 154 {\ 155 printf("PNL_DBG:"_fmt, ##_args); \ 156 }\ 157 } 158 #endif 159 #else 160 #define PNL_DBG(_dbgSwitch_, _fmt, _args...) { } 161 #endif 162 163 #define PNL_ASSERT(_cnd, _fmt, _args...) \ 164 if (!(_cnd)) { \ 165 MS_DEBUG_MSG(printf("PNL ASSERT: %s %d:"_fmt, __FILE__, __LINE__, ##_args)); \ 166 /* while(1); */ \ 167 } 168 169 // for Utopia 2.0 to Utopia 1.0 compatibility. 170 DRV_PNL_INTERFACE void* pu32PNLInst_private; 171 DRV_PNL_INTERFACE void* g_pPNLResource[E_PNL_POOL_ID_NUM]; 172 173 //------------------------------------------------------------------------------------------------- 174 // Type and Structure 175 //------------------------------------------------------------------------------------------------- 176 typedef enum 177 { 178 E_PNL_FAIL = 0, 179 E_PNL_OK = 1, 180 E_PNL_GET_BASEADDR_FAIL, ///< get base address failed when initialize panel driver 181 E_PNL_OBTAIN_MUTEX_FAIL, ///< obtain mutex timeout when calling this function 182 } PNL_Result; 183 184 typedef enum 185 { 186 E_DRVPNL_GAMMA_10BIT = 1, 187 E_DRVPNL_GAMMA_12BIT = 2, 188 } DRVPNL_GAMMA_TYPE; 189 190 typedef enum 191 { 192 E_DRVPNL_GAMMA_8BIT_MAPPING = 1, ///< mapping 1024 to 256 gamma entries 193 E_DRVPNL_GAMMA_10BIT_MAPPING = 2, ///< mapping 1024 to 1024 gamma entries 194 } DRVPNL_GAMMA_MAPPEING_MODE; 195 196 /// Define Panel MISC control index 197 /// please enum use BIT0 = 0x01, BIT1 = 0x02, BIT2 = 0x04, BIT3 = 0x08, BIT4 = 0x10, 198 typedef enum 199 { 200 E_DRVPNL_MISC_MFC_ENABLE = 0x0001, 201 202 E_DRVPNL_MISC_MFC_MCP = 0x0010, 203 E_DRVPNL_MISC_MFC_ABChannel = 0x0020, 204 E_DRVPNL_MISC_MFC_ACChannel = 0x0040, 205 E_DRVPNL_MISC_MFC_ENABLE_60HZ = 0x0080, 206 E_DRVPNL_MISC_MFC_ENABLE_240HZ = 0x0100, 207 E_DRVPNL_MISC_4K2K_ENABLE_60HZ = 0x0200, 208 E_DRVPNL_MISC_SKIP_T3D_CONTROL = 0x0400, 209 } DRVPNL_MISC; 210 211 typedef struct 212 { 213 MS_U8 u8SupportGammaType; ///< refer to APIPNL_GAMMA_TYPE 214 MS_U8 u8SupportGammaMapLv; ///< refero to APIPNL_GAMMA_MAPPEING_MODE 215 } ST_PNL_DRV_INFO; 216 217 typedef struct 218 { 219 MS_BOOL bPanel_Initialized; ///< panel initialized or not 220 MS_BOOL bPanel_Enabled; ///< panel enabled or not, if enabled, you can see OSD/Video 221 } PNL_DrvStatus; 222 223 typedef enum 224 { 225 E_PNL_TYPE_TTL, // 0 226 E_PNL_TYPE_LVDS, // 1 227 E_PNL_TYPE_RSDS, // 2 228 E_PNL_TYPE_MINILVDS, // 3 <-- E_XC_PNL_LPLL_MINILVDS_6P_2L, 229 E_PNL_TYPE_ANALOG_MINILVDS, // 4 230 E_PNL_TYPE_DIGITAL_MINILVDS, // 5 231 E_PNL_TYPE_MFC, // 6 232 E_PNL_TYPE_DAC_I, // 7 233 E_PNL_TYPE_DAC_P, // 8 234 E_PNL_TYPE_PDPLVDS, // 9 ///< For PDP(Vsync use Manually MODE) 235 236 E_PNL_TYPE_EXT, // 10 237 E_PNL_LPLL_EPI34_8P = E_PNL_TYPE_EXT,// 10 238 E_PNL_LPLL_EPI28_8P, // 11 239 E_PNL_LPLL_EPI34_6P, // 12 240 E_PNL_LPLL_EPI28_6P, // 13 241 242 // E_PNL_LPLL_MINILVDS_6P_2L, ///< replace this with E_PNL_TYPE_MINILVDS 243 E_PNL_LPLL_MINILVDS_5P_2L, // 14 244 E_PNL_LPLL_MINILVDS_4P_2L, // 15 245 E_PNL_LPLL_MINILVDS_3P_2L, // 16 246 E_PNL_LPLL_MINILVDS_6P_1L, // 17 247 E_PNL_LPLL_MINILVDS_5P_1L, // 18 248 E_PNL_LPLL_MINILVDS_4P_1L, // 19 249 E_PNL_LPLL_MINILVDS_3P_1L, // 20 250 251 E_PNL_TYPE_HS_LVDS, // 21 252 E_PNL_TYPE_HF_LVDS, // 22 253 254 E_PNL_TYPE_TTL_TCON, // 23 255 E_PNL_LPLL_MINILVDS_2CH_3P_8BIT, // 24 // 2 channel, 3 pari, 8 bits 256 E_PNL_LPLL_MINILVDS_2CH_4P_8BIT, // 25 // 2 channel, 4 pari, 8 bits 257 E_PNL_LPLL_MINILVDS_2CH_5P_8BIT, // 26 //2 channel, 5 pari, 8 bits 258 E_PNL_LPLL_MINILVDS_2CH_6P_8BIT, // 27 //2 channel, 6 pari, 8 bits 259 260 E_PNL_LPLL_MINILVDS_1CH_3P_8BIT, // 28 //1 channel, 3 pair, 8 bits 261 E_PNL_LPLL_MINILVDS_1CH_4P_8BIT, // 29 //1 channel, 4 pair, 8 bits 262 E_PNL_LPLL_MINILVDS_1CH_5P_8BIT, // 30 //1 channel, 5 pair, 8 bits 263 E_PNL_LPLL_MINILVDS_1CH_6P_8BIT, // 31 //1 channel, 6 pair, 8 bits 264 265 E_PNL_LPLL_MINILVDS_2CH_3P_6BIT, // 32 //2 channel, 3 pari, 6 bits 266 E_PNL_LPLL_MINILVDS_2CH_4P_6BIT, // 33 //2 channel, 4 pari, 6 bits 267 E_PNL_LPLL_MINILVDS_2CH_5P_6BIT, // 34 //2 channel, 5 pari, 6 bits 268 E_PNL_LPLL_MINILVDS_2CH_6P_6BIT, // 35 //2 channel, 6 pari, 6 bits 269 270 E_PNL_LPLL_MINILVDS_1CH_3P_6BIT, // 36 //1 channel, 3 pair, 6 bits 271 E_PNL_LPLL_MINILVDS_1CH_4P_6BIT, // 37 //1 channel, 4 pair, 6 bits 272 E_PNL_LPLL_MINILVDS_1CH_5P_6BIT, // 38 //1 channel, 5 pair, 6 bits 273 E_PNL_LPLL_MINILVDS_1CH_6P_6BIT, // 39 //1 channel, 6 pair, 6 bits 274 275 E_PNL_LPLL_HDMI_BYPASS_MODE, //40 // HDMI Bypass Mode 276 277 E_PNL_LPLL_EPI34_2P, /// 41 278 E_PNL_LPLL_EPI34_4P, /// 42 279 E_PNL_LPLL_EPI28_2P, /// 43 280 E_PNL_LPLL_EPI28_4P, /// 44 281 282 E_PNL_LPLL_VBY1_10BIT_4LANE, ///45 283 E_PNL_LPLL_VBY1_10BIT_2LANE, ///46 284 E_PNL_LPLL_VBY1_10BIT_1LANE, ///47 285 E_PNL_LPLL_VBY1_8BIT_4LANE, ///48 286 E_PNL_LPLL_VBY1_8BIT_2LANE, ///49 287 E_PNL_LPLL_VBY1_8BIT_1LANE, ///50 288 289 E_PNL_LPLL_VBY1_10BIT_8LANE, ///51 290 E_PNL_LPLL_VBY1_8BIT_8LANE, ///52 291 292 E_PNL_LPLL_EPI28_12P, /// 53 293 294 E_PNL_LPLL_HS_LVDS_BYPASS_MODE, ///54 295 E_PNL_LPLL_VBY1_10BIT_4LANE_BYPASS_MODE, ///55 296 E_PNL_LPLL_VBY1_8BIT_4LANE_BYPASS_MODE, ///56 297 E_PNL_LPLL_EPI24_12P, ///57 298 E_PNL_LPLL_VBY1_10BIT_16LANE, ///58 299 E_PNL_LPLL_VBY1_8BIT_16LANE, ///59 300 E_PNL_LPLL_USI_T_8BIT_12P, ///60 301 E_PNL_LPLL_USI_T_10BIT_12P, ///61 302 E_PNL_LPLL_ISP_8BIT_12P, ///62 303 E_PNL_LPLL_ISP_8BIT_6P_D, ///63 304 } PNL_TYPE; 305 306 typedef enum 307 { 308 E_PNL_LPLL_VIDEO = 0, 309 E_PNL_LPLL_OSD, 310 311 }PNL_LPLL_TYPE_SEL; 312 313 typedef enum 314 { 315 E_PNL_MODE_SINGLE = 0, ///< single channel 316 E_PNL_MODE_DUAL = 1, ///< dual channel 317 318 E_PNL_MODE_QUAD = 2, ///< quad channel 319 E_PNL_MODE_QUAD_LR = 3, ///< quad channel 320 321 } PNL_MODE; 322 323 typedef enum 324 { 325 E_PNL_OUTPUT_NO_OUTPUT = 0, ///< even called g_IPanel.Enable(TRUE), still no physical output 326 E_PNL_OUTPUT_CLK_ONLY, ///< after called g_IPanel.Enable(TRUE), will output clock only 327 E_PNL_OUTPUT_DATA_ONLY, ///< after called g_IPanel.Enable(TRUE), will output data only 328 E_PNL_OUTPUT_CLK_DATA, ///< after called g_IPanel.Enable(TRUE), will output clock and data 329 E_PNL_OUTPUT_MAX, ///< after called g_IPanel.Enable(TRUE), will output clock and data 330 } PNL_OUTPUT_MODE; 331 332 typedef struct 333 { 334 // Output timing info 335 MS_U16 u16VTotal; ///< Output vertical total 336 MS_U16 u16DEVStart; ///< Output DE vertical start 337 MS_U16 u16DEVEnd; ///< Output DE Vertical end 338 MS_U16 u16VSyncStart; ///< Output VSync start 339 MS_U16 u16VSyncEnd; ///< Output VSync end 340 MS_U16 u16HTotal; ///< Output horizontal total 341 MS_U16 u16DEHStart; ///< Output DE horizontal start 342 MS_U16 u16DEHEnd; ///< Output DE horizontal end 343 MS_U16 u16HSyncWidth; ///< Output HSync width 344 MS_BOOL bIsPanelManualVysncMode; ///< enable manuel V sync control 345 MS_BOOL bInterlaceOutput; ///< enable Scaler Interlace output 346 } PNL_TimingInfo; 347 348 typedef struct __attribute__((packed)) 349 { 350 const char *pPanelName; ///< PanelName 351 #if !defined (__aarch64__) 352 MS_U32 u32AlignmentDummy0; 353 #endif 354 // Output timing 355 MS_U16 u16HStart; ///< DE H start 356 MS_U16 u16VStart; ///< DE V start 357 MS_U16 u16Width; ///< DE H width 358 MS_U16 u16Height; ///< DE V height 359 MS_U16 u16HTotal; ///< H total 360 MS_U16 u16VTotal; ///< V total 361 362 MS_U16 u16DefaultVFreq; ///< Panel output Vfreq., used in free run 363 364 // Later need to refine to use Min/Max SET for PDP panel, but for LCD, it maybe no need to check the Min/Max SET 365 //MS_U16 u16DefaultHTotal, u16DefaultVTotal; 366 //MS_U16 u16MinHTotal, u16DefaultHTotal, u16MaxHTotal; 367 //MS_U16 u16MinVTotal, u16DefaultVTotal, u16MaxVTotal; 368 //MS_U32 u32MinDCLK, u32MaxDCLK; 369 MS_U32 u32MinSET, u32MaxSET; 370 371 // output type 372 PNL_TYPE eLPLL_Type; ///< 0: LVDS type, 1: RSDS type 373 PNL_TYPE eLPLL_Type_Ext; ///< 0: Ext LVDS type, 1: RSDS type 374 PNL_MODE eLPLL_Mode; ///< 0: single mode, 1: dual mode 375 376 // sync 377 MS_U8 u8HSyncWidth; ///< H sync width 378 MS_U16 u16VSyncStart; ///< V sync start = Vtotal - backporch - VSyncWidth 379 MS_U8 u8VSyncWidth; ///< V sync width 380 MS_BOOL bManuelVSyncCtrl; ///< enable manuel V sync control 381 382 // output control 383 MS_U16 u16OCTRL; ///< Output control such as Swap port, etc. 384 MS_U16 u16OSTRL; ///< Output control sync as Invert sync/DE, etc. 385 MS_U16 u16ODRV; ///< Driving current 386 MS_U16 u16DITHCTRL; ///< Dither control 387 388 // MOD 389 MS_U16 u16MOD_CTRL0; ///< MOD_REG(0x40), PANEL_DCLK_DELAY:8, PANEL_SWAP_LVDS_CH:6, PANEL_SWAP_LVDS_POL:5, PANEL_LVDS_TI_MODE:2, 390 MS_U16 u16MOD_CTRL9; ///< MOD_REG(0x49), PANEL_SWAP_EVEN_ML:14, PANEL_SWAP_EVEN_RB:13, PANEL_SWAP_ODD_ML:12, PANEL_SWAP_ODD_RB:11, [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit 391 MS_U16 u16MOD_CTRLA; ///< MOD_REG(0x4A), PANEL_INV_HSYNC:12, PANEL_INV_DCLK:4, PANEL_INV_VSYNC:3, PANEL_INV_DE:2, PANEL_DUAL_PORT:1, PANEL_SWAP_PORT:0, 392 MS_U8 u8MOD_CTRLB; ///< MOD_REG(0x4B), [1:0]ti_bitmode=00(10bit) 393 394 // Other 395 MS_U16 u16LVDSTxSwapValue; ///< swap PN setting 396 MS_U8 u8PanelNoiseDith; ///< PAFRC mixed with noise dither disable 397 MS_U32 u32PNL_MISC; 398 MS_U16 u16OutputCFG0_7; 399 MS_U16 u16OutputCFG8_15; 400 MS_U16 u16OutputCFG16_21; 401 402 // panel on/off timing 403 MS_U16 u16PanelOnTiming1; ///< time between panel & data while turn on power 404 MS_U16 u16PanelOnTiming2; ///< time between data & back light while turn on power 405 MS_U16 u16PanelOffTiming1; ///< time between back light & data while turn off power 406 MS_U16 u16PanelOffTiming2; ///< time between data & panel while turn off power 407 408 MS_U8 u16PanelDimmingCtl; ///< Initial Dimming Value 409 MS_U8 u16PanelMaxPWMVal; ///< Max Dimming Value 410 MS_U8 u16PanelMinPWMVal; ///< Min Dimming Value 411 412 ///< not support Manuel VSync Start/End now 413 ///< VOP_02[10:0] VSync start = Vtt - VBackPorch - VSyncWidth 414 ///< VOP_03[10:0] VSync end = Vtt - VBackPorch 415 MS_U8 u16PanelHSyncBackPorch; ///< PANEL_HSYNC_BACK_PORCH, no register setting, provide value for query only 416 MS_U8 u16PanelVBackPorch; ///< define PANEL_VSYNC_BACK_PORCH 417 MS_U16 u16PanelAspectRatio; ///< Panel Aspect Ratio, provide information to upper layer application for aspect ratio setting. 418 419 MS_U16 u16PanelOutTimingMode; ///<Define which panel output timing change mode is used to change VFreq for same panel 420 421 MS_U16 u16Ext_LpllType; ///< Ext LPLL type is used by OSDC 422 423 MS_U8 u8OutputOrderType; 424 MS_U16 u16OutputOrder0_3; 425 MS_U16 u16OutputOrder4_7; 426 MS_U16 u16OutputOrder8_11; 427 MS_U16 u16OutputOrder12_13; 428 429 MS_BOOL bVideo_HW_Training_En; ///< Enable Video HW training mode 430 MS_BOOL bOSD_HW_Training_En; ///< Enable OSD HW training mode 431 } PNL_InitData; 432 433 434 435 //HW LVDS Reserved Bit to L/R flag Info 436 typedef struct 437 { 438 MS_U32 u32pair; // pair 0: BIT0, pair 1: BIT1, pair 2: BIT2, pair 3: BIT3, pair 4: BIT4, etc ... 439 MS_U16 u16channel; // channel A: BIT0, channel B: BIT1, 440 MS_BOOL bEnable; 441 } PNL_DrvHW_LVDSResInfo; 442 443 typedef struct 444 { 445 MS_U16 u16ExpectSwingLevel; 446 MS_U8 u8ModCaliPairSel; 447 MS_U8 u8ModCaliTarget; 448 MS_S8 s8ModCaliOffset; 449 MS_BOOL bPVDD_2V5; 450 }PNL_ModCali_InitData; 451 452 typedef enum 453 { 454 /* 455 __________________________________________________________________________________________________________________________________________ 456 |Vby1 Output Format|D0|D1|D2|D3|D4|D5|D6|D7|D8|D9|D10|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|D24|D25|D26|D27|D28|D29|D30|D31| 457 |------------------|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| 458 | ARGB 1 |R0|R1|R2|R3|R4|R5|R6|R7|G0|G1|G2 |G3 |G4 |G5 |G6 |G7 |B0 |B1 |B2 |B3 |B4 |B5 |B6 |B7 |A1 |A0 |A2 |A3 |A4 |A5 |A6 |A7 | 459 |------------------|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| 460 | ARGB 2 |R2|R3|R4|R5|R6|R7|A6|A7|G2|G3|G4 |G5 |G6 |G7 |A4 |A5 |B2 |B3 |B4 |B5 |B6 |B7 |A2 |A3 |A0 |A1 |B0 |B1 |G0 |G1 |R0 |R1 | 461 ------------------------------------------------------------------------------------------------------------------------------------------ 462 */ 463 E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB1, 464 E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB2, 465 } E_PNL_OSDC_OUTPUT_FORMAT; 466 467 468 #define IsVBY1(x) ( (((x)>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&((x)<= E_PNL_LPLL_VBY1_8BIT_8LANE)) || ((x)== E_PNL_LPLL_VBY1_10BIT_16LANE)||((x)== E_PNL_LPLL_VBY1_8BIT_16LANE) ) 469 //------------------------------------------------------------------------------------------------- 470 // Function and Variable 471 //------------------------------------------------------------------------------------------------- 472 DRV_PNL_INTERFACE MS_U16 _u16PnlDbgSwitch; 473 474 // must have functions 475 DRV_PNL_INTERFACE const MS_U8 * MDrv_PNL_GetLibVer(void); ///< Get version (without Mutex protect) 476 DRV_PNL_INTERFACE ST_PNL_DRV_INFO MDrv_PNL_GetInfo(void *pInstance); ///< Get supported gamma type from driver (without Mutex protect) 477 478 // initial functions 479 PNL_Result MDrv_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam); 480 PNL_Result MDrv_PNL_Init(void *pInstance); ///< initialize panel driver 481 PNL_Result MDrv_PNL_Close(void *pInstance); ///< close panel driver and release resources 482 483 //DRV_PNL_INTERFACE void MDrv_PNL_TCONMAP_DumpTable(MS_U8 *pTCONTable, MS_U8 u8Tcontype); 484 //DRV_PNL_INTERFACE void MDrv_PNL_TCONMAP_Power_Sequence(MS_U8 *pTCONTable, MS_BOOL bEnable); 485 void MDrv_PNL_TCON_DumpSCRegTab(void *pInstance, MS_U8* pu8TconTab); 486 void MDrv_PNL_TCON_DumpMODRegTab(void *pInstance, MS_U8* pu8TconTab); 487 void MDrv_PNL_TCON_DumpGENRegTab(void *pInstance, MS_U8* pu8TconTab); 488 489 490 DRV_PNL_INTERFACE void MDrv_PNL_TCON_Count_Reset(void *pInstance, MS_BOOL bEnable); 491 DRV_PNL_INTERFACE void MDrv_PNL_TCON_Init(void *pInstance); 492 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_GetDataFromRegister(void *pInstance, PNL_TimingInfo *PNLTiming); 493 494 // control & setting functions 495 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn); ///< bPanelOn = TRUE to show up OSD & video 496 497 #define MDrv_PNL_MOD_Calibration MHal_PNL_MOD_Calibration 498 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_MOD_Calibration(void *pInstance); 499 500 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetGammaTbl(void *pInstance, DRVPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3], DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); ///< set gamma table 501 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_GetGammaTbl(void *pInstance, DRVPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3],DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); ///< get gamma table 502 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16Offset, MS_U16 u16GammaValue); 503 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 504 DRV_PNL_INTERFACE void MDrv_PNL_MFC(void *pInstance, MS_BOOL bIsMFC); 505 DRV_PNL_INTERFACE void MDrv_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 506 DRV_PNL_INTERFACE void MDrv_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type); 507 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetPanelType(void *pInstance, PNL_InitData *pstPanelInitData); 508 509 DRV_PNL_INTERFACE void MDrv_PNL_SetSSC_Rdeviation(void *pInstance, MS_U16 u16Rdeviation); 510 DRV_PNL_INTERFACE void MDrv_PNL_SetSSC_Fmodulation(void *pInstance, MS_U16 u16Fmodulation); 511 DRV_PNL_INTERFACE void MDrv_PNL_SetSSC_En(void *pInstance, MS_BOOL bEnable); 512 513 DRV_PNL_INTERFACE void MDrv_PNL_SetOSDSSC_Rdeviation(void *pInstance, MS_U16 u16Rdeviation); 514 DRV_PNL_INTERFACE void MDrv_PNL_SetOSDSSC_Fmodulation(void *pInstance, MS_U16 u16Fmodulation); 515 DRV_PNL_INTERFACE void MDrv_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable); 516 517 DRV_PNL_INTERFACE void MDrv_Mod_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData); 518 DRV_PNL_INTERFACE void MDrv_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type); 519 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level); 520 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_SkipTimingChange_GetCaps(void *pInstance); 521 DRV_PNL_INTERFACE void MDrv_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode); 522 523 DRV_PNL_INTERFACE void MDrv_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo); 524 DRV_PNL_INTERFACE void MDrv_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_LSB_Addr, MS_U8 u8ODTbl[1056]); 525 DRV_PNL_INTERFACE void MDrv_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable); 526 DRV_PNL_INTERFACE MS_U32 MDrv_PNL_CalculateLPLLSETbyDClk(void *pInstance, MS_U64 ldHz, MS_BOOL bHighAccurate); 527 528 #define MDrv_MOD_PVDD_Power_Setting MHal_MOD_PVDD_Power_Setting 529 DRV_PNL_INTERFACE void MDrv_MOD_PVDD_Power_Setting(void *pInstance, MS_BOOL bIs2p5); 530 531 #define MDrv_PNL_MISC_Control MHal_PNL_MISC_Control 532 DRV_PNL_INTERFACE void MDrv_PNL_MISC_Control(void *pInstance, MS_U32 u32PNL_MISC); 533 534 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Is_SupportFRC(void *pInstance); 535 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Is_SupportTCON(void *pInstance); 536 DRV_PNL_INTERFACE void MDrv_FRC_MOD_ForcePairSwap(void *pInstance, MS_U32 u32Polarity); 537 MS_U16 MDrv_PNL_Get_DEVstart(void *pInstance); 538 MS_U16 MDrv_PNL_Get_DEHstart(void *pInstance); 539 MS_U16 MDrv_PNL_GetDefaultVfreq(void *pInstance, MS_U16 u16Vfreq); 540 MS_BOOL MDrv_PNL_isYUVOutput(void *pInstance); 541 MS_BOOL MDrv_PNL_GetDACOut(void *pInstance); 542 543 void MDrv_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz); 544 545 MS_BOOL MDrv_PNL_EnableInternalTermination(void *pInstance, MS_BOOL bEnable); 546 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_VBY1_Handshake(void *pInstance); 547 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_VBY1_OC_Handshake(void *pInstance); 548 DRV_PNL_INTERFACE PNL_Result MDrv_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable); 549 DRV_PNL_INTERFACE void MDrv_PNL_GetOutputInterlaceTiming(void *pInstance, MS_BOOL* bIsInterlaceOutput); 550 DRV_PNL_INTERFACE void MDrv_PNL_SetOSDCOutputType(void *pInstance, MS_U16 eLPLL_Type, MS_U8 eOC_OutputFormat); 551 DRV_PNL_INTERFACE MS_U32 MDrv_PNL_Get_Semaphore(void *pInstance,E_PNL_POOL_ID eID); 552 DRV_PNL_INTERFACE MS_U32 MDrv_PNL_Release_Semaphore(void *pInstance,E_PNL_POOL_ID eID); 553 DRV_PNL_INTERFACE MS_U32 MDrv_PNL_GetDeviceNum(void); 554 DRV_PNL_INTERFACE MS_U16 MDrv_PNL_GetPanelVStart(void); 555 DRV_PNL_INTERFACE MS_BOOL MDrv_PNL_Check_VBY1_Handshake_Status(void *pInstance); 556 DRV_PNL_INTERFACE void MDrv_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select); 557 DRV_PNL_INTERFACE void MDrv_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable); 558 DRV_PNL_INTERFACE const char* MDrv_PNL_GetName(void); 559 560 #endif // _DRV_PNL_H_ 561 562