1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal power management enums and defines */ 9 10 #ifndef PM_DEFS_H 11 #define PM_DEFS_H 12 13 #include "pm_node.h" 14 15 /********************************************************************* 16 * Macro definitions 17 ********************************************************************/ 18 19 /* State arguments of the self suspend */ 20 #define PM_STATE_CPU_IDLE 0x0U 21 #define PM_STATE_CPU_OFF 0x1U 22 #define PM_STATE_SUSPEND_TO_RAM 0xFU 23 24 #define MAX_LATENCY (~0U) 25 26 /* Processor core device IDs */ 27 #define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \ 28 XPM_NODETYPE_DEV_CORE_APU, (IDX)) 29 30 #define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) 31 #define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) 32 33 #define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \ 34 (uint32_t)XPM_NODESUBCL_DEV_PERIPH, \ 35 (uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX)) 36 37 #define TF_A_FEATURE_CHECK 0xa00U 38 #define PM_GET_CALLBACK_DATA 0xa01U 39 #define PM_GET_TRUSTZONE_VERSION 0xa03U 40 #define TF_A_PM_REGISTER_SGI 0xa04U 41 #define TF_A_CLEAR_PM_STATE 0xa05U 42 43 /* PM API Versions */ 44 #define PM_API_BASE_VERSION 1U 45 #define PM_API_VERSION_2 2U 46 47 /* Loader API ids */ 48 #define PM_LOAD_PDI 0x701U 49 #define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU 50 51 /* Boot mode id */ 52 #define CRP_BOOT_MODE_REG_NODE 0x30000001U 53 #define CRP_BOOT_MODE_REG_OFFSET 0x200U 54 55 /* System shutdown macros */ 56 #define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U 57 #define XPM_SHUTDOWN_TYPE_RESET 1U 58 #define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U 59 60 #define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U 61 #define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U 62 #define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U 63 64 /********************************************************************* 65 * Enum definitions 66 ********************************************************************/ 67 68 /* 69 * ioctl id 70 */ 71 enum { 72 IOCTL_GET_RPU_OPER_MODE = 0, 73 IOCTL_SET_RPU_OPER_MODE = 1, 74 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 75 IOCTL_TCM_COMB_CONFIG = 3, 76 IOCTL_SET_TAPDELAY_BYPASS = 4, 77 IOCTL_SD_DLL_RESET = 6, 78 IOCTL_SET_SD_TAPDELAY = 7, 79 /* Ioctl for clock driver */ 80 IOCTL_SET_PLL_FRAC_MODE = 8, 81 IOCTL_GET_PLL_FRAC_MODE = 9, 82 IOCTL_SET_PLL_FRAC_DATA = 10, 83 IOCTL_GET_PLL_FRAC_DATA = 11, 84 IOCTL_WRITE_GGS = 12, 85 IOCTL_READ_GGS = 13, 86 IOCTL_WRITE_PGGS = 14, 87 IOCTL_READ_PGGS = 15, 88 /* IOCTL for ULPI reset */ 89 IOCTL_ULPI_RESET = 16, 90 /* Set healthy bit value */ 91 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 92 IOCTL_AFI = 18, 93 /* Probe counter read/write */ 94 IOCTL_PROBE_COUNTER_READ = 19, 95 IOCTL_PROBE_COUNTER_WRITE = 20, 96 IOCTL_OSPI_MUX_SELECT = 21, 97 /* IOCTL for USB power request */ 98 IOCTL_USB_SET_STATE = 22, 99 /* IOCTL to get last reset reason */ 100 IOCTL_GET_LAST_RESET_REASON = 23, 101 /* AI engine NPI ISR clear */ 102 IOCTL_AIE_ISR_CLEAR = 24, 103 IOCTL_READ_REG = 28U, 104 IOCTL_UFS_TXRX_CFGRDY_GET = 40, 105 IOCTL_UFS_SRAM_CSR_SEL = 41, 106 }; 107 108 /** 109 * enum pm_pll_param - enum represents the parameters for a phase-locked loop. 110 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL. 111 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL. 112 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL. 113 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input. 114 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode. 115 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize. 116 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting. 117 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control. 118 * @PM_PLL_PARAM_CP: PLL charge pump control. 119 * @PM_PLL_PARAM_RES: PLL loop filter resistor control. 120 * @PM_PLL_PARAM_MAX: Represents the maximum parameter value for the PLL 121 */ 122 enum pm_pll_param { 123 PM_PLL_PARAM_DIV2, 124 PM_PLL_PARAM_FBDIV, 125 PM_PLL_PARAM_DATA, 126 PM_PLL_PARAM_PRE_SRC, 127 PM_PLL_PARAM_POST_SRC, 128 PM_PLL_PARAM_LOCK_DLY, 129 PM_PLL_PARAM_LOCK_CNT, 130 PM_PLL_PARAM_LFHF, 131 PM_PLL_PARAM_CP, 132 PM_PLL_PARAM_RES, 133 PM_PLL_PARAM_MAX, 134 }; 135 136 enum pm_api_id { 137 /* Miscellaneous API functions: */ 138 PM_GET_API_VERSION = 1, /* Do not change or move */ 139 PM_SET_CONFIGURATION, 140 PM_GET_NODE_STATUS, 141 PM_GET_OP_CHARACTERISTIC, 142 PM_REGISTER_NOTIFIER, 143 /* API for suspending of PUs: */ 144 PM_REQ_SUSPEND, 145 PM_SELF_SUSPEND, 146 PM_FORCE_POWERDOWN, 147 PM_ABORT_SUSPEND, 148 PM_REQ_WAKEUP, 149 PM_SET_WAKEUP_SOURCE, 150 PM_SYSTEM_SHUTDOWN, 151 /* API for managing PM slaves: */ 152 PM_REQ_NODE, 153 PM_RELEASE_NODE, 154 PM_SET_REQUIREMENT, 155 PM_SET_MAX_LATENCY, 156 /* Direct control API functions: */ 157 PM_RESET_ASSERT, 158 PM_RESET_GET_STATUS, 159 PM_MMIO_WRITE, 160 PM_MMIO_READ, 161 PM_INIT_FINALIZE, 162 PM_FPGA_LOAD, 163 PM_FPGA_GET_STATUS, 164 PM_GET_CHIPID, 165 PM_SECURE_RSA_AES, 166 PM_SECURE_SHA, 167 PM_SECURE_RSA, 168 PM_PINCTRL_REQUEST, 169 PM_PINCTRL_RELEASE, 170 PM_PINCTRL_GET_FUNCTION, 171 PM_PINCTRL_SET_FUNCTION, 172 PM_PINCTRL_CONFIG_PARAM_GET, 173 PM_PINCTRL_CONFIG_PARAM_SET, 174 PM_IOCTL, 175 /* API to query information from firmware */ 176 PM_QUERY_DATA, 177 /* Clock control API functions */ 178 PM_CLOCK_ENABLE, 179 PM_CLOCK_DISABLE, 180 PM_CLOCK_GETSTATE, 181 PM_CLOCK_SETDIVIDER, 182 PM_CLOCK_GETDIVIDER, 183 PM_CLOCK_SETPARENT = 43, 184 PM_CLOCK_GETPARENT, 185 PM_SECURE_IMAGE, 186 /* FPGA PL Readback */ 187 PM_FPGA_READ, 188 PM_SECURE_AES, 189 /* PLL control API functions */ 190 PM_PLL_SET_PARAMETER, 191 PM_PLL_GET_PARAMETER, 192 PM_PLL_SET_MODE, 193 PM_PLL_GET_MODE, 194 /* PM Register Access API */ 195 PM_REGISTER_ACCESS, 196 PM_EFUSE_ACCESS, 197 PM_FPGA_GET_VERSION, 198 PM_FPGA_GET_FEATURE_LIST, 199 PM_FEATURE_CHECK = 63, 200 PM_API_MAX = 74 201 }; 202 203 enum pm_abort_reason { 204 ABORT_REASON_WKUP_EVENT = 100, 205 ABORT_REASON_PU_BUSY, 206 ABORT_REASON_NO_PWRDN, 207 ABORT_REASON_UNKNOWN, 208 }; 209 210 /* TODO: move pm_ret_status from device specific location to common location */ 211 /** 212 * enum pm_ret_status - enum represents the return status codes for a PM 213 * operation. 214 * @PM_RET_SUCCESS: success. 215 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated). 216 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated). 217 * @PM_RET_ERROR_IOCTL_NOT_SUPPORTED: IOCTL is not supported. 218 * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication. 219 * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled. 220 * @PM_RET_ERROR_INTERNAL: internal error. 221 * @PM_RET_ERROR_CONFLICT: conflict. 222 * @PM_RET_ERROR_ACCESS: access rights violation. 223 * @PM_RET_ERROR_INVALID_NODE: invalid node. 224 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node. 225 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted. 226 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU. 227 * @PM_RET_ERROR_NODE_USED: node is already in use. 228 * @PM_RET_ERROR_NO_FEATURE: indicates that the requested feature is not 229 * supported. 230 */ 231 enum pm_ret_status { 232 PM_RET_SUCCESS = 0U, 233 PM_RET_ERROR_ARGS = 1U, 234 PM_RET_ERROR_NOTSUPPORTED = 4U, 235 PM_RET_ERROR_IOCTL_NOT_SUPPORTED = 19U, 236 PM_RET_ERROR_NOT_ENABLED = 29U, 237 PM_RET_ERROR_INVALID_CRC = 301U, 238 PM_RET_ERROR_INTERNAL = 2000U, 239 PM_RET_ERROR_CONFLICT = 2001U, 240 PM_RET_ERROR_ACCESS = 2002U, 241 PM_RET_ERROR_INVALID_NODE = 2003U, 242 PM_RET_ERROR_DOUBLE_REQ = 2004U, 243 PM_RET_ERROR_ABORT_SUSPEND = 2005U, 244 PM_RET_ERROR_TIMEOUT = 2006U, 245 PM_RET_ERROR_NODE_USED = 2007U, 246 PM_RET_ERROR_NO_FEATURE = 2008U 247 }; 248 249 /* 250 * Qids 251 */ 252 enum pm_query_id { 253 XPM_QID_INVALID, 254 XPM_QID_CLOCK_GET_NAME, 255 XPM_QID_CLOCK_GET_TOPOLOGY, 256 XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, 257 XPM_QID_CLOCK_GET_MUXSOURCES, 258 XPM_QID_CLOCK_GET_ATTRIBUTES, 259 XPM_QID_PINCTRL_GET_NUM_PINS, 260 XPM_QID_PINCTRL_GET_NUM_FUNCTIONS, 261 XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, 262 XPM_QID_PINCTRL_GET_FUNCTION_NAME, 263 XPM_QID_PINCTRL_GET_FUNCTION_GROUPS, 264 XPM_QID_PINCTRL_GET_PIN_GROUPS, 265 XPM_QID_CLOCK_GET_NUM_CLOCKS, 266 XPM_QID_CLOCK_GET_MAX_DIVISOR, 267 XPM_QID_PLD_GET_PARENT, 268 }; 269 270 enum pm_boot_mode_ids { 271 BOOT_MODE_INVALID = 0x000000FFU, 272 BOOT_MODES_MASK = 0x0000000FU, 273 QSPI_MODE_24BIT = 0x00000001U, 274 QSPI_MODE_32BIT = 0x00000002U, 275 SD_MODE = 0x00000003U, /* sd 0 */ 276 SD_MODE1 = 0x00000005U, /* sd 1 */ 277 EMMC_MODE = 0x00000006U, 278 USB_MODE = 0x00000007U, 279 OSPI_MODE = 0x00000008U, 280 SELECTMAP_MODE = 0x0000000AU, 281 SD1_LSHFT_MODE = 0x0000000EU, /* SD1 Level shifter */ 282 JTAG_MODE = 0x00000000U, 283 }; 284 #endif /* PM_DEFS_H */ 285