1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Misc utility routines for accessing the SOC Interconnects
4 * of Broadcom HNBU chips.
5 *
6 * Copyright (C) 1999-2017, Broadcom Corporation
7 *
8 * Unless you and Broadcom execute a separate written software license
9 * agreement governing use of this software, this software is licensed to you
10 * under the terms of the GNU General Public License version 2 (the "GPL"),
11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12 * following added to such license:
13 *
14 * As a special exception, the copyright holders of this software give you
15 * permission to link this software with independent modules, and to copy and
16 * distribute the resulting executable under terms of your choice, provided that
17 * you also meet, for each linked independent module, the terms and conditions of
18 * the license of that module. An independent module is a module which is not
19 * derived from this software. The special exception does not apply to any
20 * modifications of the software.
21 *
22 * Notwithstanding the above, under no circumstances may you combine this
23 * software in any way with any other Broadcom software provided under a license
24 * other than the GPL, without Broadcom's express prior written consent.
25 *
26 *
27 * <<Broadcom-WL-IPTag/Open:>>
28 *
29 * $Id: siutils.h 668442 2016-11-03 08:42:43Z $
30 */
31
32 #ifndef _siutils_h_
33 #define _siutils_h_
34
35 #ifdef SR_DEBUG
36 #include "wlioctl.h"
37 #endif /* SR_DEBUG */
38
39
40 #define WARM_BOOT 0xA0B0C0D0
41
42 #ifdef BCM_BACKPLANE_TIMEOUT
43
44 #define SI_MAX_ERRLOG_SIZE 4
45 typedef struct si_axi_error
46 {
47 uint32 error;
48 uint32 coreid;
49 uint32 errlog_lo;
50 uint32 errlog_hi;
51 uint32 errlog_id;
52 uint32 errlog_flags;
53 uint32 errlog_status;
54 } si_axi_error_t;
55
56 typedef struct si_axi_error_info
57 {
58 uint32 count;
59 si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE];
60 } si_axi_error_info_t;
61 #endif /* BCM_BACKPLANE_TIMEOUT */
62
63 /**
64 * Data structure to export all chip specific common variables
65 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
66 */
67 struct si_pub {
68 uint socitype; /**< SOCI_SB, SOCI_AI */
69
70 uint bustype; /**< SI_BUS, PCI_BUS */
71 uint buscoretype; /**< PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
72 uint buscorerev; /**< buscore rev */
73 uint buscoreidx; /**< buscore index */
74 int ccrev; /**< chip common core rev */
75 uint32 cccaps; /**< chip common capabilities */
76 uint32 cccaps_ext; /**< chip common capabilities extension */
77 int pmurev; /**< pmu core rev */
78 uint32 pmucaps; /**< pmu capabilities */
79 uint boardtype; /**< board type */
80 uint boardrev; /* board rev */
81 uint boardvendor; /**< board vendor */
82 uint boardflags; /**< board flags */
83 uint boardflags2; /**< board flags2 */
84 uint chip; /**< chip number */
85 uint chiprev; /**< chip revision */
86 uint chippkg; /**< chip package option */
87 uint32 chipst; /**< chip status */
88 bool issim; /**< chip is in simulation or emulation */
89 uint socirev; /**< SOC interconnect rev */
90 bool pci_pr32414;
91 int gcirev; /**< gci core rev */
92 #ifdef BCM_BACKPLANE_TIMEOUT
93 si_axi_error_info_t * err_info;
94 #endif /* BCM_BACKPLANE_TIMEOUT */
95 };
96
97 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
98 * for monolithic driver, it is readonly to prevent accident change
99 */
100 typedef const struct si_pub si_t;
101
102 /*
103 * Many of the routines below take an 'sih' handle as their first arg.
104 * Allocate this by calling si_attach(). Free it by calling si_detach().
105 * At any one time, the sih is logically focused on one particular si core
106 * (the "current core").
107 * Use si_setcore() or si_setcoreidx() to change the association to another core.
108 */
109 #define SI_OSH NULL /**< Use for si_kattach when no osh is available */
110
111 #define BADIDX (SI_MAXCORES + 1)
112
113 /* clkctl xtal what flags */
114 #define XTAL 0x1 /**< primary crystal oscillator (2050) */
115 #define PLL 0x2 /**< main chip pll */
116
117 /* clkctl clk mode */
118 #define CLK_FAST 0 /**< force fast (pll) clock */
119 #define CLK_DYNAMIC 2 /**< enable dynamic clock control */
120
121 /* GPIO usage priorities */
122 #define GPIO_DRV_PRIORITY 0 /**< Driver */
123 #define GPIO_APP_PRIORITY 1 /**< Application */
124 #define GPIO_HI_PRIORITY 2 /**< Highest priority. Ignore GPIO reservation */
125
126 /* GPIO pull up/down */
127 #define GPIO_PULLUP 0
128 #define GPIO_PULLDN 1
129
130 /* GPIO event regtype */
131 #define GPIO_REGEVT 0 /**< GPIO register event */
132 #define GPIO_REGEVT_INTMSK 1 /**< GPIO register event int mask */
133 #define GPIO_REGEVT_INTPOL 2 /**< GPIO register event int polarity */
134
135 /* device path */
136 #define SI_DEVPATH_BUFSZ 16 /**< min buffer size in bytes */
137
138 /* SI routine enumeration: to be used by update function with multiple hooks */
139 #define SI_DOATTACH 1
140 #define SI_PCIDOWN 2 /**< wireless interface is down */
141 #define SI_PCIUP 3 /**< wireless interface is up */
142
143 #ifdef SR_DEBUG
144 #define PMU_RES 31
145 #endif /* SR_DEBUG */
146
147 /* "access" param defines for si_seci_access() below */
148 #define SECI_ACCESS_STATUSMASK_SET 0
149 #define SECI_ACCESS_INTRS 1
150 #define SECI_ACCESS_UART_CTS 2
151 #define SECI_ACCESS_UART_RTS 3
152 #define SECI_ACCESS_UART_RXEMPTY 4
153 #define SECI_ACCESS_UART_GETC 5
154 #define SECI_ACCESS_UART_TXFULL 6
155 #define SECI_ACCESS_UART_PUTC 7
156 #define SECI_ACCESS_STATUSMASK_GET 8
157
158 #define ISSIM_ENAB(sih) FALSE
159
160 #define INVALID_ADDR (~0)
161
162 /* PMU clock/power control */
163 #if defined(BCMPMUCTL)
164 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
165 #else
166 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
167 #endif
168
169 #if defined(BCMAOBENAB)
170 #define AOB_ENAB(sih) (BCMAOBENAB)
171 #else
172 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \
173 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
174 #endif /* BCMAOBENAB */
175
176 /* chipcommon clock/power control (exclusive with PMU's) */
177 #if defined(BCMPMUCTL) && BCMPMUCTL
178 #define CCCTL_ENAB(sih) (0)
179 #define CCPLL_ENAB(sih) (0)
180 #else
181 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
182 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
183 #endif
184
185 typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg);
186
187 /* External BT Coex enable mask */
188 #define CC_BTCOEX_EN_MASK 0x01
189 /* External PA enable mask */
190 #define GPIO_CTRL_EPA_EN_MASK 0x40
191 /* WL/BT control enable mask */
192 #define GPIO_CTRL_5_6_EN_MASK 0x60
193 #define GPIO_CTRL_7_6_EN_MASK 0xC0
194 #define GPIO_OUT_7_EN_MASK 0x80
195
196
197
198 /* CR4 specific defines used by the host driver */
199 #define SI_CR4_CAP (0x04)
200 #define SI_CR4_BANKIDX (0x40)
201 #define SI_CR4_BANKINFO (0x44)
202 #define SI_CR4_BANKPDA (0x4C)
203
204 #define ARMCR4_TCBBNB_MASK 0xf0
205 #define ARMCR4_TCBBNB_SHIFT 4
206 #define ARMCR4_TCBANB_MASK 0xf
207 #define ARMCR4_TCBANB_SHIFT 0
208
209 #define SICF_CPUHALT (0x0020)
210 #define ARMCR4_BSZ_MASK 0x3f
211 #define ARMCR4_BSZ_MULT 8192
212 #define SI_BPIND_1BYTE 0x1
213 #define SI_BPIND_2BYTE 0x3
214 #define SI_BPIND_4BYTE 0xF
215 #include <osl_decl.h>
216 /* === exported functions === */
217 extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype,
218 void *sdh, char **vars, uint *varsz);
219 extern si_t *si_kattach(osl_t *osh);
220 extern void si_detach(si_t *sih);
221 extern bool si_pci_war16165(si_t *sih);
222 extern volatile void *
223 si_d11_switch_addrbase(si_t *sih, uint coreunit);
224 extern uint si_corelist(si_t *sih, uint coreid[]);
225 extern uint si_coreid(si_t *sih);
226 extern uint si_flag(si_t *sih);
227 extern uint si_flag_alt(si_t *sih);
228 extern uint si_intflag(si_t *sih);
229 extern uint si_coreidx(si_t *sih);
230 extern uint si_coreunit(si_t *sih);
231 extern uint si_corevendor(si_t *sih);
232 extern uint si_corerev(si_t *sih);
233 extern void *si_osh(si_t *sih);
234 extern void si_setosh(si_t *sih, osl_t *osh);
235 extern uint si_backplane_access(si_t *sih, uint addr, uint size,
236 uint *val, bool read);
237 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
238 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
239 extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
240 extern volatile void *si_coreregs(si_t *sih);
241 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
242 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
243 extern void *si_wrapperregs(si_t *sih);
244 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
245 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
246 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
247 extern void si_commit(si_t *sih);
248 extern bool si_iscoreup(si_t *sih);
249 extern uint si_numcoreunits(si_t *sih, uint coreid);
250 extern uint si_numd11coreunits(si_t *sih);
251 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
252 extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
253 extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
254 extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
255 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
256 extern int si_numaddrspaces(si_t *sih);
257 extern uint32 si_addrspace(si_t *sih, uint asidx);
258 extern uint32 si_addrspacesize(si_t *sih, uint asidx);
259 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
260 extern int si_corebist(si_t *sih);
261 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
262 extern void si_core_disable(si_t *sih, uint32 bits);
263 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
264 extern uint si_chip_hostif(si_t *sih);
265 extern bool si_read_pmu_autopll(si_t *sih);
266 extern uint32 si_clock(si_t *sih);
267 extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */
268 extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */
269 extern void si_pci_setup(si_t *sih, uint coremask);
270 extern void si_pcmcia_init(si_t *sih);
271 extern void si_setint(si_t *sih, int siflag);
272 extern bool si_backplane64(si_t *sih);
273 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
274 void *intrsenabled_fn, void *intr_arg);
275 extern void si_deregister_intr_callback(si_t *sih);
276 extern void si_clkctl_init(si_t *sih);
277 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
278 extern bool si_clkctl_cc(si_t *sih, uint mode);
279 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
280 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
281 extern void si_btcgpiowar(si_t *sih);
282 extern bool si_deviceremoved(si_t *sih);
283 extern void si_set_device_removed(si_t *sih, bool status);
284 extern uint32 si_sysmem_size(si_t *sih);
285 extern uint32 si_socram_size(si_t *sih);
286 extern uint32 si_socdevram_size(si_t *sih);
287 extern uint32 si_socram_srmem_size(si_t *sih);
288 extern void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda);
289 extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap);
290 extern bool si_socdevram_pkg(si_t *sih);
291 extern bool si_socdevram_remap_isenb(si_t *sih);
292 extern uint32 si_socdevram_remap_size(si_t *sih);
293
294 extern void si_watchdog(si_t *sih, uint ticks);
295 extern void si_watchdog_ms(si_t *sih, uint32 ms);
296 extern uint32 si_watchdog_msticks(void);
297 extern volatile void *si_gpiosetcore(si_t *sih);
298 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
299 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
300 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
301 extern uint32 si_gpioin(si_t *sih);
302 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
303 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
304 extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
305 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
306 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
307 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
308 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
309 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
310 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
311 extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode);
312 extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value);
313 extern uint8 si_gci_host_wake_gpio_init(si_t *sih);
314 extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state);
315
316 extern void si_invalidate_second_bar0win(si_t *sih);
317
318 /* GCI interrupt handlers */
319 extern void si_gci_handler_process(si_t *sih);
320
321 /* GCI GPIO event handlers */
322 extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts,
323 gci_gpio_handler_t cb, void *arg);
324 extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i);
325 extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value);
326
327 /* Wake-on-wireless-LAN (WOWL) */
328 extern bool si_pci_pmecap(si_t *sih);
329 extern bool si_pci_fastpmecap(struct osl_info *osh);
330 extern bool si_pci_pmestat(si_t *sih);
331 extern void si_pci_pmeclr(si_t *sih);
332 extern void si_pci_pmeen(si_t *sih);
333 extern void si_pci_pmestatclr(si_t *sih);
334 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
335 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
336 extern void si_deepsleep_count(si_t *sih, bool arm_wakeup);
337
338
339 #ifdef BCMSDIO
340 extern void si_sdio_init(si_t *sih);
341 #endif
342
343 extern uint16 si_d11_devid(si_t *sih);
344 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
345 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
346
347 extern uint32 si_seci_access(si_t *sih, uint32 val, int access);
348 extern volatile void* si_seci_init(si_t *sih, uint8 seci_mode);
349 extern void si_seci_clk_force(si_t *sih, bool val);
350 extern bool si_seci_clk_force_status(si_t *sih);
351
352 #define si_eci(sih) 0
si_eci_init(si_t * sih)353 static INLINE void * si_eci_init(si_t *sih) {return NULL;}
354 #define si_eci_notify_bt(sih, type, val) (0)
355 #define si_seci(sih) 0
356 #define si_seci_upd(sih, a) do {} while (0)
si_gci_init(si_t * sih)357 static INLINE void * si_gci_init(si_t *sih) {return NULL;}
358 #define si_seci_down(sih) do {} while (0)
359 #define si_gci(sih) 0
360
361 /* OTP status */
362 extern bool si_is_otp_disabled(si_t *sih);
363 extern bool si_is_otp_powered(si_t *sih);
364 extern void si_otp_power(si_t *sih, bool on, uint32* min_res_mask);
365
366 /* SPROM availability */
367 extern bool si_is_sprom_available(si_t *sih);
368
369 /* OTP/SROM CIS stuff */
370 extern int si_cis_source(si_t *sih);
371 #define CIS_DEFAULT 0
372 #define CIS_SROM 1
373 #define CIS_OTP 2
374
375 /* Fab-id information */
376 #define DEFAULT_FAB 0x0 /**< Original/first fab used for this chip */
377 #define CSM_FAB7 0x1 /**< CSM Fab7 chip */
378 #define TSMC_FAB12 0x2 /**< TSMC Fab12/Fab14 chip */
379 #define SMIC_FAB4 0x3 /**< SMIC Fab4 chip */
380
381 extern int si_otp_fabid(si_t *sih, uint16 *fabid, bool rw);
382 extern uint16 si_fabid(si_t *sih);
383 extern uint16 si_chipid(si_t *sih);
384
385 /*
386 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
387 * The returned path is NULL terminated and has trailing '/'.
388 * Return 0 on success, nonzero otherwise.
389 */
390 extern int si_devpath(si_t *sih, char *path, int size);
391 extern int si_devpath_pcie(si_t *sih, char *path, int size);
392 /* Read variable with prepending the devpath to the name */
393 extern char *si_getdevpathvar(si_t *sih, const char *name);
394 extern int si_getdevpathintvar(si_t *sih, const char *name);
395 extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
396
397
398 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
399 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
400 extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val);
401 extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val);
402 extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val);
403 extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val);
404 extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val);
405 extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
406 extern void si_pcie_set_L1substate(si_t *sih, uint32 substate);
407 extern uint32 si_pcie_get_L1substate(si_t *sih);
408 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
409 extern void si_pci_down(si_t *sih);
410 extern void si_pci_up(si_t *sih);
411 extern void si_pci_sleep(si_t *sih);
412 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
413 extern void si_pcie_power_save_enable(si_t *sih, bool enable);
414 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
415 extern int si_pci_fixcfg(si_t *sih);
416 extern void si_chippkg_set(si_t *sih, uint);
417 extern bool si_is_warmboot(void);
418
419 extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on);
420 extern void si_chipcontrl_restore(si_t *sih, uint32 val);
421 extern uint32 si_chipcontrl_read(si_t *sih);
422 extern void si_chipcontrl_epa4331(si_t *sih, bool on);
423 extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl);
424 extern void si_chipcontrl_srom4360(si_t *sih, bool on);
425 extern void si_clk_srom4365(si_t *sih);
426 /* Enable BT-COEX & Ex-PA for 4313 */
427 extern void si_epa_4313war(si_t *sih);
428 extern void si_btc_enable_chipcontrol(si_t *sih);
429 /* BT/WL selection for 4313 bt combo >= P250 boards */
430 extern void si_btcombo_p250_4313_war(si_t *sih);
431 extern void si_btcombo_43228_war(si_t *sih);
432 extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear);
433 extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag);
434 extern void si_pmu_synth_pwrsw_4313_war(si_t *sih);
435 extern uint si_pll_reset(si_t *sih);
436 /* === debug routines === */
437
438 extern bool si_taclear(si_t *sih, bool details);
439
440 #if defined(BCMDBG_PHYDUMP)
441 struct bcmstrbuf;
442 extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b);
443 extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b);
444 extern int si_dump_pcieregs(si_t *sih, struct bcmstrbuf *b);
445 #endif
446
447 #if defined(BCMDBG_PHYDUMP)
448 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
449 #endif
450
451 extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
452 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
453 extern int si_bpind_access(si_t *sih, uint32 addr_high, uint32 addr_low,
454 int32* data, bool read);
455 #ifdef SR_DEBUG
456 extern void si_dump_pmu(si_t *sih, void *pmu_var);
457 extern void si_pmu_keep_on(si_t *sih, int32 int_val);
458 extern uint32 si_pmu_keep_on_get(si_t *sih);
459 extern uint32 si_power_island_set(si_t *sih, uint32 int_val);
460 extern uint32 si_power_island_get(si_t *sih);
461 #endif /* SR_DEBUG */
462 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
463 extern void si_pcie_set_request_size(si_t *sih, uint16 size);
464 extern uint16 si_pcie_get_request_size(si_t *sih);
465 extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
466 extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
467 extern uint16 si_pcie_get_ssid(si_t *sih);
468 extern uint32 si_pcie_get_bar0(si_t *sih);
469 extern int si_pcie_configspace_cache(si_t *sih);
470 extern int si_pcie_configspace_restore(si_t *sih);
471 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
472
473
474 #ifdef BCM_BACKPLANE_TIMEOUT
475 extern const si_axi_error_info_t * si_get_axi_errlog_info(si_t *sih);
476 extern void si_reset_axi_errlog_info(si_t * sih);
477 #endif /* BCM_BACKPLANE_TIMEOUT */
478
479 extern uint32 si_tcm_size(si_t *sih);
480 extern bool si_has_flops(si_t *sih);
481
482 extern int si_set_sromctl(si_t *sih, uint32 value);
483 extern uint32 si_get_sromctl(si_t *sih);
484
485 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
486 extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val);
487 extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
488 extern uint32 si_gci_input(si_t *sih, uint reg);
489 extern uint32 si_gci_int_enable(si_t *sih, bool enable);
490 extern void si_gci_reset(si_t *sih);
491 #ifdef BCMLTECOEX
492 extern void si_gci_seci_init(si_t *sih);
493 extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum,
494 uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
495 #endif /* BCMLTECOEX */
496 extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum,
497 uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
498
499 extern bool si_btcx_wci2_init(si_t *sih);
500
501 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
502 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
503 extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel);
504 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
505 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
506 extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
507 extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status);
508 extern void si_swdenable(si_t *sih, uint32 swdflag);
509 extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status);
510
511 extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset);
512 #define CHIPCTRLREG1 0x1
513 #define CHIPCTRLREG2 0x2
514 #define CHIPCTRLREG3 0x3
515 #define CHIPCTRLREG4 0x4
516 #define CHIPCTRLREG5 0x5
517 #define MINRESMASKREG 0x618
518 #define MAXRESMASKREG 0x61c
519 #define CHIPCTRLADDR 0x650
520 #define CHIPCTRLDATA 0x654
521 #define RSRCTABLEADDR 0x620
522 #define RSRCUPDWNTIME 0x628
523 #define PMUREG_RESREQ_MASK 0x68c
524
525 void si_update_masks(si_t *sih);
526 void si_force_islanding(si_t *sih, bool enable);
527 extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
528 extern void si_pmu_rfldo(si_t *sih, bool on);
529 extern void si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 spert_val);
530 extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask, uint32 spert_val);
531 extern void si_pcie_ltr_war(si_t *sih);
532 extern void si_pcie_hw_LTR_war(si_t *sih);
533 extern void si_pcie_hw_L1SS_war(si_t *sih);
534 extern void si_pciedev_crwlpciegen2(si_t *sih);
535 extern void si_pcie_prep_D3(si_t *sih, bool enter_D3);
536 extern void si_pciedev_reg_pm_clk_period(si_t *sih);
537 extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
538 extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
539 extern void si_pcie_disable_oobselltr(si_t *sih);
540 extern uint32 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req);
541
542 #ifdef WLRSDB
543 extern void si_d11rsdb_core_disable(si_t *sih, uint32 bits);
544 extern void si_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
545 extern void set_secondary_d11_core(si_t *sih, void **secmap, void **secwrap);
546 #endif
547
548
549 /* Macro to enable clock gating changes in different cores */
550 #define MEM_CLK_GATE_BIT 5
551 #define GCI_CLK_GATE_BIT 18
552
553 #define USBAPP_CLK_BIT 0
554 #define PCIE_CLK_BIT 3
555 #define ARMCR4_DBG_CLK_BIT 4
556 #define SAMPLE_SYNC_CLK_BIT 17
557 #define PCIE_TL_CLK_BIT 18
558 #define HQ_REQ_BIT 24
559 #define PLL_DIV2_BIT_START 9
560 #define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START)
561 #define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START)
562
563 #define pmu_corereg(si, cc_idx, member, mask, val) \
564 (AOB_ENAB(si) ? \
565 si_pmu_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
566 OFFSETOF(pmuregs_t, member), mask, val): \
567 si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), mask, val))
568
569 /* Used only for the regs present in the pmu core and not present in the old cc core */
570 #define PMU_REG_NEW(si, member, mask, val) \
571 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
572 OFFSETOF(pmuregs_t, member), mask, val)
573
574 #define PMU_REG(si, member, mask, val) \
575 (AOB_ENAB(si) ? \
576 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
577 OFFSETOF(pmuregs_t, member), mask, val): \
578 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val))
579
580 #define LHL_REG(si, member, mask, val) \
581 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
582 OFFSETOF(gciregs_t, member), mask, val)
583
584 #define CHIPC_REG(si, member, mask, val) \
585 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val)
586
587 /* GCI Macros */
588 #define ALLONES_32 0xFFFFFFFF
589 #define GCI_CCTL_SECIRST_OFFSET 0 /**< SeciReset */
590 #define GCI_CCTL_RSTSL_OFFSET 1 /**< ResetSeciLogic */
591 #define GCI_CCTL_SECIEN_OFFSET 2 /**< EnableSeci */
592 #define GCI_CCTL_FSL_OFFSET 3 /**< ForceSeciOutLow */
593 #define GCI_CCTL_SMODE_OFFSET 4 /**< SeciOpMode, 6:4 */
594 #define GCI_CCTL_US_OFFSET 7 /**< UpdateSeci */
595 #define GCI_CCTL_BRKONSLP_OFFSET 8 /**< BreakOnSleep */
596 #define GCI_CCTL_SILOWTOUT_OFFSET 9 /**< SeciInLowTimeout, 10:9 */
597 #define GCI_CCTL_RSTOCC_OFFSET 11 /**< ResetOffChipCoex */
598 #define GCI_CCTL_ARESEND_OFFSET 12 /**< AutoBTSigResend */
599 #define GCI_CCTL_FGCR_OFFSET 16 /**< ForceGciClkReq */
600 #define GCI_CCTL_FHCRO_OFFSET 17 /**< ForceHWClockReqOff */
601 #define GCI_CCTL_FREGCLK_OFFSET 18 /**< ForceRegClk */
602 #define GCI_CCTL_FSECICLK_OFFSET 19 /**< ForceSeciClk */
603 #define GCI_CCTL_FGCA_OFFSET 20 /**< ForceGciClkAvail */
604 #define GCI_CCTL_FGCAV_OFFSET 21 /**< ForceGciClkAvailValue */
605 #define GCI_CCTL_SCS_OFFSET 24 /**< SeciClkStretch, 31:24 */
606
607 #define GCI_MODE_UART 0x0
608 #define GCI_MODE_SECI 0x1
609 #define GCI_MODE_BTSIG 0x2
610 #define GCI_MODE_GPIO 0x3
611 #define GCI_MODE_MASK 0x7
612
613 #define GCI_CCTL_LOWTOUT_DIS 0x0
614 #define GCI_CCTL_LOWTOUT_10BIT 0x1
615 #define GCI_CCTL_LOWTOUT_20BIT 0x2
616 #define GCI_CCTL_LOWTOUT_30BIT 0x3
617 #define GCI_CCTL_LOWTOUT_MASK 0x3
618
619 #define GCI_CCTL_SCS_DEF 0x19
620 #define GCI_CCTL_SCS_MASK 0xFF
621
622 #define GCI_SECIIN_MODE_OFFSET 0
623 #define GCI_SECIIN_GCIGPIO_OFFSET 4
624 #define GCI_SECIIN_RXID2IP_OFFSET 8
625
626 #define GCI_SECIOUT_MODE_OFFSET 0
627 #define GCI_SECIOUT_GCIGPIO_OFFSET 4
628 #define GCI_SECIOUT_LOOPBACK_OFFSET 8
629 #define GCI_SECIOUT_SECIINRELATED_OFFSET 16
630
631 #define GCI_SECIAUX_RXENABLE_OFFSET 0
632 #define GCI_SECIFIFO_RXENABLE_OFFSET 16
633
634 #define GCI_SECITX_ENABLE_OFFSET 0
635
636 #define GCI_GPIOCTL_INEN_OFFSET 0
637 #define GCI_GPIOCTL_OUTEN_OFFSET 1
638 #define GCI_GPIOCTL_PDN_OFFSET 4
639
640 #define GCI_GPIOIDX_OFFSET 16
641
642 #define GCI_LTECX_SECI_ID 0 /**< SECI port for LTECX */
643
644 /* To access per GCI bit registers */
645 #define GCI_REG_WIDTH 32
646
647 /* GCI bit positions */
648 /* GCI [127:000] = WLAN [127:0] */
649 #define GCI_WLAN_IP_ID 0
650 #define GCI_WLAN_BEGIN 0
651 #define GCI_WLAN_PRIO_POS (GCI_WLAN_BEGIN + 4)
652 #define GCI_WLAN_PERST_POS (GCI_WLAN_BEGIN + 15)
653
654 /* GCI [639:512] = LTE [127:0] */
655 #define GCI_LTE_IP_ID 4
656 #define GCI_LTE_BEGIN 512
657 #define GCI_LTE_FRAMESYNC_POS (GCI_LTE_BEGIN + 0)
658 #define GCI_LTE_RX_POS (GCI_LTE_BEGIN + 1)
659 #define GCI_LTE_TX_POS (GCI_LTE_BEGIN + 2)
660 #define GCI_LTE_WCI2TYPE_POS (GCI_LTE_BEGIN + 48)
661 #define GCI_LTE_WCI2TYPE_MASK 7
662 #define GCI_LTE_AUXRXDVALID_POS (GCI_LTE_BEGIN + 56)
663
664 /* Reg Index corresponding to ECI bit no x of ECI space */
665 #define GCI_REGIDX(x) ((x)/GCI_REG_WIDTH)
666 /* Bit offset of ECI bit no x in 32-bit words */
667 #define GCI_BITOFFSET(x) ((x)%GCI_REG_WIDTH)
668
669 /* End - GCI Macros */
670
671 #ifdef REROUTE_OOBINT
672 #define CC_OOB 0x0
673 #define M2MDMA_OOB 0x1
674 #define PMU_OOB 0x2
675 #define D11_OOB 0x3
676 #define SDIOD_OOB 0x4
677 #define WLAN_OOB 0x5
678 #define PMU_OOB_BIT 0x12
679 #endif /* REROUTE_OOBINT */
680
681 #define GCI_REG(si, offset, mask, val) \
682 (AOB_ENAB(si) ? \
683 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
684 offset, mask, val): \
685 si_corereg(si, SI_CC_IDX, offset, mask, val))
686
687 extern void si_pll_sr_reinit(si_t *sih);
688 extern void si_pll_closeloop(si_t *sih);
689 void si_config_4364_d11_oob(si_t *sih, uint coreid);
690 extern void si_update_macclk_mul_fact(si_t *sih, uint mul_fact);
691 extern uint32 si_get_macclk_mul_fact(si_t *sih);
692 extern void si_gci_set_femctrl(si_t *sih, osl_t *osh, bool set);
693 extern void si_gci_set_femctrl_mask_ant01(si_t *sih, osl_t *osh, bool set);
694 extern uint si_num_slaveports(si_t *sih, uint coreid);
695 extern uint32 si_get_slaveport_addr(si_t *sih, uint asidx, uint core_id, uint coreunit);
696 extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint asidx, uint coreunit);
697 uint si_introff(si_t *sih);
698 void si_intrrestore(si_t *sih, uint intr_val);
699 void si_nvram_res_masks(si_t *sih, uint32 *min_mask, uint32 *max_mask);
700 uint32 si_xtalfreq(si_t *sih);
701 extern uint32 si_wrapper_dump_buf_size(si_t *sih);
702 extern uint32 si_wrapper_dump_binary(si_t *sih, uchar *p);
703
704 /* SR Power Control */
705 extern uint32 si_srpwr_request(si_t *sih, uint32 mask, uint32 val);
706 extern uint32 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val);
707 extern uint32 si_srpwr_stat(si_t *sih);
708 extern uint32 si_srpwr_domain(si_t *sih);
709
710 /* SR Power Control */
711 #ifdef BCMSRPWR
712 /* No capabilities bit so using chipid for now */
713 #define SRPWR_CAP(sih) (\
714 (CHIPID(sih->chip) == BCM4347_CHIP_ID) || \
715 (0))
716
717 extern bool _bcmsrpwr;
718 #if defined(WL_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
719 #define SRPWR_ENAB() (_bcmsrpwr)
720 #elif defined(BCMSRPWR_DISABLED)
721 #define SRPWR_ENAB() (0)
722 #else
723 #define SRPWR_ENAB() (1)
724 #endif
725 #else
726 #define SRPWR_CAP(sih) (0)
727 #define SRPWR_ENAB() (0)
728 #endif /* BCMSRPWR */
729
730 #endif /* _siutils_h_ */
731