1 /* 2 * Copyright (c) 2020-2026, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __RZA3M_DEF_H__ 8 #define __RZA3M_DEF_H__ 9 10 #define PLAT_BOOT_ROM_BASE 0x00000000 11 #define PLAT_MSRAM_BASE 0x00010000 12 #define PLAT_ASRAM_BASE 0x00020000 13 #define PLAT_DEVICE_BASE 0x10000000 14 #define PLAT_SCIF0_BASE 0x1004B800 15 #define PLAT_SPIMULT_BASE 0x10060000 16 #define PLAT_SPIMULT_WBUF_BASE 0x10070000 17 #define PLAT_SYC_BASE 0x11000000 18 #define PLAT_CPG_BASE 0x11010000 19 #define PLAT_SYSC_BASE 0x11020000 20 #define PLAT_PFC_BASE 0x11030000 21 #define PLAT_TZC_SPI_BASE 0x11060000 22 #define PLAT_TZC_DDR_BASE 0x11070000 23 #define PLAT_DDR_PHY_BASE 0x11400000 24 #define PLAT_DDR_MEMC_BASE 0x11410000 25 #define PLAT_GIC_BASE 0x11900000 26 #define PLAT_SPIROM_BASE 0x20000000 27 #define PLAT_DDR_BASE 0x40000000 28 29 #define PLAT_GICD_BASE PLAT_GIC_BASE 30 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x00040000) 31 32 #define PLAT_SRAM_BASE PLAT_MSRAM_BASE 33 34 #define PLAT_BOOT_ROM_SIZE (0x00010000 - PLAT_BOOT_ROM_BASE) 35 #define PLAT_MSRAM_SIZE (0x00020000 - PLAT_MSRAM_BASE) 36 #define PLAT_ASRAM_SIZE (0x00030000 - PLAT_ASRAM_BASE) 37 #define PLAT_SRAM_SIZE (PLAT_MSRAM_SIZE + PLAT_ASRAM_SIZE) 38 #define PLAT_DEVICE_SIZE (0x15000000 - PLAT_DEVICE_BASE) 39 #define PLAT_SPIROM_SIZE (0x30000000 - PLAT_SPIROM_BASE) 40 #define PLAT_DDR_SIZE 0x8000000 41 42 #define PLAT_SPIROM_FIP_BASE (PLAT_SPIROM_BASE + 0x0001D200) 43 #define PLAT_SPIROM_FIP_SIZE (0x30000000 - PLAT_SPIROM_FIP_BASE) 44 45 #define PLAT_SYC_INCK_HZ 24000000 46 #define PLAT_UART_INCK_HZ 100000000 47 #define PLAT_UART_BARDRATE 115200 48 49 /* Boot Info base address */ 50 #define PLAT_BOOTINFO_BASE PLAT_SRAM_BASE 51 52 /* Base address where parameters to BL31 are stored */ 53 #define PARAMS_BASE (PLAT_SRAM_BASE + 0x0001F000) 54 #define PARAMS_SIZE 0x1000 55 56 #endif /* __RZA3M_DEF_H__ */ 57