1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include MBEDTLS_CONFIG_FILE 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/common/arm_spm_def.h> 18 #include <plat/arm/css/common/css_def.h> 19 #include <plat/arm/soc/common/soc_css_def.h> 20 #include <plat/common/common_def.h> 21 22 #include "../juno_def.h" 23 #ifdef JUNO_ETHOSN_TZMP1 24 #include "../juno_ethosn_tzmp1_def.h" 25 #endif 26 27 /* Required platform porting definitions */ 28 /* Juno supports system power domain */ 29 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 30 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 31 JUNO_CLUSTER_COUNT + \ 32 PLATFORM_CORE_COUNT) 33 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 34 JUNO_CLUSTER1_CORE_COUNT) 35 36 /* 37 * Other platform porting definitions are provided by included headers 38 */ 39 40 #if SPMC_AT_EL3 41 /* Define memory configuration for device tree files. */ 42 #define PLAT_ARM_HW_CONFIG_SIZE SZ_2K 43 44 /* Define maximum size of sp manifest file. */ 45 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE SZ_2K 46 #else 47 /* Define memory configuration for device tree files. */ 48 #define PLAT_ARM_HW_CONFIG_SIZE U(0x8000) 49 50 /* Define maximum size of sp manifest file. */ 51 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE U(0x0) 52 #endif 53 54 /* 55 * Required ARM standard platform porting definitions 56 */ 57 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 58 59 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 60 61 /* Use the bypass address */ 62 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 63 BL1_ROM_BYPASS_OFFSET) 64 65 #define NSRAM_BASE UL(0x2e000000) 66 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 67 68 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 69 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 70 71 /* Range of kernel DTB load address */ 72 #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) 73 #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ 74 75 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 76 JUNO_DTB_DRAM_MAP_START, \ 77 JUNO_DTB_DRAM_MAP_SIZE, \ 78 MT_MEMORY | MT_RO | MT_NS) 79 80 #ifdef JUNO_ETHOSN_TZMP1 81 #define JUNO_ETHOSN_PROT_FW_RO MAP_REGION_FLAT( \ 82 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 83 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 84 MT_RO_DATA | MT_SECURE) 85 86 #define JUNO_ETHOSN_PROT_FW_RW MAP_REGION_FLAT( \ 87 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 88 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 89 MT_MEMORY | MT_RW | MT_SECURE) 90 #endif 91 92 /* virtual address used by dynamic mem_protect for chunk_base */ 93 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 94 95 /* 96 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 97 */ 98 99 #if USE_ROMLIB 100 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 101 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 102 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 103 #else 104 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 105 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 106 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 107 #endif 108 109 /* 110 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 111 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 112 * flash 113 */ 114 115 #if TRUSTED_BOARD_BOOT 116 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 117 #else 118 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 119 #endif /* TRUSTED_BOARD_BOOT */ 120 121 /* 122 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 123 * plat_arm_mmap array defined for each BL stage. 124 */ 125 #ifdef IMAGE_BL1 126 # define PLAT_ARM_MMAP_ENTRIES 7 127 # define MAX_XLAT_TABLES 4 128 #endif 129 130 #ifdef IMAGE_BL2 131 #ifdef SPD_opteed 132 # define PLAT_ARM_MMAP_ENTRIES 13 133 # define MAX_XLAT_TABLES 5 134 #else 135 # define PLAT_ARM_MMAP_ENTRIES 11 136 # define MAX_XLAT_TABLES 5 137 #endif 138 #endif 139 140 #ifdef IMAGE_BL2U 141 # define PLAT_ARM_MMAP_ENTRIES 5 142 # define MAX_XLAT_TABLES 3 143 #endif 144 145 #ifdef IMAGE_BL31 146 # if SPMC_AT_EL3 147 # define PLAT_ARM_MMAP_ENTRIES 11 148 # define MAX_XLAT_TABLES 10 149 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 150 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 151 # else 152 # define PLAT_ARM_MMAP_ENTRIES 8 153 # define MAX_XLAT_TABLES 6 154 # endif 155 #endif 156 157 #ifdef IMAGE_BL32 158 # define PLAT_ARM_MMAP_ENTRIES 6 159 # define MAX_XLAT_TABLES 4 160 #endif 161 162 #if SPMC_AT_EL3 163 /* 164 * Number of Secure Partitions supported. 165 * SPMC at EL3, uses this count to configure the maximum number of supported 166 * secure partitions. 167 */ 168 #define SECURE_PARTITION_COUNT 1 169 170 /* 171 * Number of Normal World Partitions supported. 172 * SPMC at EL3, uses this count to configure the maximum number of supported 173 * NWd partitions. 174 */ 175 #define NS_PARTITION_COUNT 1 176 177 /* 178 * Number of Logical Partitions supported. 179 * SPMC at EL3, uses this count to configure the maximum number of supported 180 * logical partitions. 181 */ 182 #define MAX_EL3_LP_DESCS_COUNT 1 183 184 #endif /* SPMC_AT_EL3 */ 185 186 #if TRANSFER_LIST 187 #define PLAT_ARM_FW_HANDOFF_SIZE SZ_8K 188 189 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 190 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 191 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 192 193 #define JUNO_MAP_FW_NS_HANDOFF \ 194 MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, \ 195 PLAT_ARM_FW_HANDOFF_SIZE, \ 196 MT_MEMORY | MT_RW | MT_NS) 197 198 #define JUNO_MAP_EL3_FW_HANDOFF \ 199 MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \ 200 PLAT_ARM_FW_HANDOFF_SIZE, \ 201 MT_MEMORY | MT_RW | EL3_PAS) 202 #else 203 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 204 #endif 205 206 /* 207 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 208 * plus a little space for growth. 209 */ 210 #if TRUSTED_BOARD_BOOT || MEASURED_BOOT 211 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 212 #else 213 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 214 #endif 215 216 /* 217 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 218 * little space for growth. 219 */ 220 #if TRUSTED_BOARD_BOOT 221 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 222 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x20000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 223 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 224 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 225 #else 226 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 227 #endif 228 #else 229 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 230 #endif 231 232 /* 233 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 234 * calculated using the current BL31 PROGBITS debug size plus the sizes of 235 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 236 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 237 */ 238 #if TRANSFER_LIST 239 #define PLAT_ARM_MAX_BL31_SIZE (ARM_BL_RAM_SIZE - PLAT_ARM_FW_HANDOFF_SIZE) 240 #else 241 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 242 #endif 243 244 #if JUNO_AARCH32_EL3_RUNTIME 245 /* 246 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 247 * calculated using the current BL32 PROGBITS debug size plus the sizes of 248 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 249 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 250 */ 251 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 252 #endif 253 254 /* 255 * Size of cacheable stacks 256 */ 257 #if defined(IMAGE_BL1) 258 # if TRUSTED_BOARD_BOOT 259 # define PLATFORM_STACK_SIZE UL(0x1000) 260 # else 261 # define PLATFORM_STACK_SIZE UL(0x440) 262 # endif 263 #elif defined(IMAGE_BL2) 264 # if TRUSTED_BOARD_BOOT 265 # define PLATFORM_STACK_SIZE UL(0x1000) 266 # else 267 # define PLATFORM_STACK_SIZE UL(0x400) 268 # endif 269 #elif defined(IMAGE_BL2U) 270 # define PLATFORM_STACK_SIZE UL(0x400) 271 #elif defined(IMAGE_BL31) 272 # if PLAT_XLAT_TABLES_DYNAMIC 273 # define PLATFORM_STACK_SIZE UL(0x800) 274 # else 275 # define PLATFORM_STACK_SIZE UL(0x400) 276 # endif 277 #elif defined(IMAGE_BL32) 278 # define PLATFORM_STACK_SIZE UL(0x440) 279 #endif 280 281 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 282 PLAT_SPM_BUF_SIZE) 283 284 /* CCI related constants */ 285 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 286 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 287 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 288 289 /* System timer related constants */ 290 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 291 292 /* TZC related constants */ 293 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 294 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 295 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 296 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 297 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 298 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 299 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 300 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 301 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 302 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 303 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 304 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 305 306 /* TZC related constants */ 307 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 308 309 /* 310 * Required ARM CSS based platform porting definitions 311 */ 312 313 /* GIC related constants (no GICR in GIC-400) */ 314 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 315 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 316 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 317 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 318 319 /* MHU related constants */ 320 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 321 322 #if CSS_USE_SCMI_SDS_DRIVER 323 /* Index of SDS region used in the communication between AP and SCP */ 324 #define SDS_SCP_AP_REGION_ID U(0) 325 #else 326 /* 327 * Base address of the first memory region used for communication between AP 328 * and SCP. Used by the BOM and SCPI protocols. 329 * 330 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 331 * means the SCP/AP configuration data gets overwritten when the AP initiates 332 * communication with the SCP. The configuration data is expected to be a 333 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 334 * which CPU is the primary, according to the shift and mask definitions below. 335 */ 336 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 337 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 338 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 339 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 340 341 /* 342 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 343 * anything else in this memory region and is handed over to the SCP before 344 * BL31 is loaded over the top. 345 */ 346 #if TRANSFER_LIST 347 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 348 + (PAGE_SIZE / 2U)) 349 #endif 350 351 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 352 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 353 354 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 355 356 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 357 CSS_G1S_IRQ_PROPS(grp), \ 358 ARM_G1S_IRQ_PROPS(grp), \ 359 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 360 (grp), GIC_INTR_CFG_LEVEL), \ 361 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 362 (grp), GIC_INTR_CFG_LEVEL), \ 363 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 364 (grp), GIC_INTR_CFG_LEVEL), \ 365 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 366 (grp), GIC_INTR_CFG_LEVEL), \ 367 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 368 (grp), GIC_INTR_CFG_LEVEL), \ 369 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 370 (grp), GIC_INTR_CFG_LEVEL), \ 371 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 372 (grp), GIC_INTR_CFG_LEVEL), \ 373 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 374 (grp), GIC_INTR_CFG_LEVEL) 375 376 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 377 378 /* 379 * Required ARM CSS SoC based platform porting definitions 380 */ 381 382 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 383 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 384 385 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 386 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 387 388 /* System power domain level */ 389 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 390 391 /* 392 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 393 */ 394 #ifdef __aarch64__ 395 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 396 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 397 #else 398 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 399 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 400 #endif 401 402 #if defined(IMAGE_BL1) && TRANSFER_LIST 403 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200) 404 #else 405 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 406 #endif 407 408 /* Number of SCMI channels on the platform */ 409 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 410 411 /* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */ 412 #ifdef JUNO_ETHOSN_TZMP1 413 #define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT 414 #define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT 415 #define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT 416 417 #define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS 418 #define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS 419 420 #define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE 421 #define ETHOSN_NPU_FW_IMAGE_LIMIT \ 422 (JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE) 423 #endif 424 425 #endif /* PLATFORM_DEF_H */ 426