1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * This file is limited to include the platform port definitions for the 7 * third generation of platforms. 8 */ 9 10 #ifndef NRD_PLAT_ARM_DEF3_H 11 #define NRD_PLAT_ARM_DEF3_H 12 13 #include <common/tbbr/tbbr_img_def.h> 14 15 #ifndef __ASSEMBLER__ 16 #include <lib/mmio.h> 17 #endif /* __ASSEMBLER__ */ 18 19 #include <plat/arm/common/arm_spm_def.h> 20 #include <plat/common/common_def.h> 21 #include <nrd_css_fw_def3.h> 22 #include <nrd_ros_fw_def3.h> 23 24 /******************************************************************************* 25 * Core count 26 ******************************************************************************/ 27 28 #define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \ 29 PLAT_ARM_CLUSTER_COUNT * \ 30 NRD_MAX_CPUS_PER_CLUSTER * \ 31 NRD_MAX_PE_PER_CPU) 32 33 /******************************************************************************* 34 * PA/VA config 35 ******************************************************************************/ 36 37 #ifdef __aarch64__ 38 #define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \ 39 NRD_CHIP_COUNT) 40 #define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \ 41 NRD_CHIP_COUNT) 42 #else 43 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 44 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 45 #endif 46 47 /******************************************************************************* 48 * XLAT definitions 49 ******************************************************************************/ 50 51 /* 52 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 53 * plat_arm_mmap array defined for each BL stage. In addition to that, on 54 * multi-chip platforms, address regions on each of the remote chips are 55 * also mapped. In BL31, for instance, three address regions on the remote 56 * chips are accessed - secure ram, css device and soc device regions. 57 */ 58 #if defined(IMAGE_BL31) 59 # define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3)) 60 # define MAX_XLAT_TABLES (10 + ((NRD_CHIP_COUNT - 1) * 3)) 61 #elif defined(IMAGE_BL32) 62 # define PLAT_ARM_MMAP_ENTRIES U(8) 63 # define MAX_XLAT_TABLES U(5) 64 #elif defined(IMAGE_BL2) 65 # define PLAT_ARM_MMAP_ENTRIES (16 + (NRD_CHIP_COUNT - 1)) 66 # define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 2)) 67 #else 68 # define PLAT_ARM_MMAP_ENTRIES U(7) 69 # define MAX_XLAT_TABLES U(7) 70 #endif 71 72 /******************************************************************************* 73 * BL sizes 74 ******************************************************************************/ 75 76 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 77 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 78 79 #define PLAT_ARM_MAX_BL1_RW_SIZE NRD_CSS_BL1_RW_SIZE 80 81 /* 82 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 83 * little space for growth. Additional 8KiB space is added per chip in 84 * order to accommodate the additional level of translation required for "TZC" 85 * peripheral access which lies in >4TB address space. 86 * 87 */ 88 #define PLAT_ARM_MAX_BL2_SIZE (NRD_CSS_BL2_SIZE + \ 89 ((NRD_CHIP_COUNT - 1) * 0x2000)) 90 91 #define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \ 92 PLAT_ARM_MAX_BL2_SIZE + \ 93 PLAT_ARM_MAX_BL1_RW_SIZE) 94 95 /******************************************************************************* 96 * BL31 plat param 97 ******************************************************************************/ 98 99 /* Special value used to verify platform parameters from BL2 to BL31 */ 100 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 101 102 /******************************************************************************* 103 * Stack sizes 104 ******************************************************************************/ 105 106 #if defined(IMAGE_BL1) 107 # if TRUSTED_BOARD_BOOT 108 # define PLATFORM_STACK_SIZE UL(0x1000) 109 # else 110 # define PLATFORM_STACK_SIZE UL(0x440) 111 # endif 112 #elif defined(IMAGE_BL2) 113 # if TRUSTED_BOARD_BOOT 114 # define PLATFORM_STACK_SIZE UL(0x1000) 115 # else 116 # define PLATFORM_STACK_SIZE UL(0x400) 117 # endif 118 #elif defined(IMAGE_BL2U) 119 # define PLATFORM_STACK_SIZE UL(0x400) 120 #elif defined(IMAGE_BL31) 121 # if SPM_MM || SPMD_SPM_AT_SEL2 122 # define PLATFORM_STACK_SIZE UL(0x500) 123 # else 124 # define PLATFORM_STACK_SIZE UL(0x400) 125 # endif 126 #elif defined(IMAGE_BL32) 127 # define PLATFORM_STACK_SIZE UL(0x440) 128 #endif 129 130 /******************************************************************************* 131 * Console config 132 ******************************************************************************/ 133 134 #define ARM_CONSOLE_BAUDRATE (115200) 135 136 /* UART related constants */ 137 #define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SECURE_UART_BASE 138 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ 139 140 #define PLAT_ARM_RUN_UART_BASE NRD_CSS_SECURE_UART_BASE 141 #define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ 142 143 #define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SECURE_UART_BASE 144 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ 145 146 /******************************************************************************* 147 * System counter and timer config 148 ******************************************************************************/ 149 150 #define ARM_SYS_CNTCTL_BASE NRD_CSS_GENERIC_REFCLK_BASE 151 #define ARM_SYS_CNTREAD_BASE NRD_CSS_CNTCTL_REFCLK_READFRAME_BASE 152 #define ARM_SYS_TIMCTL_BASE NRD_CSS_SYS_TIMCTL_BASE 153 #define ARM_SYS_CNT_BASE_S NRD_CSS_SECURE_TIMER_CTL_BASE 154 #define ARM_SYS_CNT_BASE_NS NRD_CSS_NS_TIMER_CTL_BASE 155 156 /******************************************************************************* 157 * SRAM and DRAM config for FW 158 ******************************************************************************/ 159 160 #define PLAT_ARM_TRUSTED_ROM_BASE NRD_CSS_SECURE_ROM_BASE 161 #define PLAT_ARM_TRUSTED_ROM_SIZE NRD_CSS_SECURE_ROM_SIZE 162 163 #define PLAT_ARM_DRAM2_BASE NRD_CSS_DRAM2_BASE 164 #define PLAT_ARM_DRAM2_SIZE NRD_CSS_DRAM2_SIZE 165 166 #define PLAT_ARM_TRUSTED_SRAM_SIZE NRD_CSS_SECURE_SRAM_SIZE 167 168 #define PLAT_ARM_NSTIMER_FRAME_ID (0) 169 170 #define PLAT_ARM_NSRAM_BASE NRD_CSS_NS_SRAM_BASE 171 #define PLAT_ARM_NSRAM_SIZE NRD_CSS_NS_SRAM_SIZE 172 173 /******************************************************************************* 174 * Power config 175 ******************************************************************************/ 176 177 /* 178 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 179 * power levels have a 1:1 mapping with the MPIDR affinity levels. 180 */ 181 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 182 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 183 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 184 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 185 186 /* Local power state for power domains in Run state. */ 187 #define ARM_LOCAL_STATE_RUN U(0) 188 /* Local power state for retention. Valid only for CPU power domains */ 189 #define ARM_LOCAL_STATE_RET U(1) 190 /* 191 * Local power state for OFF/power-down. Valid for CPU and cluster power 192 * domains 193 */ 194 #define ARM_LOCAL_STATE_OFF U(2) 195 /* 196 * This macro defines the deepest retention state possible. A higher state 197 * id will represent an invalid or a power down state. 198 */ 199 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 200 /* 201 * This macro defines the deepest power down states possible. Any state ID 202 * higher than this is invalid. 203 */ 204 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 205 206 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 207 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 208 209 /******************************************************************************* 210 * MHU config 211 ******************************************************************************/ 212 213 #define PLAT_CSS_MHU_BASE NRD_CSS_AP_SCP_SECURE_MHU_BASE 214 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 215 216 /******************************************************************************* 217 * Cache config 218 ******************************************************************************/ 219 220 #define ARM_CACHE_WRITEBACK_SHIFT U(6) 221 222 /* 223 * Some data must be aligned on the biggest cache line size in the platform. 224 * This is known only to the platform as it might have a combination of 225 * integrated and external caches. 226 */ 227 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 228 229 /******************************************************************************* 230 * SCMI config 231 ******************************************************************************/ 232 233 /* Number of SCMI channels on the platform */ 234 #define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT 235 236 /******************************************************************************* 237 * GIC/EHF config 238 ******************************************************************************/ 239 240 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 241 #define PLAT_CORE_FAULT_IRQ U(17) 242 243 /* ARM platforms use 3 upper bits of secure interrupt priority */ 244 #define PLAT_PRI_BITS U(3) 245 246 #if ENABLE_FEAT_RAS && FFH_SUPPORT 247 #define PLAT_RAS_PRI U(0x10) 248 #endif 249 250 #if ENABLE_FEAT_RAS && FFH_SUPPORT 251 #define PLAT_SP_PRI PLAT_RAS_PRI 252 #else 253 #define PLAT_SP_PRI U(0x10) 254 #endif 255 256 #define ARM_IRQ_SEC_PHY_TIMER U(29) 257 258 #define ARM_IRQ_SEC_SGI_0 U(8) 259 #define ARM_IRQ_SEC_SGI_1 U(9) 260 #define ARM_IRQ_SEC_SGI_2 U(10) 261 #define ARM_IRQ_SEC_SGI_3 U(11) 262 #define ARM_IRQ_SEC_SGI_4 U(12) 263 #define ARM_IRQ_SEC_SGI_5 U(13) 264 #define ARM_IRQ_SEC_SGI_6 U(14) 265 #define ARM_IRQ_SEC_SGI_7 U(15) 266 267 #define ARM_G0_IRQ_PROPS(grp) \ 268 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, \ 269 (grp), GIC_INTR_CFG_EDGE), \ 270 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 271 (grp), GIC_INTR_CFG_EDGE) 272 273 /* 274 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 275 * terminology. On a GICv2 system or mode, the lists will be merged and treated 276 * as Group 0 interrupts. 277 */ 278 #define ARM_G1S_IRQ_PROPS(grp) \ 279 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 280 (grp), GIC_INTR_CFG_LEVEL), \ 281 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 282 (grp), GIC_INTR_CFG_EDGE), \ 283 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 284 (grp), GIC_INTR_CFG_EDGE), \ 285 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 286 (grp), GIC_INTR_CFG_EDGE), \ 287 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 288 (grp), GIC_INTR_CFG_EDGE), \ 289 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 290 (grp), GIC_INTR_CFG_EDGE), \ 291 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 292 (grp), GIC_INTR_CFG_EDGE) 293 294 #define ARM_G0_IRQ_PROPS(grp) \ 295 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, \ 296 (grp), GIC_INTR_CFG_EDGE), \ 297 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 298 (grp), GIC_INTR_CFG_EDGE) 299 300 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 301 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 302 303 #define PLAT_ARM_GICD_BASE NRD_CSS_GIC_BASE 304 #if (NRD_PLATFORM_VARIANT == 1) 305 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00100000) 306 #else 307 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x001C0000) 308 #endif 309 310 /******************************************************************************* 311 * SDEI config 312 ******************************************************************************/ 313 314 #define PLAT_SDEI_CRITICAL_PRI U(0x60) 315 #define PLAT_SDEI_NORMAL_PRI U(0x70) 316 317 /* SGI used for SDEI signalling */ 318 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 319 320 #if SDEI_IN_FCONF 321 /* ARM SDEI dynamic private event max count */ 322 #define ARM_SDEI_DP_EVENT_MAX_CNT U(3) 323 324 /* ARM SDEI dynamic shared event max count */ 325 #define ARM_SDEI_DS_EVENT_MAX_CNT U(3) 326 #else 327 /* ARM SDEI dynamic private event numbers */ 328 #define ARM_SDEI_DP_EVENT_0 UL(1000) 329 #define ARM_SDEI_DP_EVENT_1 UL(1001) 330 #define ARM_SDEI_DP_EVENT_2 UL(1002) 331 332 /* ARM SDEI dynamic shared event numbers */ 333 #define ARM_SDEI_DS_EVENT_0 UL(2000) 334 #define ARM_SDEI_DS_EVENT_1 UL(2001) 335 #define ARM_SDEI_DS_EVENT_2 UL(2002) 336 337 #define ARM_SDEI_PRIVATE_EVENTS \ 338 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 339 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, \ 340 SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 341 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, \ 342 SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 343 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 344 345 #define ARM_SDEI_SHARED_EVENTS \ 346 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, \ 347 SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 348 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, \ 349 SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 350 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, \ 351 SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 352 #endif /* SDEI_IN_FCONF */ 353 354 /******************************************************************************* 355 * SDS config 356 ******************************************************************************/ 357 358 /* SDS ID for unusable CPU MPID list structure */ 359 #define SDS_ISOLATED_CPU_LIST_ID U(128) 360 361 /* Index of SDS region used in the communication with SCP */ 362 #define SDS_SCP_AP_REGION_ID U(0) 363 364 /******************************************************************************* 365 * SMMUv3 Config 366 ******************************************************************************/ 367 368 /* SMMUv3 root offset register */ 369 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0xA0000) 370 371 /******************************************************************************* 372 * Platform type identification macro 373 ******************************************************************************/ 374 375 /* Platform ID related accessors */ 376 #define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F) 377 #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00) 378 #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00) 379 #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08) 380 #define BOARD_CSS_PLAT_TYPE_RTL U(0x00) 381 #define BOARD_CSS_PLAT_TYPE_FPGA U(0x01) 382 #define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02) 383 #define BOARD_CSS_PLAT_TYPE_FVP U(0x03) 384 385 #ifndef __ASSEMBLER__ 386 #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 387 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 388 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 389 #endif /* __ASSEMBLER__ */ 390 391 /* Platform ID address */ 392 #define BOARD_CSS_PLAT_ID_REG_ADDR NRD_ROS_PLATFORM_PERIPH_BASE + \ 393 UL(0x00FE00E0) 394 395 /******************************************************************************* 396 * Flash config 397 ******************************************************************************/ 398 399 #define MAX_IO_DEVICES U(3) 400 #define MAX_IO_HANDLES U(4) 401 402 #define V2M_SYS_LED U(0x8) 403 404 #define V2M_SYS_LED_SS_SHIFT U(0) 405 #define V2M_SYS_LED_EL_SHIFT U(1) 406 #define V2M_SYS_LED_EC_SHIFT U(3) 407 408 #define V2M_SYS_LED_SS_MASK U(0x01) 409 #define V2M_SYS_LED_EL_MASK U(0x03) 410 #define V2M_SYS_LED_EC_MASK U(0x1f) 411 412 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) 413 414 #define V2M_SYSREGS_BASE NRD_ROS_SYSTEM_PERIPH_BASE + \ 415 UL(0x00010000) 416 #define V2M_FLASH0_BASE NRD_ROS_SMC0_BASE 417 #define V2M_FLASH0_SIZE NRD_ROS_SMC0_SIZE 418 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 419 420 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 421 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 422 423 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 424 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 425 426 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 427 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 428 429 /******************************************************************************* 430 * ROS peripheral config 431 ******************************************************************************/ 432 433 /* Non-volatile counters */ 434 #define SOC_TRUSTED_NVCTR_BASE NRD_ROS_PLATFORM_PERIPH_BASE + \ 435 UL(0x00E70000) 436 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 437 #define TFW_NVCTR_SIZE U(4) 438 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 439 #define NTFW_CTR_SIZE U(4) 440 441 /******************************************************************************* 442 * SRAM layout 443 ******************************************************************************/ 444 445 /* if !RESET_TO_BL31 446 * Trusted SRAM 447 * 0x00100000 +--------------+ 448 * | L0 GPT | 449 * 0x000E0000 +--------------+ loaded by BL2 +----------------+ 450 * | BL1 (rw) | <<<<<<<<<<<<< | | 451 * |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 452 * | BL2 | <<<<<<<<<<<<< | | 453 * |--------------| <<<<<<<<<<<<< |----------------| 454 * | | <<<<<<<<<<<<< | BL31 PROGBITS | 455 * | | +----------------+ 456 * +--------------+ 457 * | CONFIG | 458 * 0x0001A000 +--------------+ 459 * | Shared | 460 * 0x00019000 +--------------+ 461 * | BL1 (ro) | 462 * 0x00000000 +--------------+ 463 * 464 * else 465 * 466 * Trusted SRAM 467 * 0x00100000 +--------------+ 468 * | L0 GPT | 469 * 0x000E0000 +-------------- 470 * | | side-loaded +----------------+ 471 * | | <<<<<<<<<<<<< | | 472 * | | <<<<<<<<<<<<< | BL31 NOBITS | 473 * | | <<<<<<<<<<<<< | | 474 * | | <<<<<<<<<<<<< |----------------| 475 * | | <<<<<<<<<<<<< | BL31 PROGBITS | 476 * 0x00063000 | | +----------------+ 477 * 0x0001A000 +--------------+ 478 * | Shared | 479 * 0x00019000 +--------------+ 480 * | BL1 (ro) | 481 * 0x00000000 +--------------+ 482 * endif 483 */ 484 485 /******************************************************************************* 486 * BL1 RO specifics 487 ******************************************************************************/ 488 489 /* 490 * SRAM region to store BL1 code and RO. This has been carved out at the bottom 491 * of SRAM 492 */ 493 494 #define BL1_RO_BASE NRD_CSS_BL1_RO_BASE 495 #define BL1_RO_LIMIT (NRD_CSS_BL1_RO_BASE \ 496 + NRD_CSS_BL1_RO_SIZE) 497 498 /******************************************************************************* 499 * L0 GPT specifics 500 ******************************************************************************/ 501 502 /* 503 * L0 GPT has to be aligned to its size. In order to avoid holes due to 504 * alignment, place L0 GPT at the top of SRAM. 505 */ 506 #define ARM_L0_GPT_SIZE UL(0x00020000) /* 128KB */ 507 #define ARM_L0_GPT_BASE NRD_CSS_SHARED_SRAM_SIZE - \ 508 ARM_L0_GPT_SIZE 509 510 /******************************************************************************* 511 * Arm shared RAM specifics 512 ******************************************************************************/ 513 514 #define ARM_SHARED_RAM_BASE (NRD_CSS_BL1_RO_BASE + \ 515 NRD_CSS_BL1_RO_SIZE) 516 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 517 518 /******************************************************************************* 519 * Arm BL RAM specifics 520 ******************************************************************************/ 521 522 /*Rest of SRAM till L0 GPT base */ 523 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 524 ARM_SHARED_RAM_SIZE) 525 #define ARM_BL_RAM_SIZE (ARM_L0_GPT_BASE - \ 526 ARM_BL_RAM_BASE) 527 528 /******************************************************************************* 529 * FW_CONFIG specifics 530 ******************************************************************************/ 531 532 /* 533 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 534 * and limit. Leave enough space of BL2 meminfo. 535 */ 536 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 537 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 538 + (PAGE_SIZE / 2U)) 539 540 /* 541 * Boot parameters passed from BL2 to BL31/BL32 are stored here 542 */ 543 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 544 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 545 + (PAGE_SIZE / 2U)) 546 547 /* 548 * Define limit of firmware configuration memory: 549 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 550 */ 551 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 552 #if RESET_TO_BL31 553 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE) 554 #else 555 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 556 #endif 557 558 /******************************************************************************* 559 * BL1 RW specifics 560 ******************************************************************************/ 561 562 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 563 ARM_BL_RAM_SIZE - \ 564 PLAT_ARM_MAX_BL1_RW_SIZE) 565 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 566 ARM_BL_RAM_SIZE) 567 568 /******************************************************************************* 569 * BL2 specific defines. 570 ******************************************************************************/ 571 572 /* Put BL2 just below BL1. */ 573 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 574 #define BL2_LIMIT BL1_RW_BASE 575 576 /******************************************************************************* 577 * BL31 specific defines. 578 ******************************************************************************/ 579 580 /* Keep BL31 below BL2 in the Trusted SRAM.*/ 581 #if RESET_TO_BL31 582 #define BL31_BASE (0x63000) 583 #else 584 #define BL31_BASE ((ARM_BL_RAM_BASE + \ 585 ARM_BL_RAM_SIZE) - \ 586 PLAT_ARM_MAX_BL31_SIZE) 587 #endif 588 #define BL31_PROGBITS_LIMIT BL2_BASE 589 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 590 591 /* 592 * The max number of regions like RO(code), coherent and data required by 593 * different BL stages which need to be mapped in the MMU. 594 */ 595 #define ARM_BL_REGIONS 7 596 597 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 598 ARM_BL_REGIONS) 599 600 /******************************************************************************* 601 * DRAM layout 602 ******************************************************************************/ 603 604 /* 605 * The top 100MB of DRAM1 is configured as follows: 606 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 607 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 608 * - REALM DRAM: Reserved for Realm world if RME is enabled 609 * - BL32: Carveout for BL32 image if BL32 is present 610 * 611 * DRAM layout 612 * +------------------+ 613 * | | 614 * | BL32 | 615 * +------------------+ 616 * | REALM (RMM) | 617 * | (32MB - 4KB) | 618 * +------------------+ 619 * | | 620 * | TF-A <-> RMM | 621 * | SHARED (4KB) | 622 * +------------------+ 623 * | L1 GPT | 624 * | | 625 * DRAM1 End +------------------+ 626 */ 627 628 /* Number of DRAM banks */ 629 #if (NRD_PLATFORM_VARIANT == 2) 630 #define ARM_DRAM_NUM_BANKS U(8) 631 #else 632 #define ARM_DRAM_NUM_BANKS U(2) 633 #endif 634 635 /******************************************************************************* 636 * DRAM bank1 specific defines. 637 ******************************************************************************/ 638 639 /* Bank-1 DRAM */ 640 #define ARM_DRAM1_BASE UL(0x80000000) 641 #define ARM_DRAM1_SIZE UL(0x80000000) 642 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 643 ARM_DRAM1_SIZE - 1U) 644 645 /******************************************************************************* 646 * DRAM bank2 specific defines. 647 ******************************************************************************/ 648 649 /* Bank-2 DRAM */ 650 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 651 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 652 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 653 ARM_DRAM2_SIZE - 1U) 654 655 /******************************************************************************* 656 * L1GPT specific defines. 657 ******************************************************************************/ 658 659 /* 2MB per L1 entry, PPS - 48 bits, PGS - 4KB, L0GPTSZ - 16GB */ 660 #define ARM_L1_GPT_SIZE (UL(40 * 1024 * 1024) + \ 661 ((NRD_CHIP_COUNT - 1) * \ 662 (4 * 1024 * 1024))) 663 664 #define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \ 665 ARM_DRAM1_SIZE - \ 666 ARM_L1_GPT_SIZE) 667 #define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \ 668 ARM_L1_GPT_SIZE - 1U) 669 670 /******************************************************************************* 671 * "RMM TF-A shared region" specific defines. 672 ******************************************************************************/ 673 674 /* PLAT_ARM_EL3_RMM_SHARED_SIZE */ 675 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 676 677 #define ARM_EL3_RMM_SHARED_BASE (ARM_L1_GPT_BASE - \ 678 ARM_EL3_RMM_SHARED_SIZE) 679 680 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 681 ARM_EL3_RMM_SHARED_SIZE - 1U) 682 683 /******************************************************************************* 684 * RMM specific defines. 685 ******************************************************************************/ 686 687 /* ARM_REALM_SIZE */ 688 #define ARM_REALM_SIZE (UL(0x02600000) - \ 689 ARM_EL3_RMM_SHARED_SIZE) 690 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 691 ARM_REALM_SIZE) 692 693 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 694 695 #define RMM_BASE (ARM_REALM_BASE) 696 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 697 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 698 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 699 700 /******************************************************************************* 701 * S-EL2 SPMC region defines. 702 ******************************************************************************/ 703 /* BL32 (1500KB) + PLAT_ARM_SP_MAX_SIZE (3MB) + SP HEAP (5MB) */ 704 /* 9692KB */ 705 #define PLAT_ARM_SPMC_SIZE (UL(1500 * 1024) + UL(0x300000) + UL(0x500000)) 706 #define PLAT_ARM_SPMC_BASE (RMM_BASE - PLAT_ARM_SPMC_SIZE) 707 708 /******************************************************************************* 709 * NRD_CSS_CARVEOUT_RESERVED region specific defines. 710 ******************************************************************************/ 711 712 #define NRD_CSS_CARVEOUT_RESERVED_BASE (ARM_DRAM1_BASE + \ 713 ARM_DRAM1_SIZE - \ 714 NRD_CSS_DRAM1_CARVEOUT_SIZE) 715 #define NRD_CSS_CARVEOUT_RESERVED_SIZE (NRD_CSS_DRAM1_CARVEOUT_SIZE - \ 716 (ARM_EL3_RMM_SHARED_SIZE + \ 717 ARM_REALM_SIZE + \ 718 ARM_L1_GPT_SIZE + \ 719 PLAT_ARM_SPMC_SIZE)) 720 721 #define NRD_CSS_CARVEOUT_RESERVED_END (NRD_CSS_CARVEOUT_RESERVED_BASE +\ 722 NRD_CSS_CARVEOUT_RESERVED_SIZE - 1U) 723 724 /******************************************************************************* 725 * BL32 specific defines for EL3 runtime in AArch64 mode 726 ******************************************************************************/ 727 728 #if SPD_spmd && SPMD_SPM_AT_SEL2 729 # define BL32_BASE PLAT_ARM_SPMC_BASE 730 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 731 PLAT_ARM_SPMC_SIZE) 732 733 #if RESET_TO_BL31 734 # define PLAT_ARM_SPMC_MANIFEST_BASE UL(0x1F500) 735 # define ARM_SPMC_MANIFEST_BASE PLAT_ARM_SPMC_MANIFEST_BASE 736 #endif 737 738 # endif 739 740 /******************************************************************************* 741 * NS RAM specific defines specific defines. 742 ******************************************************************************/ 743 744 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 745 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 746 NRD_CSS_DRAM1_CARVEOUT_SIZE) 747 748 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 749 ARM_NS_DRAM1_SIZE - 1U) 750 751 /******************************************************************************* 752 * Secure Partition specific defines. 753 ******************************************************************************/ 754 755 #define PLAT_ARM_SP_MAX_SIZE U(0x300000) /* 3MB */ 756 757 /******************************************************************************* 758 * MMU mapping 759 ******************************************************************************/ 760 761 #define V2M_MAP_FLASH0_RW \ 762 MAP_REGION_FLAT( \ 763 V2M_FLASH0_BASE, \ 764 V2M_FLASH0_SIZE, \ 765 MT_DEVICE | MT_RW | EL3_PAS) 766 767 #define V2M_MAP_FLASH0_RO \ 768 MAP_REGION_FLAT( \ 769 V2M_FLASH0_BASE, \ 770 V2M_FLASH0_SIZE, \ 771 MT_RO_DATA | EL3_PAS) 772 773 #define ARM_MAP_L0_GPT_REGION \ 774 MAP_REGION_FLAT( \ 775 ARM_L0_GPT_BASE, \ 776 ARM_L0_GPT_SIZE, \ 777 MT_MEMORY | MT_RW | MT_ROOT) 778 779 #define ARM_MAP_BL_CONFIG_REGION \ 780 MAP_REGION_FLAT( \ 781 ARM_BL_RAM_BASE, \ 782 (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \ 783 MT_MEMORY | MT_RW | EL3_PAS) 784 785 #if SEPARATE_CODE_AND_RODATA 786 #define ARM_MAP_BL_RO \ 787 MAP_REGION_FLAT( \ 788 BL_CODE_BASE, \ 789 (BL_CODE_END - BL_CODE_BASE), \ 790 MT_CODE | EL3_PAS), \ 791 MAP_REGION_FLAT( \ 792 BL_RO_DATA_BASE, \ 793 (BL_RO_DATA_END - BL_RO_DATA_BASE), \ 794 MT_RO_DATA | EL3_PAS) 795 #else 796 #define ARM_MAP_BL_RO \ 797 MAP_REGION_FLAT( \ 798 BL_CODE_BASE, \ 799 (BL_CODE_END - BL_CODE_BASE), \ 800 MT_CODE | EL3_PAS) 801 #endif 802 803 #if USE_COHERENT_MEM 804 #define ARM_MAP_BL_COHERENT_RAM \ 805 MAP_REGION_FLAT( \ 806 BL_COHERENT_RAM_BASE, \ 807 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 808 MT_DEVICE | MT_RW | EL3_PAS) 809 #endif 810 811 #define ARM_MAP_DRAM2 \ 812 MAP_REGION_FLAT( \ 813 ARM_DRAM2_BASE, \ 814 ARM_DRAM2_SIZE, \ 815 MT_MEMORY | MT_RW | MT_NS) 816 817 #endif /* NRD_PLAT_ARM_DEF3_H */ 818