1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16 #define _RTL8188E_PHYCFG_C_
17
18 #include <drv_types.h>
19 #include <rtl8188e_hal.h>
20
21
22 /*---------------------------Define Local Constant---------------------------*/
23 /* Channel switch:The size of command tables for switch channel*/
24 #define MAX_PRECMD_CNT 16
25 #define MAX_RFDEPENDCMD_CNT 16
26 #define MAX_POSTCMD_CNT 16
27
28 #define MAX_DOZE_WAITING_TIMES_9x 64
29
30 /*---------------------------Define Local Constant---------------------------*/
31
32
33 /*------------------------Define global variable-----------------------------*/
34
35 /*------------------------Define local variable------------------------------*/
36
37
38 /*--------------------Define export function prototype-----------------------*/
39 /* Please refer to header file
40 *--------------------Define export function prototype-----------------------*/
41
42 /*----------------------------Function Body----------------------------------*/
43 /*
44 * 1. BB register R/W API
45 * */
46
47 #if (SIC_ENABLE == 1)
48 static BOOLEAN
sic_IsSICReady(PADAPTER Adapter)49 sic_IsSICReady(
50 PADAPTER Adapter
51 )
52 {
53 BOOLEAN bRet = _FALSE;
54 u32 retryCnt = 0;
55 u8 sic_cmd = 0xff;
56
57 while (1) {
58 if (retryCnt++ >= SIC_MAX_POLL_CNT) {
59 /* RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return FALSE\n")); */
60 return _FALSE;
61 }
62
63 /* if(RT_SDIO_CANNOT_IO(Adapter)) */
64 /* return _FALSE; */
65
66 sic_cmd = rtw_read8(Adapter, SIC_CMD_REG);
67 /* sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG); */
68 #if (SIC_HW_SUPPORT == 1)
69 sic_cmd &= 0xf0; /* [7:4] */
70 #endif
71 /* RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd)); */
72 if (sic_cmd == SIC_CMD_READY)
73 return _TRUE;
74 else {
75 rtw_msleep_os(1);
76 /* delay_ms(1); */
77 }
78 }
79
80 return bRet;
81 }
82
83 /*
84 u32
85 sic_CalculateBitShift(
86 u32 BitMask
87 )
88 {
89 u32 i;
90
91 for(i=0; i<=31; i++)
92 {
93 if ( ((BitMask>>i) & 0x1 ) == 1)
94 break;
95 }
96
97 return i;
98 }
99 */
100
101 static u32
sic_Read4Byte(void * Adapter,u32 offset)102 sic_Read4Byte(
103 void *Adapter,
104 u32 offset
105 )
106 {
107 u32 u4ret = 0xffffffff;
108 #if RTL8188E_SUPPORT == 1
109 u8 retry = 0;
110 #endif
111
112 /* RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset)); */
113
114 if (sic_IsSICReady(Adapter)) {
115 #if (SIC_HW_SUPPORT == 1)
116 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);
117 /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD); */
118 /* RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD)); */
119 #endif
120 rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset & 0xff));
121 /* PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); */
122 /* RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u8)(offset&0xff))); */
123 rtw_write8(Adapter, SIC_ADDR_REG + 1, (u8)((offset & 0xff00) >> 8));
124 /* PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); */
125 /* RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8))); */
126 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_READ);
127 /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ); */
128 /* RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ)); */
129
130 #if RTL8188E_SUPPORT == 1
131 retry = 4;
132 while (retry--) {
133 rtw_udelay_os(50);
134 /* PlatformStallExecution(50); */
135 }
136 #else
137 rtw_udelay_os(200);
138 /* PlatformStallExecution(200); */
139 #endif
140
141 if (sic_IsSICReady(Adapter)) {
142 u4ret = rtw_read32(Adapter, SIC_DATA_REG);
143 /* u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG); */
144 /* RTPRINT(FPHY, PHY_SICR, ("read 0x%x = 0x%x\n", SIC_DATA_REG, u4ret)); */
145 /* DbgPrint("<===Read 0x%x = 0x%x\n", offset, u4ret); */
146 }
147 }
148
149 return u4ret;
150 }
151
152 static void
sic_Write4Byte(void * Adapter,u32 offset,u32 data)153 sic_Write4Byte(
154 void *Adapter,
155 u32 offset,
156 u32 data
157 )
158 {
159 #if RTL8188E_SUPPORT == 1
160 u8 retry = 6;
161 #endif
162 /* DbgPrint("=>Write 0x%x = 0x%x\n", offset, data); */
163 /* RTPRINT(FPHY, PHY_SICW, ("[SIC], sic_Write4Byte(): write offset(%#x)=0x%x\n", offset, data)); */
164 if (sic_IsSICReady(Adapter)) {
165 #if (SIC_HW_SUPPORT == 1)
166 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);
167 /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE); */
168 /* RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREWRITE)); */
169 #endif
170 rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset & 0xff));
171 /* PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); */
172 /* RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", SIC_ADDR_REG, (u8)(offset&0xff))); */
173 rtw_write8(Adapter, SIC_ADDR_REG + 1, (u8)((offset & 0xff00) >> 8));
174 /* PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); */
175 /* RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", (SIC_ADDR_REG+1), (u8)((offset&0xff00)>>8))); */
176 rtw_write32(Adapter, SIC_DATA_REG, (u32)data);
177 /* PlatformEFIOWrite4Byte(Adapter, SIC_DATA_REG, (u32)data); */
178 /* RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_DATA_REG, data)); */
179 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);
180 /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_WRITE); */
181 /* RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_WRITE)); */
182 #if RTL8188E_SUPPORT == 1
183 while (retry--) {
184 rtw_udelay_os(50);
185 /* PlatformStallExecution(50); */
186 }
187 #else
188 rtw_udelay_os(150);
189 /* PlatformStallExecution(150); */
190 #endif
191
192 }
193 }
194 /* ************************************************************
195 * extern function
196 * ************************************************************ */
197 static void
SIC_SetBBReg(PADAPTER Adapter,u32 RegAddr,u32 BitMask,u32 Data)198 SIC_SetBBReg(
199 PADAPTER Adapter,
200 u32 RegAddr,
201 u32 BitMask,
202 u32 Data
203 )
204 {
205 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
206 u32 OriginalValue, BitShift;
207 u16 BBWaitCounter = 0;
208
209 /* RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() start\n")); */
210 #if 0
211 while (PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE) {
212 BBWaitCounter++;
213 delay_ms(10); /* 1 ms */
214
215 if ((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter)) {
216 /* Wait too long, return FALSE to avoid to be stuck here. */
217 RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), Fail to set BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));
218 return;
219 }
220 }
221 #endif
222 /* */
223 /* Critical section start */
224 /* */
225
226 /* RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data)); */
227
228 if (BitMask != bMaskDWord) { /* if not "double word" write */
229 OriginalValue = sic_Read4Byte(Adapter, RegAddr);
230 /* BitShift = sic_CalculateBitShift(BitMask); */
231 BitShift = PHY_CalculateBitShift(BitMask);
232 Data = (((OriginalValue)&(~BitMask)) | (Data << BitShift));
233 }
234
235 sic_Write4Byte(Adapter, RegAddr, Data);
236
237 /* PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE); */
238 /* RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() end\n")); */
239 }
240
241 static u32
SIC_QueryBBReg(PADAPTER Adapter,u32 RegAddr,u32 BitMask)242 SIC_QueryBBReg(
243 PADAPTER Adapter,
244 u32 RegAddr,
245 u32 BitMask
246 )
247 {
248 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
249 u32 ReturnValue = 0, OriginalValue, BitShift;
250 u16 BBWaitCounter = 0;
251
252 /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() start\n")); */
253
254 #if 0
255 while (PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE) {
256 BBWaitCounter++;
257 delay_ms(10); /* 10 ms */
258
259 if ((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter)) {
260 /* Wait too long, return FALSE to avoid to be stuck here. */
261 RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_QueryBBReg(), Fail to query BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));
262 return ReturnValue;
263 }
264 }
265 #endif
266 OriginalValue = sic_Read4Byte(Adapter, RegAddr);
267 /* BitShift = sic_CalculateBitShift(BitMask); */
268 BitShift = PHY_CalculateBitShift(BitMask);
269 ReturnValue = (OriginalValue & BitMask) >> BitShift;
270
271 /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg(), 0x%x=0x%x\n", RegAddr, OriginalValue)); */
272 /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() end\n")); */
273
274 /* PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE); */
275 return ReturnValue;
276 }
277
278 void
SIC_Init(PADAPTER Adapter)279 SIC_Init(
280 PADAPTER Adapter
281 )
282 {
283 /* Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded */
284 /* because for 8723E at beginning 0x1b8=0x1e, that will cause */
285 /* sic always not be ready */
286 #if (SIC_HW_SUPPORT == 1)
287 /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", */
288 /* SIC_INIT_REG, SIC_INIT_VAL)); */
289 rtw_write8(Adapter, SIC_INIT_REG, SIC_INIT_VAL);
290 /* PlatformEFIOWrite1Byte(Adapter, SIC_INIT_REG, SIC_INIT_VAL); */
291 /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", */
292 /* SIC_CMD_REG, SIC_CMD_INIT)); */
293 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_INIT);
294 /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_INIT); */
295 #else
296 /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x1b8~0x1bf = 0x0\n")); */
297 rtw_write32(Adapter, SIC_CMD_REG, 0);
298 /* PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG, 0); */
299 rtw_write32(Adapter, SIC_CMD_REG + 4, 0);
300 /* PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG+4, 0); */
301 #endif
302 }
303
304 static BOOLEAN
SIC_LedOff(PADAPTER Adapter)305 SIC_LedOff(
306 PADAPTER Adapter
307 )
308 {
309 /* When SIC is enabled, led pin will be used as debug pin, */
310 /* so don't execute led function when SIC is enabled. */
311 return _TRUE;
312 }
313 #endif
314
315 /**
316 * Function: PHY_QueryBBReg
317 *
318 * OverView: Read "sepcific bits" from BB register
319 *
320 * Input:
321 * PADAPTER Adapter,
322 * u32 RegAddr, //The target address to be readback
323 * u32 BitMask //The target bit position in the target address
324 * //to be readback
325 * Output: None
326 * Return: u32 Data //The readback register value
327 * Note: This function is equal to "GetRegSetting" in PHY programming guide
328 */
329 u32
PHY_QueryBBReg8188E(PADAPTER Adapter,u32 RegAddr,u32 BitMask)330 PHY_QueryBBReg8188E(
331 PADAPTER Adapter,
332 u32 RegAddr,
333 u32 BitMask
334 )
335 {
336 u32 ReturnValue = 0, OriginalValue, BitShift;
337 u16 BBWaitCounter = 0;
338
339 #if (DISABLE_BB_RF == 1)
340 return 0;
341 #endif
342
343 #if (SIC_ENABLE == 1)
344 return SIC_QueryBBReg(Adapter, RegAddr, BitMask);
345 #endif
346
347
348 OriginalValue = rtw_read32(Adapter, RegAddr);
349 BitShift = PHY_CalculateBitShift(BitMask);
350 ReturnValue = (OriginalValue & BitMask) >> BitShift;
351
352 /* RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue)); */
353
354 return ReturnValue;
355
356 }
357
358
359 /**
360 * Function: PHY_SetBBReg
361 *
362 * OverView: Write "Specific bits" to BB register (page 8~)
363 *
364 * Input:
365 * PADAPTER Adapter,
366 * u32 RegAddr, //The target address to be modified
367 * u32 BitMask //The target bit position in the target address
368 * //to be modified
369 * u32 Data //The new register value in the target bit position
370 * //of the target address
371 *
372 * Output: None
373 * Return: None
374 * Note: This function is equal to "PutRegSetting" in PHY programming guide
375 */
376
377 void
PHY_SetBBReg8188E(PADAPTER Adapter,u32 RegAddr,u32 BitMask,u32 Data)378 PHY_SetBBReg8188E(
379 PADAPTER Adapter,
380 u32 RegAddr,
381 u32 BitMask,
382 u32 Data
383 )
384 {
385 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
386 /* u16 BBWaitCounter = 0; */
387 u32 OriginalValue, BitShift;
388
389 #if (DISABLE_BB_RF == 1)
390 return;
391 #endif
392
393 #if (SIC_ENABLE == 1)
394 SIC_SetBBReg(Adapter, RegAddr, BitMask, Data);
395 return;
396 #endif
397
398
399 if (BitMask != bMaskDWord) { /* if not "double word" write */
400 OriginalValue = rtw_read32(Adapter, RegAddr);
401 BitShift = PHY_CalculateBitShift(BitMask);
402 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
403 }
404
405 rtw_write32(Adapter, RegAddr, Data);
406
407 /* RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data)); */
408
409 }
410
411
412 /*
413 * 2. RF register R/W API
414 *
415 **
416 * Function: phy_RFSerialRead
417 *
418 * OverView: Read regster from RF chips
419 *
420 * Input:
421 * PADAPTER Adapter,
422 enum rf_path eRFPath, //Radio path of A/B/C/D
423 * u32 Offset, //The target address to be read
424 *
425 * Output: None
426 * Return: u32 reback value
427 * Note: Threre are three types of serial operations:
428 * 1. Software serial write
429 * 2. Hardware LSSI-Low Speed Serial Interface
430 * 3. Hardware HSSI-High speed
431 * serial write. Driver need to implement (1) and (2).
432 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
433 */
434 static u32
phy_RFSerialRead(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset)435 phy_RFSerialRead(
436 PADAPTER Adapter,
437 enum rf_path eRFPath,
438 u32 Offset
439 )
440 {
441 u32 retValue = 0;
442 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
443 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
444 u32 NewOffset;
445 u32 tmplong, tmplong2;
446 u8 RfPiEnable = 0;
447
448 _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
449 #if 0
450 if (pHalData->RFChipID == RF_8225 && Offset > 0x24) /* 36 valid regs */
451 return retValue;
452 if (pHalData->RFChipID == RF_8256 && Offset > 0x2D) /* 45 valid regs */
453 return retValue;
454 #endif
455 /* */
456 /* Make sure RF register offset is correct */
457 /* */
458 Offset &= 0xff;
459
460 /* */
461 /* Switch page for 8256 RF IC */
462 /* */
463 NewOffset = Offset;
464
465 /* 2009/06/17 MH We can not execute IO for power save or other accident mode. */
466 /* if(RT_CANNOT_IO(Adapter)) */
467 /* { */
468 /* RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); */
469 /* return 0xFFFFFFFF; */
470 /* } */
471
472 /* For 92S LSSI Read RFLSSIRead */
473 /* For RF A/B write 0x824/82c(does not work in the future) */
474 /* We must use 0x824 for RF A and B to execute read trigger */
475 tmplong = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
476 if (eRFPath == RF_PATH_A)
477 tmplong2 = tmplong;
478 else
479 tmplong2 = phy_query_bb_reg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
480
481 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
482
483 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge));
484 rtw_udelay_os(10);/* PlatformStallExecution(10); */
485
486 phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
487 rtw_udelay_os(100);/* PlatformStallExecution(100); */
488
489 /* phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); */
490 rtw_udelay_os(10);/* PlatformStallExecution(10); */
491
492 if (eRFPath == RF_PATH_A)
493 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
494 else if (eRFPath == RF_PATH_B)
495 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
496
497 if (RfPiEnable) {
498 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
499 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
500 /* RTW_INFO("Readback from RF-PI : 0x%x\n", retValue); */
501 } else {
502 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
503 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
504 /* RTW_INFO("Readback from RF-SI : 0x%x\n", retValue); */
505 }
506 /* RTW_INFO("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); */
507 _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
508 return retValue;
509
510 }
511
512
513
514 /**
515 * Function: phy_RFSerialWrite
516 *
517 * OverView: Write data to RF register (page 8~)
518 *
519 * Input:
520 * PADAPTER Adapter,
521 enum rf_path eRFPath, //Radio path of A/B/C/D
522 * u32 Offset, //The target address to be read
523 * u32 Data //The new register Data in the target bit position
524 * //of the target to be read
525 *
526 * Output: None
527 * Return: None
528 * Note: Threre are three types of serial operations:
529 * 1. Software serial write
530 * 2. Hardware LSSI-Low Speed Serial Interface
531 * 3. Hardware HSSI-High speed
532 * serial write. Driver need to implement (1) and (2).
533 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
534 *
535 * Note: For RF8256 only
536 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
537 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
538 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
539 * programming guide" for more details.
540 * Thus, we define a sub-finction for RTL8526 register address conversion
541 * ===========================================================
542 * Register Mode RegCTL[1] RegCTL[0] Note
543 * (Reg00[12]) (Reg00[10])
544 * ===========================================================
545 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
546 * ------------------------------------------------------------------
547 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
548 * ------------------------------------------------------------------
549 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
550 * ------------------------------------------------------------------
551 *
552 * 2008/09/02 MH Add 92S RF definition
553 *
554 *
555 *
556 */
557 static void
phy_RFSerialWrite(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset,u32 Data)558 phy_RFSerialWrite(
559 PADAPTER Adapter,
560 enum rf_path eRFPath,
561 u32 Offset,
562 u32 Data
563 )
564 {
565 u32 DataAndAddr = 0;
566 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
567 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
568 u32 NewOffset;
569
570 #if 0
571 /* <Roger_TODO> We should check valid regs for RF_6052 case. */
572 if (pHalData->RFChipID == RF_8225 && Offset > 0x24) /* 36 valid regs */
573 return;
574 if (pHalData->RFChipID == RF_8256 && Offset > 0x2D) /* 45 valid regs */
575 return;
576 #endif
577
578 /* 2009/06/17 MH We can not execute IO for power save or other accident mode. */
579 /* if(RT_CANNOT_IO(Adapter)) */
580 /* { */
581 /* RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n")); */
582 /* return; */
583 /* } */
584
585 Offset &= 0xff;
586
587 /* */
588 /* Shadow Update */
589 /* */
590 /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
591
592 /* */
593 /* Switch page for 8256 RF IC */
594 /* */
595 NewOffset = Offset;
596
597 /* */
598 /* Put write addr in [5:0] and write data in [31:16] */
599 /* */
600 /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
601 DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
602
603 /* */
604 /* Write Operation */
605 /* */
606 phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
607 /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
608
609 }
610
611
612 /**
613 * Function: PHY_QueryRFReg
614 *
615 * OverView: Query "Specific bits" to RF register (page 8~)
616 *
617 * Input:
618 * PADAPTER Adapter,
619 enum rf_path eRFPath, //Radio path of A/B/C/D
620 * u32 RegAddr, //The target address to be read
621 * u32 BitMask //The target bit position in the target address
622 * //to be read
623 *
624 * Output: None
625 * Return: u32 Readback value
626 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
627 */
628 u32
PHY_QueryRFReg8188E(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)629 PHY_QueryRFReg8188E(
630 PADAPTER Adapter,
631 enum rf_path eRFPath,
632 u32 RegAddr,
633 u32 BitMask
634 )
635 {
636 u32 Original_Value, Readback_Value, BitShift;
637 /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); */
638 /* u8 RFWaitCounter = 0; */
639 /* _irqL irqL; */
640
641 if (eRFPath >= MAX_RF_PATH)
642 return 0;
643
644 #if (DISABLE_BB_RF == 1)
645 return 0;
646 #endif
647
648
649 #ifdef CONFIG_USB_HCI
650 /* PlatformAcquireMutex(&pHalData->mxRFOperate); */
651 #else
652 /* _enter_critical(&pHalData->rf_lock, &irqL); */
653 #endif
654
655
656 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
657
658 BitShift = PHY_CalculateBitShift(BitMask);
659 Readback_Value = (Original_Value & BitMask) >> BitShift;
660
661 #ifdef CONFIG_USB_HCI
662 /* PlatformReleaseMutex(&pHalData->mxRFOperate); */
663 #else
664 /* _exit_critical(&pHalData->rf_lock, &irqL); */
665 #endif
666
667
668 /* RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask, */
669
670 return Readback_Value;
671 }
672
673 /**
674 * Function: PHY_SetRFReg
675 *
676 * OverView: Write "Specific bits" to RF register (page 8~)
677 *
678 * Input:
679 * PADAPTER Adapter,
680 enum rf_path eRFPath, //Radio path of A/B/C/D
681 * u32 RegAddr, //The target address to be modified
682 * u32 BitMask //The target bit position in the target address
683 * //to be modified
684 * u32 Data //The new register Data in the target bit position
685 * //of the target address
686 *
687 * Output: None
688 * Return: None
689 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
690 */
691 void
PHY_SetRFReg8188E(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)692 PHY_SetRFReg8188E(
693 PADAPTER Adapter,
694 enum rf_path eRFPath,
695 u32 RegAddr,
696 u32 BitMask,
697 u32 Data
698 )
699 {
700
701 /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); */
702 /* u8 RFWaitCounter = 0; */
703 u32 Original_Value, BitShift;
704 /* _irqL irqL; */
705
706 if (eRFPath >= MAX_RF_PATH)
707 return;
708
709 #if (DISABLE_BB_RF == 1)
710 return;
711 #endif
712
713 /* RTPRINT(FINIT, INIT_RF, ("phy_set_rf_reg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", */
714 /* RegAddr, BitMask, Data, eRFPath)); */
715
716
717 #ifdef CONFIG_USB_HCI
718 /* PlatformAcquireMutex(&pHalData->mxRFOperate); */
719 #else
720 /* _enter_critical(&pHalData->rf_lock, &irqL); */
721 #endif
722
723
724 /* RF data is 12 bits only */
725 if (BitMask != bRFRegOffsetMask) {
726 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
727 BitShift = PHY_CalculateBitShift(BitMask);
728 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
729 }
730
731 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
732
733
734 #ifdef CONFIG_USB_HCI
735 /* PlatformReleaseMutex(&pHalData->mxRFOperate); */
736 #else
737 /* _exit_critical(&pHalData->rf_lock, &irqL); */
738 #endif
739
740 /* phy_query_rf_reg(Adapter,eRFPath,RegAddr,BitMask); */
741
742 }
743
744
745 /*
746 * 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
747 * */
748
749 /*-----------------------------------------------------------------------------
750 * Function: PHY_MACConfig8192C
751 *
752 * Overview: Condig MAC by header file or parameter file.
753 *
754 * Input: NONE
755 *
756 * Output: NONE
757 *
758 * Return: NONE
759 *
760 * Revised History:
761 * When Who Remark
762 * 08/12/2008 MHC Create Version 0.
763 *
764 *---------------------------------------------------------------------------*/
PHY_MACConfig8188E(PADAPTER Adapter)765 s32 PHY_MACConfig8188E(PADAPTER Adapter)
766 {
767 int rtStatus = _SUCCESS;
768 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
769 u16 val = 0;
770
771 /* */
772 /* Config MAC */
773 /* */
774 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
775 rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
776 if (rtStatus == _FAIL)
777 #endif
778 {
779 #ifdef CONFIG_EMBEDDED_FWIMG
780 if (HAL_STATUS_FAILURE == odm_config_mac_with_header_file(&pHalData->odmpriv))
781 rtStatus = _FAIL;
782 else
783 rtStatus = _SUCCESS;
784 #endif/* CONFIG_EMBEDDED_FWIMG */
785 }
786
787 /* 2010.07.13 AMPDU aggregation number B */
788 val |= MAX_AGGR_NUM;
789 val = val << 8;
790 val |= MAX_AGGR_NUM;
791 rtw_write16(Adapter, REG_MAX_AGGR_NUM, val);
792 /* rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0B); */
793
794 return rtStatus;
795
796 }
797
798 /*-----------------------------------------------------------------------------
799 * Function: phy_InitBBRFRegisterDefinition
800 *
801 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
802 *
803 * Input:
804 * PADAPTER Adapter,
805 *
806 * Output: None
807 * Return: None
808 * Note: The initialization value is constant and it should never be changes
809 -----------------------------------------------------------------------------*/
810 static void
phy_InitBBRFRegisterDefinition(PADAPTER Adapter)811 phy_InitBBRFRegisterDefinition(
812 PADAPTER Adapter
813 )
814 {
815 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
816
817 /* RF Interface Sowrtware Control */
818 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
819 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
820 pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 LSBs if read 32-bit from 0x874 */
821 pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
822
823 /* RF Interface Output (and Enable) */
824 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
825 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
826
827 /* RF Interface (Output and) Enable */
828 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
829 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
830
831 /* Addr of LSSI. Wirte RF register by driver */
832 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
833 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
834
835 /* Tranceiver A~D HSSI Parameter-2 */
836 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
837 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */
838
839 /* Tranceiver LSSI Readback SI mode */
840 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
841 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
842 pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
843 pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
844
845 /* Tranceiver LSSI Readback PI mode */
846 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
847 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
848 /* pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; */
849 /* pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; */
850
851 }
852
853 static int
phy_BB8188E_Config_ParaFile(PADAPTER Adapter)854 phy_BB8188E_Config_ParaFile(
855 PADAPTER Adapter
856 )
857 {
858 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
859 int rtStatus = _SUCCESS;
860
861 /* */
862 /* 1. Read PHY_REG.TXT BB INIT!! */
863 /* */
864 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
865 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
866 #endif
867 {
868 #ifdef CONFIG_EMBEDDED_FWIMG
869 if (HAL_STATUS_FAILURE == odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
870 rtStatus = _FAIL;
871 #endif
872 }
873
874 if (rtStatus != _SUCCESS) {
875 goto phy_BB8190_Config_ParaFile_Fail;
876 }
877
878 #if (MP_DRIVER == 1)
879 /* */
880 /* 1.1 Read PHY_REG_MP.TXT BB INIT!! */
881 /* */
882 if (Adapter->registrypriv.mp_mode == 1) {
883 /* 3 Read PHY_REG.TXT BB INIT!! */
884 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
885 if (phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP) == _FAIL)
886 #endif
887 {
888 #ifdef CONFIG_EMBEDDED_FWIMG
889 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))
890 rtStatus = _FAIL;
891 #endif
892 }
893
894 if (rtStatus != _SUCCESS) {
895 RTW_INFO("phy_BB8188E_Config_ParaFile():Write BB Reg MP Fail!!");
896 goto phy_BB8190_Config_ParaFile_Fail;
897 }
898 }
899 #endif /* #if (MP_DRIVER == 1) */
900
901 /* */
902 /* 3. BB AGC table Initialization */
903 /* */
904 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
905 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
906 #endif
907 {
908 #ifdef CONFIG_EMBEDDED_FWIMG
909 if (HAL_STATUS_FAILURE == odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
910 rtStatus = _FAIL;
911 #endif
912 }
913
914 if (rtStatus != _SUCCESS) {
915 goto phy_BB8190_Config_ParaFile_Fail;
916 }
917
918
919 phy_BB8190_Config_ParaFile_Fail:
920
921 return rtStatus;
922 }
923
924
925 int
PHY_BBConfig8188E(PADAPTER Adapter)926 PHY_BBConfig8188E(
927 PADAPTER Adapter
928 )
929 {
930 int rtStatus = _SUCCESS;
931 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
932 u32 RegVal;
933 u8 TmpU1B = 0;
934 u8 value8;
935
936 phy_InitBBRFRegisterDefinition(Adapter);
937
938
939 /* Enable BB and RF */
940 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
941 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT13 | BIT0 | BIT1));
942
943 /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
944 /* rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83); */
945 /* rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb); */
946
947 rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
948
949 #ifdef CONFIG_USB_HCI
950 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
951 #elif defined CONFIG_PCI_HCI
952 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
953 #endif
954
955 #if 0
956 #ifdef CONFIG_USB_HCI
957 /* To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23. */
958 rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
959 rtw_write8(Adapter, 0x15, 0xe9);
960 #endif
961
962 rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
963 #endif
964
965 #ifdef CONFIG_USB_HCI
966 /* rtw_write8(Adapter, 0x15, 0xe9); */
967 #endif
968
969
970 #ifdef CONFIG_PCI_HCI
971 #ifdef CONFIG_RTW_LED
972 /* Force use left antenna by default for 88C. */
973 if (adapter_to_led(Adapter)->LedStrategy != SW_LED_MODE10) {
974 RegVal = rtw_read32(Adapter, REG_LEDCFG0);
975 rtw_write32(Adapter, REG_LEDCFG0, RegVal | BIT23);
976 }
977 #endif
978 #endif
979
980 /* */
981 /* Config BB and AGC */
982 /* */
983 rtStatus = phy_BB8188E_Config_ParaFile(Adapter);
984
985 if (rtw_phydm_set_crystal_cap(Adapter, pHalData->crystal_cap) == _FALSE) {
986 RTW_ERR("Init crystal_cap failed\n");
987 rtw_warn_on(1);
988 rtStatus = _FAIL;
989 }
990
991 return rtStatus;
992
993 }
994
995
996 int
PHY_RFConfig8188E(PADAPTER Adapter)997 PHY_RFConfig8188E(
998 PADAPTER Adapter
999 )
1000 {
1001 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1002 int rtStatus = _SUCCESS;
1003
1004 /* */
1005 /* RF config */
1006 /* */
1007 rtStatus = PHY_RF6052_Config8188E(Adapter);
1008 #if 0
1009 switch (pHalData->rf_chip) {
1010 case RF_6052:
1011 rtStatus = PHY_RF6052_Config(Adapter);
1012 break;
1013 case RF_8225:
1014 rtStatus = PHY_RF8225_Config(Adapter);
1015 break;
1016 case RF_8256:
1017 rtStatus = PHY_RF8256_Config(Adapter);
1018 break;
1019 case RF_8258:
1020 break;
1021 case RF_PSEUDO_11N:
1022 rtStatus = PHY_RF8225_Config(Adapter);
1023 break;
1024 default: /* for MacOs Warning: "RF_TYPE_MIN" not handled in switch */
1025 break;
1026 }
1027 #endif
1028 return rtStatus;
1029 }
1030
1031
1032 /*-----------------------------------------------------------------------------
1033 * Function: PHY_ConfigRFWithParaFile()
1034 *
1035 * Overview: This function read RF parameters from general file format, and do RF 3-wire
1036 *
1037 * Input: PADAPTER Adapter
1038 * ps1Byte pFileName
1039 * u8 eRFPath
1040 *
1041 * Output: NONE
1042 *
1043 * Return: RT_STATUS_SUCCESS: configuration file exist
1044 *
1045 * Note: Delay may be required for RF configuration
1046 *---------------------------------------------------------------------------*/
1047 int
rtl8188e_PHY_ConfigRFWithParaFile(PADAPTER Adapter,u8 * pFileName,enum rf_path eRFPath)1048 rtl8188e_PHY_ConfigRFWithParaFile(
1049 PADAPTER Adapter,
1050 u8 *pFileName,
1051 enum rf_path eRFPath
1052 )
1053 {
1054 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1055
1056 int rtStatus = _SUCCESS;
1057
1058
1059 return rtStatus;
1060
1061 }
1062
1063 /* ****************************************
1064 * The following is for High Power PA
1065 * **************************************** */
1066 #define HighPowerRadioAArrayLen 22
1067 /* This is for High power PA */
1068 u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {
1069 0x013, 0x00029ea4,
1070 0x013, 0x00025e74,
1071 0x013, 0x00020ea4,
1072 0x013, 0x0001ced0,
1073 0x013, 0x00019f40,
1074 0x013, 0x00014e70,
1075 0x013, 0x000106a0,
1076 0x013, 0x0000c670,
1077 0x013, 0x000082a0,
1078 0x013, 0x00004270,
1079 0x013, 0x00000240,
1080 };
1081
1082 /*-----------------------------------------------------------------------------
1083 * Function: SetTxPowerLevel8190()
1084 *
1085 * Overview: This function is export to "HalCommon" moudule
1086 * We must consider RF path later!!!!!!!
1087 *
1088 * Input: PADAPTER Adapter
1089 * u8 channel
1090 *
1091 * Output: NONE
1092 *
1093 * Return: NONE
1094 * 2008/11/04 MHC We remove EEPROM_93C56.
1095 * We need to move CCX relative code to independet file.
1096 * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
1097 *
1098 *---------------------------------------------------------------------------*/
1099 void
PHY_SetTxPowerLevel8188E(PADAPTER Adapter,u8 Channel)1100 PHY_SetTxPowerLevel8188E(
1101 PADAPTER Adapter,
1102 u8 Channel
1103 )
1104 {
1105 phy_set_tx_power_level_by_path(Adapter, Channel, RF_PATH_A);
1106 }
1107
1108 void
PHY_SetTxPowerIndex_8188E(PADAPTER Adapter,u32 PowerIndex,enum rf_path RFPath,u8 Rate)1109 PHY_SetTxPowerIndex_8188E(
1110 PADAPTER Adapter,
1111 u32 PowerIndex,
1112 enum rf_path RFPath,
1113 u8 Rate
1114 )
1115 {
1116 if (RFPath == RF_PATH_A) {
1117 switch (Rate) {
1118 case MGN_1M:
1119 phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
1120 break;
1121 case MGN_2M:
1122 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
1123 break;
1124 case MGN_5_5M:
1125 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
1126 break;
1127 case MGN_11M:
1128 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
1129 break;
1130
1131 case MGN_6M:
1132 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
1133 break;
1134 case MGN_9M:
1135 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
1136 break;
1137 case MGN_12M:
1138 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
1139 break;
1140 case MGN_18M:
1141 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
1142 break;
1143
1144 case MGN_24M:
1145 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
1146 break;
1147 case MGN_36M:
1148 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
1149 break;
1150 case MGN_48M:
1151 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
1152 break;
1153 case MGN_54M:
1154 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
1155 break;
1156
1157 case MGN_MCS0:
1158 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
1159 break;
1160 case MGN_MCS1:
1161 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
1162 break;
1163 case MGN_MCS2:
1164 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
1165 break;
1166 case MGN_MCS3:
1167 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
1168 break;
1169
1170 case MGN_MCS4:
1171 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
1172 break;
1173 case MGN_MCS5:
1174 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
1175 break;
1176 case MGN_MCS6:
1177 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
1178 break;
1179 case MGN_MCS7:
1180 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
1181 break;
1182
1183 case MGN_MCS8:
1184 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte0, PowerIndex);
1185 break;
1186 case MGN_MCS9:
1187 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte1, PowerIndex);
1188 break;
1189 case MGN_MCS10:
1190 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte2, PowerIndex);
1191 break;
1192 case MGN_MCS11:
1193 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte3, PowerIndex);
1194 break;
1195
1196 case MGN_MCS12:
1197 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte0, PowerIndex);
1198 break;
1199 case MGN_MCS13:
1200 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte1, PowerIndex);
1201 break;
1202 case MGN_MCS14:
1203 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte2, PowerIndex);
1204 break;
1205 case MGN_MCS15:
1206 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte3, PowerIndex);
1207 break;
1208
1209 default:
1210 RTW_INFO("Invalid Rate!!\n");
1211 break;
1212 }
1213 } else if (RFPath == RF_PATH_B) {
1214 switch (Rate) {
1215 case MGN_1M:
1216 phy_set_bb_reg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte1, PowerIndex);
1217 break;
1218 case MGN_2M:
1219 phy_set_bb_reg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte2, PowerIndex);
1220 break;
1221 case MGN_5_5M:
1222 phy_set_bb_reg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, PowerIndex);
1223 break;
1224 case MGN_11M:
1225 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, PowerIndex);
1226 break;
1227
1228 case MGN_6M:
1229 phy_set_bb_reg(Adapter, rTxAGC_B_Rate18_06, bMaskByte0, PowerIndex);
1230 break;
1231 case MGN_9M:
1232 phy_set_bb_reg(Adapter, rTxAGC_B_Rate18_06, bMaskByte1, PowerIndex);
1233 break;
1234 case MGN_12M:
1235 phy_set_bb_reg(Adapter, rTxAGC_B_Rate18_06, bMaskByte2, PowerIndex);
1236 break;
1237 case MGN_18M:
1238 phy_set_bb_reg(Adapter, rTxAGC_B_Rate18_06, bMaskByte3, PowerIndex);
1239 break;
1240
1241 case MGN_24M:
1242 phy_set_bb_reg(Adapter, rTxAGC_B_Rate54_24, bMaskByte0, PowerIndex);
1243 break;
1244 case MGN_36M:
1245 phy_set_bb_reg(Adapter, rTxAGC_B_Rate54_24, bMaskByte1, PowerIndex);
1246 break;
1247 case MGN_48M:
1248 phy_set_bb_reg(Adapter, rTxAGC_B_Rate54_24, bMaskByte2, PowerIndex);
1249 break;
1250 case MGN_54M:
1251 phy_set_bb_reg(Adapter, rTxAGC_B_Rate54_24, bMaskByte3, PowerIndex);
1252 break;
1253
1254 case MGN_MCS0:
1255 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte0, PowerIndex);
1256 break;
1257 case MGN_MCS1:
1258 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte1, PowerIndex);
1259 break;
1260 case MGN_MCS2:
1261 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte2, PowerIndex);
1262 break;
1263 case MGN_MCS3:
1264 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte3, PowerIndex);
1265 break;
1266
1267 case MGN_MCS4:
1268 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte0, PowerIndex);
1269 break;
1270 case MGN_MCS5:
1271 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte1, PowerIndex);
1272 break;
1273 case MGN_MCS6:
1274 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte2, PowerIndex);
1275 break;
1276 case MGN_MCS7:
1277 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte3, PowerIndex);
1278 break;
1279
1280 case MGN_MCS8:
1281 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte0, PowerIndex);
1282 break;
1283 case MGN_MCS9:
1284 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte1, PowerIndex);
1285 break;
1286 case MGN_MCS10:
1287 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte2, PowerIndex);
1288 break;
1289 case MGN_MCS11:
1290 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte3, PowerIndex);
1291 break;
1292
1293 case MGN_MCS12:
1294 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte0, PowerIndex);
1295 break;
1296 case MGN_MCS13:
1297 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte1, PowerIndex);
1298 break;
1299 case MGN_MCS14:
1300 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte2, PowerIndex);
1301 break;
1302 case MGN_MCS15:
1303 phy_set_bb_reg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte3, PowerIndex);
1304 break;
1305
1306 default:
1307 RTW_INFO("Invalid Rate!!\n");
1308 break;
1309 }
1310 } else
1311 RTW_INFO("Invalid RFPath!!\n");
1312 }
1313
tx_power_extra_bias(enum rf_path RFPath,u8 Rate,enum channel_width BandWidth,u8 Channel)1314 s8 tx_power_extra_bias(
1315 enum rf_path RFPath,
1316 u8 Rate,
1317 enum channel_width BandWidth,
1318 u8 Channel
1319 )
1320 {
1321 s8 bias = 0;
1322
1323 if (Rate == MGN_2M)
1324 bias = -9;
1325
1326 return bias;
1327 }
1328
1329 u8
PHY_GetTxPowerIndex_8188E(PADAPTER pAdapter,enum rf_path RFPath,u8 Rate,u8 BandWidth,u8 Channel,struct txpwr_idx_comp * tic)1330 PHY_GetTxPowerIndex_8188E(
1331 PADAPTER pAdapter,
1332 enum rf_path RFPath,
1333 u8 Rate,
1334 u8 BandWidth,
1335 u8 Channel,
1336 struct txpwr_idx_comp *tic
1337 )
1338 {
1339 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
1340 struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
1341 s16 power_idx;
1342 u8 pg = 0;
1343 s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0;
1344 BOOLEAN bIn24G = _FALSE;
1345
1346 pg = phy_get_pg_txpwr_idx(pAdapter, RFPath, Rate, RF_1TX, BandWidth, Channel, &bIn24G);
1347
1348 by_rate_diff = PHY_GetTxPowerByRate(pAdapter, BAND_ON_2_4G, RFPath, Rate);
1349 limit = PHY_GetTxPowerLimit(pAdapter, NULL, (u8)(!bIn24G), pHalData->current_channel_bw, RFPath, Rate, RF_1TX, pHalData->current_channel);
1350
1351 tpt_offset = PHY_GetTxPowerTrackingOffset(pAdapter, RFPath, Rate);
1352
1353 if (pAdapter->registrypriv.mp_mode != 1)
1354 extra_bias = tx_power_extra_bias(RFPath, Rate, BandWidth, Channel);
1355
1356 if (tic)
1357 txpwr_idx_comp_set(tic, RF_1TX, pg, by_rate_diff, limit, tpt_offset, extra_bias, 0, 0);
1358
1359 by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff;
1360 power_idx = pg + by_rate_diff + tpt_offset + extra_bias;
1361
1362 if (power_idx < 0)
1363 power_idx = 0;
1364 else if (power_idx > hal_spec->txgi_max)
1365 power_idx = hal_spec->txgi_max;
1366
1367 return power_idx;
1368 }
1369
1370 void
PHY_ScanOperationBackup8188E(PADAPTER Adapter,u8 Operation)1371 PHY_ScanOperationBackup8188E(
1372 PADAPTER Adapter,
1373 u8 Operation
1374 )
1375 {
1376 #if 0
1377 IO_TYPE IoType;
1378
1379 if (!rtw_is_drv_stopped(padapter)) {
1380 switch (Operation) {
1381 case SCAN_OPT_BACKUP:
1382 IoType = IO_CMD_PAUSE_DM_BY_SCAN;
1383 rtw_hal_set_hwreg(Adapter, HW_VAR_IO_CMD, (u8 *)&IoType);
1384
1385 break;
1386
1387 case SCAN_OPT_RESTORE:
1388 IoType = IO_CMD_RESUME_DM_BY_SCAN;
1389 rtw_hal_set_hwreg(Adapter, HW_VAR_IO_CMD, (u8 *)&IoType);
1390 break;
1391
1392 default:
1393 break;
1394 }
1395 }
1396 #endif
1397 }
1398 void
phy_SpurCalibration_8188E(PADAPTER Adapter)1399 phy_SpurCalibration_8188E(
1400 PADAPTER Adapter
1401 )
1402 {
1403 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1404 struct dm_struct *p_dm_odm = &(pHalData->odmpriv);
1405
1406 /* DbgPrint("===> phy_SpurCalibration_8188E current_channel_bw = %d, current_channel = %d\n", pHalData->current_channel_bw, pHalData->current_channel);*/
1407 if (pHalData->current_channel_bw == CHANNEL_WIDTH_20 && (pHalData->current_channel == 13 || pHalData->current_channel == 14)) {
1408 phy_set_bb_reg(Adapter, rOFDM0_RxDSP, BIT(9), 0x1);/* enable notch filter */
1409 phy_set_bb_reg(Adapter, rOFDM1_IntfDet, BIT(8) | BIT(7) | BIT(6), 0x2); /* intf_TH */
1410 phy_set_bb_reg(Adapter, rOFDM0_RxDSP, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x1f);
1411 p_dm_odm->is_rx_blocking_en = false;
1412 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40 && pHalData->current_channel == 11) {
1413 phy_set_bb_reg(Adapter, rOFDM0_RxDSP, BIT(9), 0x1);/* enable notch filter */
1414 phy_set_bb_reg(Adapter, rOFDM1_IntfDet, BIT(8) | BIT(7) | BIT(6), 0x2); /* intf_TH */
1415 phy_set_bb_reg(Adapter, rOFDM0_RxDSP, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x1f);
1416 p_dm_odm->is_rx_blocking_en = false;
1417 } else {
1418 if (Adapter->registrypriv.notch_filter == 0)
1419 phy_set_bb_reg(Adapter, rOFDM0_RxDSP, BIT(9), 0x0);/* disable notch filter */
1420 }
1421 }
1422
1423 /*-----------------------------------------------------------------------------
1424 * Function: PHY_SetBWModeCallback8192C()
1425 *
1426 * Overview: Timer callback function for SetSetBWMode
1427 *
1428 * Input: PRT_TIMER pTimer
1429 *
1430 * Output: NONE
1431 *
1432 * Return: NONE
1433 *
1434 * Note: (1) We do not take j mode into consideration now
1435 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
1436 * concurrently?
1437 *---------------------------------------------------------------------------*/
1438 static void
_PHY_SetBWMode88E(PADAPTER Adapter)1439 _PHY_SetBWMode88E(
1440 PADAPTER Adapter
1441 )
1442 {
1443 /* PADAPTER Adapter = (PADAPTER)pTimer->Adapter; */
1444 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1445 u8 regBwOpMode;
1446 u8 regRRSR_RSC;
1447
1448 /* return; */
1449
1450 /* Added it for 20/40 mhz switch time evaluation by guangan 070531 */
1451 /* u32 NowL, NowH; */
1452 /* u64 BeginTime, EndTime; */
1453
1454 if (pHalData->rf_chip == RF_PSEUDO_11N) {
1455 /* pHalData->SetBWModeInProgress= _FALSE; */
1456 return;
1457 }
1458
1459 /* There is no 40MHz mode in RF_8225. */
1460 if (pHalData->rf_chip == RF_8225)
1461 return;
1462
1463 if (rtw_is_drv_stopped(Adapter))
1464 return;
1465
1466 /* Added it for 20/40 mhz switch time evaluation by guangan 070531 */
1467 /* NowL = PlatformEFIORead4Byte(Adapter, TSFR); */
1468 /* NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); */
1469 /* BeginTime = ((u64)NowH << 32) + NowL; */
1470
1471 /* 3 */
1472 /* 3 */ /* <1>Set MAC register */
1473 /* 3 */
1474 /* Adapter->hal_func.SetBWModeHandler(); */
1475
1476 regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
1477 regRRSR_RSC = rtw_read8(Adapter, REG_RRSR + 2);
1478 /* regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(u8 *)®BwOpMode); */
1479
1480 switch (pHalData->current_channel_bw) {
1481 case CHANNEL_WIDTH_20:
1482 regBwOpMode |= BW_OPMODE_20MHZ;
1483 /* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
1484 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1485 break;
1486
1487 case CHANNEL_WIDTH_40:
1488 regBwOpMode &= ~BW_OPMODE_20MHZ;
1489 /* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
1490 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1491
1492 regRRSR_RSC = (regRRSR_RSC & 0x90) | (pHalData->nCur40MhzPrimeSC << 5);
1493 rtw_write8(Adapter, REG_RRSR + 2, regRRSR_RSC);
1494 break;
1495
1496 default:
1497 break;
1498 }
1499
1500 /* 3 */
1501 /* 3 */ /* <2>Set PHY related register */
1502 /* 3 */
1503 switch (pHalData->current_channel_bw) {
1504 /* 20 MHz channel*/
1505 case CHANNEL_WIDTH_20:
1506 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
1507 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
1508 /* phy_set_bb_reg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
1509
1510 break;
1511
1512
1513 /* 40 MHz channel*/
1514 case CHANNEL_WIDTH_40:
1515 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
1516 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
1517
1518 /* Set Control channel to upper or lower. These settings are required only for 40MHz */
1519 phy_set_bb_reg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
1520 phy_set_bb_reg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
1521 /* phy_set_bb_reg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); */
1522
1523 phy_set_bb_reg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1524
1525 break;
1526
1527
1528
1529 default:
1530 break;
1531
1532 }
1533 /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
1534
1535 /* Added it for 20/40 mhz switch time evaluation by guangan 070531 */
1536 /* NowL = PlatformEFIORead4Byte(Adapter, TSFR); */
1537 /* NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); */
1538 /* EndTime = ((u64)NowH << 32) + NowL; */
1539
1540 /* 3<3>Set RF related register */
1541 switch (pHalData->rf_chip) {
1542 case RF_8225:
1543 /* PHY_SetRF8225Bandwidth(Adapter, pHalData->current_channel_bw); */
1544 break;
1545
1546 case RF_8256:
1547 /* Please implement this function in Hal8190PciPhy8256.c */
1548 /* PHY_SetRF8256Bandwidth(Adapter, pHalData->current_channel_bw); */
1549 break;
1550
1551 case RF_8258:
1552 /* Please implement this function in Hal8190PciPhy8258.c */
1553 /* PHY_SetRF8258Bandwidth(); */
1554 break;
1555
1556 case RF_PSEUDO_11N:
1557 /* Do Nothing */
1558 break;
1559
1560 case RF_6052:
1561 rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->current_channel_bw);
1562 break;
1563
1564 default:
1565 /* RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); */
1566 break;
1567 }
1568
1569 /* pHalData->SetBWModeInProgress= FALSE; */
1570
1571 }
1572
1573
1574 #if 0
1575 /* -----------------------------------------------------------------------------
1576 * * Function: SetBWMode8190Pci()
1577 * *
1578 * * Overview: This function is export to "HalCommon" moudule
1579 * *
1580 * * Input: PADAPTER Adapter
1581 * * CHANNEL_WIDTH Bandwidth 20M or 40M
1582 * *
1583 * * Output: NONE
1584 * *
1585 * * Return: NONE
1586 * *
1587 * * Note: We do not take j mode into consideration now
1588 * *--------------------------------------------------------------------------- */
1589 #endif
1590 void
PHY_SetBWMode8188E(PADAPTER Adapter,enum channel_width Bandwidth,unsigned char Offset)1591 PHY_SetBWMode8188E(
1592 PADAPTER Adapter,
1593 enum channel_width Bandwidth, /* 20M or 40M */
1594 unsigned char Offset /* Upper, Lower, or Don't care */
1595 )
1596 {
1597 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1598 enum channel_width tmpBW = pHalData->current_channel_bw;
1599 /* Modified it for 20/40 mhz switch by guangan 070531 */
1600 /* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */
1601
1602 /* return; */
1603
1604 /* if(pHalData->SwChnlInProgress)
1605 * if(pMgntInfo->bScanInProgress)
1606 * {
1607 * return;
1608 * } */
1609
1610 /* if(pHalData->SetBWModeInProgress)
1611 * {
1612 * */ /* Modified it for 20/40 mhz switch by guangan 070531
1613 * PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);
1614 * */ /* return;
1615 * } */
1616
1617 /* if(pHalData->SetBWModeInProgress) */
1618 /* return; */
1619
1620 /* pHalData->SetBWModeInProgress= TRUE; */
1621
1622 pHalData->current_channel_bw = Bandwidth;
1623
1624 #if 0
1625 if (Offset == EXTCHNL_OFFSET_LOWER)
1626 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1627 else if (Offset == EXTCHNL_OFFSET_UPPER)
1628 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1629 else
1630 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1631 #else
1632 pHalData->nCur40MhzPrimeSC = Offset;
1633 #endif
1634
1635 if (!RTW_CANNOT_RUN(Adapter)) {
1636 #if 0
1637 /* PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0); */
1638 #else
1639 _PHY_SetBWMode88E(Adapter);
1640 #endif
1641 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
1642 if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
1643 phy_SpurCalibration_8188E(Adapter);
1644 #endif
1645 } else {
1646 /* pHalData->SetBWModeInProgress= FALSE; */
1647 pHalData->current_channel_bw = tmpBW;
1648 }
1649
1650 }
1651
1652
_PHY_SwChnl8188E(PADAPTER Adapter,u8 channel)1653 static void _PHY_SwChnl8188E(PADAPTER Adapter, u8 channel)
1654 {
1655 enum rf_path eRFPath;
1656 u32 param1, param2;
1657 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1658
1659 if (Adapter->bNotifyChannelChange)
1660 RTW_INFO("[%s] ch = %d\n", __FUNCTION__, channel);
1661
1662 /* s1. pre common command - CmdID_SetTxPowerLevel */
1663 rtw_hal_set_tx_power_level(Adapter, channel);
1664
1665 /* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
1666 param1 = RF_CHNLBW;
1667 param2 = channel;
1668 for (eRFPath = RF_PATH_A; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
1669 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
1670 phy_set_rf_reg(Adapter, eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
1671 }
1672
1673
1674 /* s3. post common command - CmdID_End, None */
1675
1676 }
1677 void
PHY_SwChnl8188E(PADAPTER Adapter,u8 channel)1678 PHY_SwChnl8188E(/* Call after initialization */
1679 PADAPTER Adapter,
1680 u8 channel
1681 )
1682 {
1683 /* PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE); */
1684 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1685 u8 tmpchannel = pHalData->current_channel;
1686 BOOLEAN bResult = _TRUE;
1687
1688 if (pHalData->rf_chip == RF_PSEUDO_11N) {
1689 /* pHalData->SwChnlInProgress=FALSE; */
1690 return; /* return immediately if it is peudo-phy */
1691 }
1692
1693 /* if(pHalData->SwChnlInProgress) */
1694 /* return; */
1695
1696 /* if(pHalData->SetBWModeInProgress) */
1697 /* return; */
1698
1699 while (pHalData->odmpriv.rf_calibrate_info.is_lck_in_progress)
1700 rtw_msleep_os(50);
1701
1702 /* -------------------------------------------- */
1703 switch (pHalData->CurrentWirelessMode) {
1704 case WIRELESS_MODE_A:
1705 case WIRELESS_MODE_N_5G:
1706 /* RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14")); */
1707 break;
1708
1709 case WIRELESS_MODE_B:
1710 /* RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14")); */
1711 break;
1712
1713 case WIRELESS_MODE_G:
1714 case WIRELESS_MODE_N_24G:
1715 /* RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14")); */
1716 break;
1717
1718 default:
1719 /* RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode)); */
1720 break;
1721 }
1722 /* -------------------------------------------- */
1723
1724 /* pHalData->SwChnlInProgress = TRUE; */
1725 if (channel == 0)
1726 channel = 1;
1727
1728 pHalData->current_channel = channel;
1729
1730 /* pHalData->SwChnlStage=0; */
1731 /* pHalData->SwChnlStep=0; */
1732
1733 if (!RTW_CANNOT_RUN(Adapter)) {
1734 #if 0
1735 /* PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0); */
1736 #else
1737 _PHY_SwChnl8188E(Adapter, channel);
1738 #endif
1739
1740 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
1741 if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
1742 phy_SpurCalibration_8188E(Adapter);
1743 #endif
1744
1745
1746
1747 if (!bResult) {
1748 /* if(IS_HARDWARE_TYPE_8192SU(Adapter)) */
1749 /* { */
1750 /* pHalData->SwChnlInProgress = FALSE; */
1751 pHalData->current_channel = tmpchannel;
1752 /* } */
1753 }
1754
1755 } else {
1756 /* if(IS_HARDWARE_TYPE_8192SU(Adapter)) */
1757 /* { */
1758 /* pHalData->SwChnlInProgress = FALSE; */
1759 pHalData->current_channel = tmpchannel;
1760 /* } */
1761 }
1762 }
1763
1764 void
PHY_SetSwChnlBWMode8188E(PADAPTER Adapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)1765 PHY_SetSwChnlBWMode8188E(
1766 PADAPTER Adapter,
1767 u8 channel,
1768 enum channel_width Bandwidth,
1769 u8 Offset40,
1770 u8 Offset80
1771 )
1772 {
1773 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1774 /* RTW_INFO("%s()===>\n",__FUNCTION__); */
1775
1776 PHY_SwChnl8188E(Adapter, channel);
1777 PHY_SetBWMode8188E(Adapter, Bandwidth, Offset40);
1778 if (pHalData->bNeedIQK == _TRUE) {
1779 if (pHalData->neediqk_24g == _TRUE) {
1780
1781 halrf_iqk_trigger(&pHalData->odmpriv, _FALSE);
1782 pHalData->bIQKInitialized = _TRUE;
1783 pHalData->neediqk_24g = _FALSE;
1784 }
1785 pHalData->bNeedIQK = _FALSE;
1786 }
1787 /* RTW_INFO("<==%s()\n",__FUNCTION__); */
1788 }
1789
1790
1791 void
PHY_SetRFEReg_8188E(PADAPTER Adapter)1792 PHY_SetRFEReg_8188E(
1793 PADAPTER Adapter
1794 )
1795 {
1796 u8 u1tmp = 0;
1797 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1798
1799 if ((pHalData->ExternalPA_2G == 0) && (pHalData->ExternalLNA_2G == 0))
1800 return;
1801
1802 switch (pHalData->rfe_type) {
1803 /* 88EU rfe_type should always be 0 */
1804 case 0:
1805 default:
1806 phy_set_bb_reg(Adapter, 0x40, BIT2|BIT3, 0x3); /*0x3 << 2*/
1807 phy_set_bb_reg(Adapter, 0xEE8, BIT28, 0x1);
1808 phy_set_bb_reg(Adapter, 0x87C, BIT0, 0x0);
1809 break;
1810 }
1811 }
1812