1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _RTL8188E_PHYCFG_C_
21
22 #include <drv_types.h>
23 #include <rtl8188e_hal.h>
24
25
26 /*---------------------------Define Local Constant---------------------------*/
27 /* Channel switch:The size of command tables for switch channel*/
28 #define MAX_PRECMD_CNT 16
29 #define MAX_RFDEPENDCMD_CNT 16
30 #define MAX_POSTCMD_CNT 16
31
32 #define MAX_DOZE_WAITING_TIMES_9x 64
33
34 /*---------------------------Define Local Constant---------------------------*/
35
36
37 /*------------------------Define global variable-----------------------------*/
38
39 /*------------------------Define local variable------------------------------*/
40
41
42 /*--------------------Define export function prototype-----------------------*/
43 // Please refer to header file
44 /*--------------------Define export function prototype-----------------------*/
45
46 /*----------------------------Function Body----------------------------------*/
47 //
48 // 1. BB register R/W API
49 //
50
51 #if(SIC_ENABLE == 1)
52 static BOOLEAN
sic_IsSICReady(IN PADAPTER Adapter)53 sic_IsSICReady(
54 IN PADAPTER Adapter
55 )
56 {
57 BOOLEAN bRet=_FALSE;
58 u32 retryCnt=0;
59 u8 sic_cmd=0xff;
60
61 while(1)
62 {
63 if(retryCnt++ >= SIC_MAX_POLL_CNT)
64 {
65 //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return FALSE\n"));
66 return _FALSE;
67 }
68
69 //if(RT_SDIO_CANNOT_IO(Adapter))
70 // return _FALSE;
71
72 sic_cmd = rtw_read8(Adapter, SIC_CMD_REG);
73 //sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG);
74 #if(SIC_HW_SUPPORT == 1)
75 sic_cmd &= 0xf0; // [7:4]
76 #endif
77 //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd));
78 if(sic_cmd == SIC_CMD_READY)
79 return _TRUE;
80 else
81 {
82 rtw_msleep_os(1);
83 //delay_ms(1);
84 }
85 }
86
87 return bRet;
88 }
89
90 /*
91 u32
92 sic_CalculateBitShift(
93 u32 BitMask
94 )
95 {
96 u32 i;
97
98 for(i=0; i<=31; i++)
99 {
100 if ( ((BitMask>>i) & 0x1 ) == 1)
101 break;
102 }
103
104 return (i);
105 }
106 */
107
108 static u32
sic_Read4Byte(PVOID Adapter,u32 offset)109 sic_Read4Byte(
110 PVOID Adapter,
111 u32 offset
112 )
113 {
114 u32 u4ret=0xffffffff;
115 #if RTL8188E_SUPPORT == 1
116 u8 retry = 0;
117 #endif
118
119 //RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset));
120
121 if(sic_IsSICReady(Adapter))
122 {
123 #if(SIC_HW_SUPPORT == 1)
124 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);
125 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);
126 //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD));
127 #endif
128 rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));
129 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));
130 //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));
131 rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));
132 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));
133 //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8)));
134 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_READ);
135 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ);
136 //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ));
137
138 #if RTL8188E_SUPPORT == 1
139 retry = 4;
140 while(retry--){
141 rtw_udelay_os(50);
142 //PlatformStallExecution(50);
143 }
144 #else
145 rtw_udelay_os(200);
146 //PlatformStallExecution(200);
147 #endif
148
149 if(sic_IsSICReady(Adapter))
150 {
151 u4ret = rtw_read32(Adapter, SIC_DATA_REG);
152 //u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG);
153 //RTPRINT(FPHY, PHY_SICR, ("read 0x%x = 0x%x\n", SIC_DATA_REG, u4ret));
154 //DbgPrint("<===Read 0x%x = 0x%x\n", offset, u4ret);
155 }
156 }
157
158 return u4ret;
159 }
160
161 static VOID
sic_Write4Byte(PVOID Adapter,u32 offset,u32 data)162 sic_Write4Byte(
163 PVOID Adapter,
164 u32 offset,
165 u32 data
166 )
167 {
168 #if RTL8188E_SUPPORT == 1
169 u8 retry = 6;
170 #endif
171 //DbgPrint("=>Write 0x%x = 0x%x\n", offset, data);
172 //RTPRINT(FPHY, PHY_SICW, ("[SIC], sic_Write4Byte(): write offset(%#x)=0x%x\n", offset, data));
173 if(sic_IsSICReady(Adapter))
174 {
175 #if(SIC_HW_SUPPORT == 1)
176 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);
177 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);
178 //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREWRITE));
179 #endif
180 rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));
181 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));
182 //RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));
183 rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));
184 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));
185 //RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", (SIC_ADDR_REG+1), (u1Byte)((offset&0xff00)>>8)));
186 rtw_write32(Adapter, SIC_DATA_REG, (u32)data);
187 //PlatformEFIOWrite4Byte(Adapter, SIC_DATA_REG, (u4Byte)data);
188 //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_DATA_REG, data));
189 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);
190 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);
191 //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_WRITE));
192 #if RTL8188E_SUPPORT == 1
193 while(retry--){
194 rtw_udelay_os(50);
195 //PlatformStallExecution(50);
196 }
197 #else
198 rtw_udelay_os(150);
199 //PlatformStallExecution(150);
200 #endif
201
202 }
203 }
204 //============================================================
205 // extern function
206 //============================================================
207 static VOID
SIC_SetBBReg(IN PADAPTER Adapter,IN u32 RegAddr,IN u32 BitMask,IN u32 Data)208 SIC_SetBBReg(
209 IN PADAPTER Adapter,
210 IN u32 RegAddr,
211 IN u32 BitMask,
212 IN u32 Data
213 )
214 {
215 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
216 u32 OriginalValue, BitShift;
217 u16 BBWaitCounter = 0;
218
219 //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() start\n"));
220 /*
221 while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE)
222 {
223 BBWaitCounter ++;
224 delay_ms(10); // 1 ms
225
226 if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter))
227 {// Wait too long, return FALSE to avoid to be stuck here.
228 RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), Fail to set BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));
229 return;
230 }
231 }
232 */
233 //
234 // Critical section start
235 //
236
237 //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data));
238
239 if(BitMask!= bMaskDWord){//if not "double word" write
240 OriginalValue = sic_Read4Byte(Adapter, RegAddr);
241 //BitShift = sic_CalculateBitShift(BitMask);
242 BitShift = PHY_CalculateBitShift(BitMask);
243 Data = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
244 }
245
246 sic_Write4Byte(Adapter, RegAddr, Data);
247
248 //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE);
249 //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() end\n"));
250 }
251
252 static u32
SIC_QueryBBReg(IN PADAPTER Adapter,IN u32 RegAddr,IN u32 BitMask)253 SIC_QueryBBReg(
254 IN PADAPTER Adapter,
255 IN u32 RegAddr,
256 IN u32 BitMask
257 )
258 {
259 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
260 u32 ReturnValue = 0, OriginalValue, BitShift;
261 u16 BBWaitCounter = 0;
262
263 //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() start\n"));
264
265 /*
266 while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE)
267 {
268 BBWaitCounter ++;
269 delay_ms(10); // 10 ms
270
271 if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter))
272 {// Wait too long, return FALSE to avoid to be stuck here.
273 RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_QueryBBReg(), Fail to query BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));
274 return ReturnValue;
275 }
276 }
277 */
278 OriginalValue = sic_Read4Byte(Adapter, RegAddr);
279 //BitShift = sic_CalculateBitShift(BitMask);
280 BitShift = PHY_CalculateBitShift(BitMask);
281 ReturnValue = (OriginalValue & BitMask) >> BitShift;
282
283 //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg(), 0x%x=0x%x\n", RegAddr, OriginalValue));
284 //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() end\n"));
285
286 //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE);
287 return (ReturnValue);
288 }
289
290 VOID
SIC_Init(IN PADAPTER Adapter)291 SIC_Init(
292 IN PADAPTER Adapter
293 )
294 {
295 // Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded
296 // because for 8723E at beginning 0x1b8=0x1e, that will cause
297 // sic always not be ready
298 #if(SIC_HW_SUPPORT == 1)
299 //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n",
300 // SIC_INIT_REG, SIC_INIT_VAL));
301 rtw_write8(Adapter, SIC_INIT_REG, SIC_INIT_VAL);
302 //PlatformEFIOWrite1Byte(Adapter, SIC_INIT_REG, SIC_INIT_VAL);
303 //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n",
304 // SIC_CMD_REG, SIC_CMD_INIT));
305 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_INIT);
306 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_INIT);
307 #else
308 //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x1b8~0x1bf = 0x0\n"));
309 rtw_write32(Adapter, SIC_CMD_REG, 0);
310 //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG, 0);
311 rtw_write32(Adapter, SIC_CMD_REG+4, 0);
312 //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG+4, 0);
313 #endif
314 }
315
316 static BOOLEAN
SIC_LedOff(IN PADAPTER Adapter)317 SIC_LedOff(
318 IN PADAPTER Adapter
319 )
320 {
321 // When SIC is enabled, led pin will be used as debug pin,
322 // so don't execute led function when SIC is enabled.
323 return _TRUE;
324 }
325 #endif
326
327 /**
328 * Function: PHY_QueryBBReg
329 *
330 * OverView: Read "sepcific bits" from BB register
331 *
332 * Input:
333 * PADAPTER Adapter,
334 * u4Byte RegAddr, //The target address to be readback
335 * u4Byte BitMask //The target bit position in the target address
336 * //to be readback
337 * Output: None
338 * Return: u4Byte Data //The readback register value
339 * Note: This function is equal to "GetRegSetting" in PHY programming guide
340 */
341 u32
PHY_QueryBBReg8188E(IN PADAPTER Adapter,IN u32 RegAddr,IN u32 BitMask)342 PHY_QueryBBReg8188E(
343 IN PADAPTER Adapter,
344 IN u32 RegAddr,
345 IN u32 BitMask
346 )
347 {
348 u32 ReturnValue = 0, OriginalValue, BitShift;
349 u16 BBWaitCounter = 0;
350
351 #if (DISABLE_BB_RF == 1)
352 return 0;
353 #endif
354
355 #if(SIC_ENABLE == 1)
356 return SIC_QueryBBReg(Adapter, RegAddr, BitMask);
357 #endif
358
359 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));
360
361 OriginalValue = rtw_read32(Adapter, RegAddr);
362 BitShift = PHY_CalculateBitShift(BitMask);
363 ReturnValue = (OriginalValue & BitMask) >> BitShift;
364
365 //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue));
366 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue));
367
368 return (ReturnValue);
369
370 }
371
372
373 /**
374 * Function: PHY_SetBBReg
375 *
376 * OverView: Write "Specific bits" to BB register (page 8~)
377 *
378 * Input:
379 * PADAPTER Adapter,
380 * u4Byte RegAddr, //The target address to be modified
381 * u4Byte BitMask //The target bit position in the target address
382 * //to be modified
383 * u4Byte Data //The new register value in the target bit position
384 * //of the target address
385 *
386 * Output: None
387 * Return: None
388 * Note: This function is equal to "PutRegSetting" in PHY programming guide
389 */
390
391 VOID
PHY_SetBBReg8188E(IN PADAPTER Adapter,IN u32 RegAddr,IN u32 BitMask,IN u32 Data)392 PHY_SetBBReg8188E(
393 IN PADAPTER Adapter,
394 IN u32 RegAddr,
395 IN u32 BitMask,
396 IN u32 Data
397 )
398 {
399 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
400 //u16 BBWaitCounter = 0;
401 u32 OriginalValue, BitShift;
402
403 #if (DISABLE_BB_RF == 1)
404 return;
405 #endif
406
407 #if(SIC_ENABLE == 1)
408 SIC_SetBBReg(Adapter, RegAddr, BitMask, Data);
409 return;
410 #endif
411
412 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
413
414 if(BitMask!= bMaskDWord){//if not "double word" write
415 OriginalValue = rtw_read32(Adapter, RegAddr);
416 BitShift = PHY_CalculateBitShift(BitMask);
417 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
418 }
419
420 rtw_write32(Adapter, RegAddr, Data);
421
422 //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data));
423 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
424
425 }
426
427
428 //
429 // 2. RF register R/W API
430 //
431 /**
432 * Function: phy_RFSerialRead
433 *
434 * OverView: Read regster from RF chips
435 *
436 * Input:
437 * PADAPTER Adapter,
438 * u8 eRFPath, //Radio path of A/B/C/D
439 * u4Byte Offset, //The target address to be read
440 *
441 * Output: None
442 * Return: u4Byte reback value
443 * Note: Threre are three types of serial operations:
444 * 1. Software serial write
445 * 2. Hardware LSSI-Low Speed Serial Interface
446 * 3. Hardware HSSI-High speed
447 * serial write. Driver need to implement (1) and (2).
448 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
449 */
450 static u32
phy_RFSerialRead(IN PADAPTER Adapter,IN u8 eRFPath,IN u32 Offset)451 phy_RFSerialRead(
452 IN PADAPTER Adapter,
453 IN u8 eRFPath,
454 IN u32 Offset
455 )
456 {
457 u32 retValue = 0;
458 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
459 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
460 u32 NewOffset;
461 u32 tmplong,tmplong2;
462 u8 RfPiEnable=0;
463 #if 0
464 if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
465 return retValue;
466 if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
467 return retValue;
468 #endif
469 //
470 // Make sure RF register offset is correct
471 //
472 Offset &= 0xff;
473
474 //
475 // Switch page for 8256 RF IC
476 //
477 NewOffset = Offset;
478
479 // 2009/06/17 MH We can not execute IO for power save or other accident mode.
480 //if(RT_CANNOT_IO(Adapter))
481 //{
482 // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n"));
483 // return 0xFFFFFFFF;
484 //}
485
486 // For 92S LSSI Read RFLSSIRead
487 // For RF A/B write 0x824/82c(does not work in the future)
488 // We must use 0x824 for RF A and B to execute read trigger
489 tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
490 if(eRFPath == RF_PATH_A)
491 tmplong2 = tmplong;
492 else
493 tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
494
495 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF
496
497 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
498 rtw_udelay_os(10);// PlatformStallExecution(10);
499
500 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
501 rtw_udelay_os(100);//PlatformStallExecution(100);
502
503 //PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
504 rtw_udelay_os(10);//PlatformStallExecution(10);
505
506 if(eRFPath == RF_PATH_A)
507 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
508 else if(eRFPath == RF_PATH_B)
509 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
510
511 if(RfPiEnable)
512 { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
513 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
514 //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue);
515 }
516 else
517 { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
518 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
519 //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue);
520 }
521 //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue);
522
523 return retValue;
524
525 }
526
527
528
529 /**
530 * Function: phy_RFSerialWrite
531 *
532 * OverView: Write data to RF register (page 8~)
533 *
534 * Input:
535 * PADAPTER Adapter,
536 * u8 eRFPath, //Radio path of A/B/C/D
537 * u4Byte Offset, //The target address to be read
538 * u4Byte Data //The new register Data in the target bit position
539 * //of the target to be read
540 *
541 * Output: None
542 * Return: None
543 * Note: Threre are three types of serial operations:
544 * 1. Software serial write
545 * 2. Hardware LSSI-Low Speed Serial Interface
546 * 3. Hardware HSSI-High speed
547 * serial write. Driver need to implement (1) and (2).
548 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
549 *
550 * Note: For RF8256 only
551 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
552 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
553 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
554 * programming guide" for more details.
555 * Thus, we define a sub-finction for RTL8526 register address conversion
556 * ===========================================================
557 * Register Mode RegCTL[1] RegCTL[0] Note
558 * (Reg00[12]) (Reg00[10])
559 * ===========================================================
560 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
561 * ------------------------------------------------------------------
562 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
563 * ------------------------------------------------------------------
564 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
565 * ------------------------------------------------------------------
566 *
567 * 2008/09/02 MH Add 92S RF definition
568 *
569 *
570 *
571 */
572 static VOID
phy_RFSerialWrite(IN PADAPTER Adapter,IN u8 eRFPath,IN u32 Offset,IN u32 Data)573 phy_RFSerialWrite(
574 IN PADAPTER Adapter,
575 IN u8 eRFPath,
576 IN u32 Offset,
577 IN u32 Data
578 )
579 {
580 u32 DataAndAddr = 0;
581 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
582 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
583 u32 NewOffset;
584
585
586 #if 0
587 //<Roger_TODO> We should check valid regs for RF_6052 case.
588 if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
589 return;
590 if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
591 return;
592 #endif
593
594 // 2009/06/17 MH We can not execute IO for power save or other accident mode.
595 //if(RT_CANNOT_IO(Adapter))
596 //{
597 // RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));
598 // return;
599 //}
600
601 Offset &= 0xff;
602
603 //
604 // Shadow Update
605 //
606 //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);
607
608 //
609 // Switch page for 8256 RF IC
610 //
611 NewOffset = Offset;
612
613 //
614 // Put write addr in [5:0] and write data in [31:16]
615 //
616 //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
617 DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
618
619 //
620 // Write Operation
621 //
622 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
623 //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
624
625 }
626
627
628 /**
629 * Function: PHY_QueryRFReg
630 *
631 * OverView: Query "Specific bits" to RF register (page 8~)
632 *
633 * Input:
634 * PADAPTER Adapter,
635 * u8 eRFPath, //Radio path of A/B/C/D
636 * u4Byte RegAddr, //The target address to be read
637 * u4Byte BitMask //The target bit position in the target address
638 * //to be read
639 *
640 * Output: None
641 * Return: u4Byte Readback value
642 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
643 */
644 u32
PHY_QueryRFReg8188E(IN PADAPTER Adapter,IN u8 eRFPath,IN u32 RegAddr,IN u32 BitMask)645 PHY_QueryRFReg8188E(
646 IN PADAPTER Adapter,
647 IN u8 eRFPath,
648 IN u32 RegAddr,
649 IN u32 BitMask
650 )
651 {
652 u32 Original_Value, Readback_Value, BitShift;
653 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
654 //u8 RFWaitCounter = 0;
655 //_irqL irqL;
656
657 if (eRFPath >= MAX_RF_PATH)
658 return 0;
659
660 #if (DISABLE_BB_RF == 1)
661 return 0;
662 #endif
663
664 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));
665
666 #ifdef CONFIG_USB_HCI
667 //PlatformAcquireMutex(&pHalData->mxRFOperate);
668 #else
669 //_enter_critical(&pHalData->rf_lock, &irqL);
670 #endif
671
672
673 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
674
675 BitShift = PHY_CalculateBitShift(BitMask);
676 Readback_Value = (Original_Value & BitMask) >> BitShift;
677
678 #ifdef CONFIG_USB_HCI
679 //PlatformReleaseMutex(&pHalData->mxRFOperate);
680 #else
681 //_exit_critical(&pHalData->rf_lock, &irqL);
682 #endif
683
684
685 //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,
686 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n",
687 // RegAddr, eRFPath, Original_Value));
688
689 return (Readback_Value);
690 }
691
692 /**
693 * Function: PHY_SetRFReg
694 *
695 * OverView: Write "Specific bits" to RF register (page 8~)
696 *
697 * Input:
698 * PADAPTER Adapter,
699 * u8 eRFPath, //Radio path of A/B/C/D
700 * u4Byte RegAddr, //The target address to be modified
701 * u4Byte BitMask //The target bit position in the target address
702 * //to be modified
703 * u4Byte Data //The new register Data in the target bit position
704 * //of the target address
705 *
706 * Output: None
707 * Return: None
708 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
709 */
710 VOID
PHY_SetRFReg8188E(IN PADAPTER Adapter,IN u8 eRFPath,IN u32 RegAddr,IN u32 BitMask,IN u32 Data)711 PHY_SetRFReg8188E(
712 IN PADAPTER Adapter,
713 IN u8 eRFPath,
714 IN u32 RegAddr,
715 IN u32 BitMask,
716 IN u32 Data
717 )
718 {
719
720 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
721 //u1Byte RFWaitCounter = 0;
722 u32 Original_Value, BitShift;
723 //_irqL irqL;
724
725 if (eRFPath > MAX_RF_PATH)
726 return;
727
728
729 #if (DISABLE_BB_RF == 1)
730 return;
731 #endif
732
733 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
734 // RegAddr, BitMask, Data, eRFPath));
735 //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
736 // RegAddr, BitMask, Data, eRFPath));
737
738
739 #ifdef CONFIG_USB_HCI
740 //PlatformAcquireMutex(&pHalData->mxRFOperate);
741 #else
742 //_enter_critical(&pHalData->rf_lock, &irqL);
743 #endif
744
745
746 // RF data is 12 bits only
747 if (BitMask != bRFRegOffsetMask)
748 {
749 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
750 BitShift = PHY_CalculateBitShift(BitMask);
751 Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));
752 }
753
754 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
755
756
757 #ifdef CONFIG_USB_HCI
758 //PlatformReleaseMutex(&pHalData->mxRFOperate);
759 #else
760 //_exit_critical(&pHalData->rf_lock, &irqL);
761 #endif
762
763 //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);
764 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
765 // RegAddr, BitMask, Data, eRFPath));
766
767 }
768
769
770 //
771 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
772 //
773
774 /*-----------------------------------------------------------------------------
775 * Function: PHY_MACConfig8192C
776 *
777 * Overview: Condig MAC by header file or parameter file.
778 *
779 * Input: NONE
780 *
781 * Output: NONE
782 *
783 * Return: NONE
784 *
785 * Revised History:
786 * When Who Remark
787 * 08/12/2008 MHC Create Version 0.
788 *
789 *---------------------------------------------------------------------------*/
PHY_MACConfig8188E(PADAPTER Adapter)790 s32 PHY_MACConfig8188E(PADAPTER Adapter)
791 {
792 int rtStatus = _SUCCESS;
793 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
794 s8 *pszMACRegFile;
795 s8 sz8188EMACRegFile[] = RTL8188E_PHY_MACREG;
796 u16 val=0;
797
798 pszMACRegFile = sz8188EMACRegFile;
799
800 //
801 // Config MAC
802 //
803 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
804 rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
805 if (rtStatus == _FAIL)
806 #endif
807 {
808 #ifdef CONFIG_EMBEDDED_FWIMG
809 if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
810 rtStatus = _FAIL;
811 else
812 rtStatus = _SUCCESS;
813 #endif//CONFIG_EMBEDDED_FWIMG
814 }
815
816 // 2010.07.13 AMPDU aggregation number B
817 val |= MAX_AGGR_NUM;
818 val = val << 8;
819 val |= MAX_AGGR_NUM;
820 rtw_write16(Adapter, REG_MAX_AGGR_NUM, val);
821 //rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0B);
822
823 return rtStatus;
824
825 }
826
827 /*-----------------------------------------------------------------------------
828 * Function: phy_InitBBRFRegisterDefinition
829 *
830 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
831 *
832 * Input:
833 * PADAPTER Adapter,
834 *
835 * Output: None
836 * Return: None
837 * Note: The initialization value is constant and it should never be changes
838 -----------------------------------------------------------------------------*/
839 static VOID
phy_InitBBRFRegisterDefinition(IN PADAPTER Adapter)840 phy_InitBBRFRegisterDefinition(
841 IN PADAPTER Adapter
842 )
843 {
844 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
845
846 // RF Interface Sowrtware Control
847 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
848 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
849 pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
850 pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
851
852 // RF Interface Output (and Enable)
853 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
854 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
855
856 // RF Interface (Output and) Enable
857 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
858 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
859
860 //Addr of LSSI. Wirte RF register by driver
861 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
862 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
863
864 // Tranceiver A~D HSSI Parameter-2
865 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
866 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
867
868 // Tranceiver LSSI Readback SI mode
869 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
870 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
871 pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
872 pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
873
874 // Tranceiver LSSI Readback PI mode
875 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
876 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
877 //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
878 //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
879
880 }
881
882 VOID
storePwrIndexDiffRateOffset(IN PADAPTER Adapter,IN u32 RegAddr,IN u32 BitMask,IN u32 Data)883 storePwrIndexDiffRateOffset(
884 IN PADAPTER Adapter,
885 IN u32 RegAddr,
886 IN u32 BitMask,
887 IN u32 Data
888 )
889 {
890 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
891
892 if(RegAddr == rTxAGC_A_Rate18_06)
893 {
894 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
895 //printk("MCSTxPowerLevelOriginalOffset[%d][0]-TxAGC_A_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt,
896 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]);
897 }
898 if(RegAddr == rTxAGC_A_Rate54_24)
899 {
900 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
901 //printk("MCSTxPowerLevelOriginalOffset[%d][1]-TxAGC_A_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt,
902 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]);
903 }
904 if(RegAddr == rTxAGC_A_CCK1_Mcs32)
905 {
906 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
907 //printk("MCSTxPowerLevelOriginalOffset[%d][6]-TxAGC_A_CCK1_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt,
908 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]);
909 }
910 if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == bMaskH3Bytes)
911 {
912 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
913 //printk("MCSTxPowerLevelOriginalOffset[%d][7]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt,
914 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]);
915 }
916 if(RegAddr == rTxAGC_A_Mcs03_Mcs00)
917 {
918 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
919 //printk("MCSTxPowerLevelOriginalOffset[%d][2]-TxAGC_A_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt,
920 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]);
921 }
922 if(RegAddr == rTxAGC_A_Mcs07_Mcs04)
923 {
924 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
925 //printk("MCSTxPowerLevelOriginalOffset[%d][3]-TxAGC_A_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt,
926 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]);
927 }
928 if(RegAddr == rTxAGC_A_Mcs11_Mcs08)
929 {
930 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
931 //printk("MCSTxPowerLevelOriginalOffset[%d][4]-TxAGC_A_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt,
932 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]);
933 }
934 if(RegAddr == rTxAGC_A_Mcs15_Mcs12)
935 {
936 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
937 //printk("MCSTxPowerLevelOriginalOffset[%d][5]-TxAGC_A_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]);
938 if(pHalData->rf_type== RF_1T1R)
939 {
940 //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt);
941 pHalData->pwrGroupCnt++;
942 }
943 }
944 if(RegAddr == rTxAGC_B_Rate18_06)
945 {
946 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
947 //printk("MCSTxPowerLevelOriginalOffset[%d][8]-TxAGC_B_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt,
948 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]);
949 }
950 if(RegAddr == rTxAGC_B_Rate54_24)
951 {
952 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
953 //printk("MCSTxPowerLevelOriginalOffset[%d][9]-TxAGC_B_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt,
954 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]);
955 }
956 if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)
957 {
958 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
959 //printk("MCSTxPowerLevelOriginalOffset[%d][14]-TxAGC_B_CCK1_55_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt,
960 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]);
961 }
962 if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
963 {
964 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
965 //printk("MCSTxPowerLevelOriginalOffset[%d][15]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt,
966 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]);
967 }
968 if(RegAddr == rTxAGC_B_Mcs03_Mcs00)
969 {
970 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
971 //printk("MCSTxPowerLevelOriginalOffset[%d][10]-TxAGC_B_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt,
972 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]);
973 }
974 if(RegAddr == rTxAGC_B_Mcs07_Mcs04)
975 {
976 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
977 //printk("MCSTxPowerLevelOriginalOffset[%d][11]-TxAGC_B_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt,
978 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]);
979 }
980 if(RegAddr == rTxAGC_B_Mcs11_Mcs08)
981 {
982 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
983 //printk("MCSTxPowerLevelOriginalOffset[%d][12]-TxAGC_B_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt,
984 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]);
985 }
986 if(RegAddr == rTxAGC_B_Mcs15_Mcs12)
987 {
988 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
989 //printk("MCSTxPowerLevelOriginalOffset[%d][13]-TxAGC_B_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,
990 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]);
991
992 if(pHalData->rf_type != RF_1T1R)
993 {
994 //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt);
995 pHalData->pwrGroupCnt++;
996 }
997 }
998 }
999
1000
1001 static VOID
phy_BB8192C_Config_1T(IN PADAPTER Adapter)1002 phy_BB8192C_Config_1T(
1003 IN PADAPTER Adapter
1004 )
1005 {
1006 #if 0
1007 //for path - A
1008 PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
1009 PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
1010 PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
1011 PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
1012 PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
1013 PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
1014 PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
1015 #endif
1016 //for path - B
1017 PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
1018 PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
1019
1020 // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.
1021 PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);
1022 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);
1023 PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC
1024
1025 PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);
1026 PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);
1027 PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);
1028 PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);
1029 PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);
1030
1031
1032 }
1033
1034 // Joseph test: new initialize order!!
1035 // Test only!! This part need to be re-organized.
1036 // Now it is just for 8256.
1037 static int
phy_BB8190_Config_HardCode(IN PADAPTER Adapter)1038 phy_BB8190_Config_HardCode(
1039 IN PADAPTER Adapter
1040 )
1041 {
1042 //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
1043 return _SUCCESS;
1044 }
1045
1046 static int
phy_BB8188E_Config_ParaFile(IN PADAPTER Adapter)1047 phy_BB8188E_Config_ParaFile(
1048 IN PADAPTER Adapter
1049 )
1050 {
1051 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1052 int rtStatus = _SUCCESS;
1053
1054 u8 sz8188EBBRegFile[] = RTL8188E_PHY_REG;
1055 u8 sz8188EAGCTableFile[] = RTL8188E_AGC_TAB;
1056 u8 sz8188EBBRegPgFile[] = RTL8188E_PHY_REG_PG;
1057 u8 sz8188EBBRegMpFile[] = RTL8188E_PHY_REG_MP;
1058 u8 sz8188EBBRegLimitFile[] = RTL8188E_TXPWR_LMT;
1059
1060 u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL,
1061 *pszRFTxPwrLmtFile = NULL;
1062
1063
1064 //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));
1065
1066 pszBBRegFile = sz8188EBBRegFile ;
1067 pszAGCTableFile = sz8188EAGCTableFile;
1068 pszBBRegPgFile = sz8188EBBRegPgFile;
1069 pszBBRegMpFile = sz8188EBBRegMpFile;
1070 pszRFTxPwrLmtFile = sz8188EBBRegLimitFile;
1071
1072 PHY_InitTxPowerLimit( Adapter );
1073
1074 if ( Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
1075 ( Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1 ) )
1076 {
1077 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
1078 if (PHY_ConfigRFWithPowerLimitTableParaFile( Adapter, pszRFTxPwrLmtFile )== _FAIL)
1079 #endif
1080 {
1081 #ifdef CONFIG_EMBEDDED_FWIMG
1082 if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0))
1083 rtStatus = _FAIL;
1084 #endif
1085 }
1086
1087 if(rtStatus != _SUCCESS){
1088 DBG_871X("phy_BB8188E_Config_ParaFile():Read Tx power limit fail!!\n");
1089 goto phy_BB8190_Config_ParaFile_Fail;
1090 }
1091 }
1092
1093 //
1094 // 1. Read PHY_REG.TXT BB INIT!!
1095 //
1096 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
1097 if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) == _FAIL)
1098 #endif
1099 {
1100 #ifdef CONFIG_EMBEDDED_FWIMG
1101 if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
1102 rtStatus = _FAIL;
1103 #endif
1104 }
1105
1106 if(rtStatus != _SUCCESS){
1107 //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"));
1108 goto phy_BB8190_Config_ParaFile_Fail;
1109 }
1110
1111 #if (MP_DRIVER == 1)
1112 //
1113 // 1.1 Read PHY_REG_MP.TXT BB INIT!!
1114 //
1115 if (Adapter->registrypriv.mp_mode == 1) {
1116 //3 Read PHY_REG.TXT BB INIT!!
1117 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
1118 if (phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile) == _FAIL)
1119 #endif
1120 {
1121 #ifdef CONFIG_EMBEDDED_FWIMG
1122 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))
1123 rtStatus = _FAIL;
1124 #endif
1125 }
1126
1127 if(rtStatus != _SUCCESS){
1128 DBG_871X("phy_BB8188E_Config_ParaFile():Write BB Reg MP Fail!!");
1129 goto phy_BB8190_Config_ParaFile_Fail;
1130 }
1131 }
1132 #endif // #if (MP_DRIVER == 1)
1133
1134 //
1135 // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
1136 //
1137 PHY_InitTxPowerByRate( Adapter );
1138 if ( ( Adapter->registrypriv.RegEnableTxPowerByRate == 1 ||
1139 ( Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2 ) ) )
1140 {
1141 pHalData->pwrGroupCnt = 0;
1142
1143 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
1144 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) == _FAIL)
1145 #endif
1146 {
1147 #ifdef CONFIG_EMBEDDED_FWIMG
1148 if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
1149 rtStatus = _FAIL;
1150 #endif
1151 }
1152
1153 if ( pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE )
1154 PHY_TxPowerByRateConfiguration(Adapter);
1155
1156 if ( Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
1157 ( Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1 ) )
1158 PHY_ConvertTxPowerLimitToPowerIndex( Adapter );
1159
1160 if(rtStatus != _SUCCESS){
1161 DBG_871X("%s(): CONFIG_BB_PHY_REG_PG Fail!!\n",__FUNCTION__ );
1162 goto phy_BB8190_Config_ParaFile_Fail;
1163 }
1164 }
1165
1166 //
1167 // 3. BB AGC table Initialization
1168 //
1169 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
1170 if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile, CONFIG_BB_AGC_TAB) == _FAIL)
1171 #endif
1172 {
1173 #ifdef CONFIG_EMBEDDED_FWIMG
1174 if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
1175 rtStatus = _FAIL;
1176 #endif
1177 }
1178
1179 if(rtStatus != _SUCCESS){
1180 //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n"));
1181 goto phy_BB8190_Config_ParaFile_Fail;
1182 }
1183
1184
1185 phy_BB8190_Config_ParaFile_Fail:
1186
1187 return rtStatus;
1188 }
1189
1190
1191 int
PHY_BBConfig8188E(IN PADAPTER Adapter)1192 PHY_BBConfig8188E(
1193 IN PADAPTER Adapter
1194 )
1195 {
1196 int rtStatus = _SUCCESS;
1197 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1198 u32 RegVal;
1199 u8 TmpU1B=0;
1200 u8 value8,CrystalCap;
1201
1202 phy_InitBBRFRegisterDefinition(Adapter);
1203
1204
1205 // Enable BB and RF
1206 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1207 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
1208
1209 // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.
1210 //rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
1211 //rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);
1212
1213 rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
1214
1215 #ifdef CONFIG_USB_HCI
1216 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
1217 #else
1218 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
1219 #endif
1220
1221 #if 0
1222 #ifdef CONFIG_USB_HCI
1223 //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
1224 rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
1225 rtw_write8(Adapter, 0x15, 0xe9);
1226 #endif
1227
1228 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
1229 #endif
1230
1231 #ifdef CONFIG_USB_HCI
1232 //rtw_write8(Adapter, 0x15, 0xe9);
1233 #endif
1234
1235
1236 #ifdef CONFIG_PCI_HCI
1237 // Force use left antenna by default for 88C.
1238 if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)
1239 {
1240 RegVal = rtw_read32(Adapter, REG_LEDCFG0);
1241 rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);
1242 }
1243 #endif
1244
1245 //
1246 // Config BB and AGC
1247 //
1248 rtStatus = phy_BB8188E_Config_ParaFile(Adapter);
1249
1250 // write 0x24[16:11] = 0x24[22:17] = CrystalCap
1251 CrystalCap = pHalData->CrystalCap & 0x3F;
1252 PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
1253
1254 return rtStatus;
1255
1256 }
1257
1258
1259 int
PHY_RFConfig8188E(IN PADAPTER Adapter)1260 PHY_RFConfig8188E(
1261 IN PADAPTER Adapter
1262 )
1263 {
1264 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1265 int rtStatus = _SUCCESS;
1266
1267 //
1268 // RF config
1269 //
1270 rtStatus = PHY_RF6052_Config8188E(Adapter);
1271 #if 0
1272 switch(pHalData->rf_chip)
1273 {
1274 case RF_6052:
1275 rtStatus = PHY_RF6052_Config(Adapter);
1276 break;
1277 case RF_8225:
1278 rtStatus = PHY_RF8225_Config(Adapter);
1279 break;
1280 case RF_8256:
1281 rtStatus = PHY_RF8256_Config(Adapter);
1282 break;
1283 case RF_8258:
1284 break;
1285 case RF_PSEUDO_11N:
1286 rtStatus = PHY_RF8225_Config(Adapter);
1287 break;
1288 default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch
1289 break;
1290 }
1291 #endif
1292 return rtStatus;
1293 }
1294
1295
1296 /*-----------------------------------------------------------------------------
1297 * Function: PHY_ConfigRFWithParaFile()
1298 *
1299 * Overview: This function read RF parameters from general file format, and do RF 3-wire
1300 *
1301 * Input: PADAPTER Adapter
1302 * ps1Byte pFileName
1303 * u8 eRFPath
1304 *
1305 * Output: NONE
1306 *
1307 * Return: RT_STATUS_SUCCESS: configuration file exist
1308 *
1309 * Note: Delay may be required for RF configuration
1310 *---------------------------------------------------------------------------*/
1311 int
rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter,IN u8 * pFileName,IN u8 eRFPath)1312 rtl8188e_PHY_ConfigRFWithParaFile(
1313 IN PADAPTER Adapter,
1314 IN u8* pFileName,
1315 IN u8 eRFPath
1316 )
1317 {
1318 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1319
1320 int rtStatus = _SUCCESS;
1321
1322
1323 return rtStatus;
1324
1325 }
1326
1327 //****************************************
1328 // The following is for High Power PA
1329 //****************************************
1330 #define HighPowerRadioAArrayLen 22
1331 //This is for High power PA
1332 u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {
1333 0x013,0x00029ea4,
1334 0x013,0x00025e74,
1335 0x013,0x00020ea4,
1336 0x013,0x0001ced0,
1337 0x013,0x00019f40,
1338 0x013,0x00014e70,
1339 0x013,0x000106a0,
1340 0x013,0x0000c670,
1341 0x013,0x000082a0,
1342 0x013,0x00004270,
1343 0x013,0x00000240,
1344 };
1345
1346 //****************************************
1347 /*-----------------------------------------------------------------------------
1348 * Function: GetTxPowerLevel8190()
1349 *
1350 * Overview: This function is export to "common" moudule
1351 *
1352 * Input: PADAPTER Adapter
1353 * psByte Power Level
1354 *
1355 * Output: NONE
1356 *
1357 * Return: NONE
1358 *
1359 *---------------------------------------------------------------------------*/
1360 VOID
PHY_GetTxPowerLevel8188E(IN PADAPTER Adapter,OUT s32 * powerlevel)1361 PHY_GetTxPowerLevel8188E(
1362 IN PADAPTER Adapter,
1363 OUT s32* powerlevel
1364 )
1365 {
1366 #if 0
1367 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1368 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
1369 s4Byte TxPwrDbm = 13;
1370 RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_GetTxPowerLevel8188E(): TxPowerLevel: %#x\n", TxPwrDbm));
1371
1372 if ( pMgntInfo->ClientConfigPwrInDbm != UNSPECIFIED_PWR_DBM )
1373 *powerlevel = pMgntInfo->ClientConfigPwrInDbm;
1374 else
1375 *powerlevel = TxPwrDbm;
1376 #endif
1377 }
1378
1379 /*-----------------------------------------------------------------------------
1380 * Function: SetTxPowerLevel8190()
1381 *
1382 * Overview: This function is export to "HalCommon" moudule
1383 * We must consider RF path later!!!!!!!
1384 *
1385 * Input: PADAPTER Adapter
1386 * u1Byte channel
1387 *
1388 * Output: NONE
1389 *
1390 * Return: NONE
1391 * 2008/11/04 MHC We remove EEPROM_93C56.
1392 * We need to move CCX relative code to independet file.
1393 * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
1394 *
1395 *---------------------------------------------------------------------------*/
1396 VOID
PHY_SetTxPowerLevel8188E(IN PADAPTER Adapter,IN u8 Channel)1397 PHY_SetTxPowerLevel8188E(
1398 IN PADAPTER Adapter,
1399 IN u8 Channel
1400 )
1401 {
1402 //DBG_871X("==>PHY_SetTxPowerLevel8188E()\n");
1403
1404 PHY_SetTxPowerLevelByPath(Adapter, Channel, ODM_RF_PATH_A);
1405
1406 //DBG_871X("<==PHY_SetTxPowerLevel8188E()\n");
1407 }
1408
1409 VOID
PHY_SetTxPowerIndex_8188E(IN PADAPTER Adapter,IN u32 PowerIndex,IN u8 RFPath,IN u8 Rate)1410 PHY_SetTxPowerIndex_8188E(
1411 IN PADAPTER Adapter,
1412 IN u32 PowerIndex,
1413 IN u8 RFPath,
1414 IN u8 Rate
1415 )
1416 {
1417 if (RFPath == ODM_RF_PATH_A)
1418 {
1419 switch (Rate)
1420 {
1421 case MGN_1M: PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex); break;
1422 case MGN_2M: PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex); break;
1423 case MGN_5_5M: PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex); break;
1424 case MGN_11M: PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex); break;
1425
1426 case MGN_6M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex); break;
1427 case MGN_9M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex); break;
1428 case MGN_12M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex); break;
1429 case MGN_18M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex); break;
1430
1431 case MGN_24M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex); break;
1432 case MGN_36M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex); break;
1433 case MGN_48M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex); break;
1434 case MGN_54M: PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex); break;
1435
1436 case MGN_MCS0: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex); break;
1437 case MGN_MCS1: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex); break;
1438 case MGN_MCS2: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex); break;
1439 case MGN_MCS3: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex); break;
1440
1441 case MGN_MCS4: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex); break;
1442 case MGN_MCS5: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex); break;
1443 case MGN_MCS6: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex); break;
1444 case MGN_MCS7: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex); break;
1445
1446 case MGN_MCS8: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte0, PowerIndex); break;
1447 case MGN_MCS9: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte1, PowerIndex); break;
1448 case MGN_MCS10: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte2, PowerIndex); break;
1449 case MGN_MCS11: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte3, PowerIndex); break;
1450
1451 case MGN_MCS12: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte0, PowerIndex); break;
1452 case MGN_MCS13: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte1, PowerIndex); break;
1453 case MGN_MCS14: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte2, PowerIndex); break;
1454 case MGN_MCS15: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte3, PowerIndex); break;
1455
1456 default:
1457 DBG_871X("Invalid Rate!!\n");
1458 break;
1459 }
1460 }
1461 else if (RFPath == ODM_RF_PATH_B)
1462 {
1463 switch (Rate)
1464 {
1465 case MGN_1M: PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte1, PowerIndex); break;
1466 case MGN_2M: PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte2, PowerIndex); break;
1467 case MGN_5_5M: PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, PowerIndex); break;
1468 case MGN_11M: PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, PowerIndex); break;
1469
1470 case MGN_6M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte0, PowerIndex); break;
1471 case MGN_9M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte1, PowerIndex); break;
1472 case MGN_12M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte2, PowerIndex); break;
1473 case MGN_18M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte3, PowerIndex); break;
1474
1475 case MGN_24M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte0, PowerIndex); break;
1476 case MGN_36M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte1, PowerIndex); break;
1477 case MGN_48M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte2, PowerIndex); break;
1478 case MGN_54M: PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte3, PowerIndex); break;
1479
1480 case MGN_MCS0: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte0, PowerIndex); break;
1481 case MGN_MCS1: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte1, PowerIndex); break;
1482 case MGN_MCS2: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte2, PowerIndex); break;
1483 case MGN_MCS3: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte3, PowerIndex); break;
1484
1485 case MGN_MCS4: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte0, PowerIndex); break;
1486 case MGN_MCS5: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte1, PowerIndex); break;
1487 case MGN_MCS6: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte2, PowerIndex); break;
1488 case MGN_MCS7: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte3, PowerIndex); break;
1489
1490 case MGN_MCS8: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte0, PowerIndex); break;
1491 case MGN_MCS9: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte1, PowerIndex); break;
1492 case MGN_MCS10: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte2, PowerIndex); break;
1493 case MGN_MCS11: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte3, PowerIndex); break;
1494
1495 case MGN_MCS12: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte0, PowerIndex); break;
1496 case MGN_MCS13: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte1, PowerIndex); break;
1497 case MGN_MCS14: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte2, PowerIndex); break;
1498 case MGN_MCS15: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte3, PowerIndex); break;
1499
1500 default:
1501 DBG_871X("Invalid Rate!!\n");
1502 break;
1503 }
1504 }
1505 else
1506 {
1507 DBG_871X("Invalid RFPath!!\n");
1508 }
1509 }
1510
1511 u8
phy_GetCurrentTxNum_8188E(IN PADAPTER pAdapter,IN u8 Rate)1512 phy_GetCurrentTxNum_8188E(
1513 IN PADAPTER pAdapter,
1514 IN u8 Rate
1515 )
1516 {
1517 u8 tmpByte = 0;
1518 u32 tmpDWord = 0;
1519 u8 TxNum = RF_TX_NUM_NONIMPLEMENT;
1520
1521 if ( ( Rate >= MGN_MCS8 && Rate <= MGN_MCS15 ) )
1522 TxNum = RF_2TX;
1523 else
1524 TxNum = RF_1TX;
1525
1526 return TxNum;
1527 }
1528
tx_power_extra_bias(IN u8 RFPath,IN u8 Rate,IN CHANNEL_WIDTH BandWidth,IN u8 Channel)1529 s8 tx_power_extra_bias(
1530 IN u8 RFPath,
1531 IN u8 Rate,
1532 IN CHANNEL_WIDTH BandWidth,
1533 IN u8 Channel
1534 )
1535 {
1536 s8 bias = 0;
1537
1538 if (Rate == MGN_2M)
1539 bias = -9;
1540
1541 return bias;
1542 }
1543
1544 u8
PHY_GetTxPowerIndex_8188E(IN PADAPTER pAdapter,IN u8 RFPath,IN u8 Rate,IN CHANNEL_WIDTH BandWidth,IN u8 Channel)1545 PHY_GetTxPowerIndex_8188E(
1546 IN PADAPTER pAdapter,
1547 IN u8 RFPath,
1548 IN u8 Rate,
1549 IN CHANNEL_WIDTH BandWidth,
1550 IN u8 Channel
1551 )
1552 {
1553 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
1554 u8 base_index = 0;
1555 s8 by_rate_diff = 0, txPower = 0, limit = 0, track_diff = 0, extra_bias = 0;
1556 u8 txNum = phy_GetCurrentTxNum_8188E(pAdapter, Rate);
1557 BOOLEAN bIn24G = _FALSE;
1558
1559 base_index = PHY_GetTxPowerIndexBase(pAdapter,RFPath, Rate, BandWidth, Channel, &bIn24G);
1560
1561 by_rate_diff = PHY_GetTxPowerByRate(pAdapter, BAND_ON_2_4G, RFPath, txNum, Rate);
1562 limit = PHY_GetTxPowerLimit(pAdapter, pAdapter->registrypriv.RegPwrTblSel, (u8)(!bIn24G), pHalData->CurrentChannelBW, RFPath, Rate, pHalData->CurrentChannel);
1563 by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff;
1564
1565 track_diff = PHY_GetTxPowerTrackingOffset(pAdapter, RFPath, Rate);
1566
1567 if (pAdapter->registrypriv.mp_mode != 1)
1568 extra_bias = tx_power_extra_bias(RFPath, Rate, BandWidth, Channel);
1569
1570 txPower = base_index + by_rate_diff + track_diff + extra_bias;
1571
1572 if(txPower > MAX_POWER_INDEX)
1573 txPower = MAX_POWER_INDEX;
1574
1575 if (0)
1576 DBG_871X("RF-%c ch%d TxPwrIdx = %d(0x%X) [%2u %2d %2d %2d]\n"
1577 , ((RFPath==0)?'A':'B'), Channel, txPower, txPower, base_index, by_rate_diff, track_diff, extra_bias);
1578
1579 return (u8)txPower;
1580 }
1581
1582 //
1583 // Description:
1584 // Update transmit power level of all channel supported.
1585 //
1586 // TODO:
1587 // A mode.
1588 // By Bruce, 2008-02-04.
1589 //
1590 BOOLEAN
PHY_UpdateTxPowerDbm8188E(IN PADAPTER Adapter,IN int powerInDbm)1591 PHY_UpdateTxPowerDbm8188E(
1592 IN PADAPTER Adapter,
1593 IN int powerInDbm
1594 )
1595 {
1596 return _TRUE;
1597 }
1598
1599 VOID
PHY_ScanOperationBackup8188E(IN PADAPTER Adapter,IN u8 Operation)1600 PHY_ScanOperationBackup8188E(
1601 IN PADAPTER Adapter,
1602 IN u8 Operation
1603 )
1604 {
1605 #if 0
1606 IO_TYPE IoType;
1607
1608 if (!rtw_is_drv_stopped(padapter)) {
1609 switch(Operation)
1610 {
1611 case SCAN_OPT_BACKUP:
1612 IoType = IO_CMD_PAUSE_DM_BY_SCAN;
1613 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
1614
1615 break;
1616
1617 case SCAN_OPT_RESTORE:
1618 IoType = IO_CMD_RESUME_DM_BY_SCAN;
1619 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
1620 break;
1621
1622 default:
1623 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
1624 break;
1625 }
1626 }
1627 #endif
1628 }
1629 void
phy_SpurCalibration_8188E(IN PADAPTER Adapter)1630 phy_SpurCalibration_8188E(
1631 IN PADAPTER Adapter
1632 )
1633 {
1634 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1635 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1636
1637 //DbgPrint("===> phy_SpurCalibration_8188E CurrentChannelBW = %d, CurrentChannel = %d\n", pHalData->CurrentChannelBW, pHalData->CurrentChannel);
1638 if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20 &&( pHalData->CurrentChannel == 13 || pHalData->CurrentChannel == 14)){
1639 PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(9), 0x1); //enable notch filter
1640 PHY_SetBBReg(Adapter, rOFDM1_IntfDet, BIT(8)|BIT(7)|BIT(6), 0x2); //intf_TH
1641 PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(28) | BIT(27) | BIT(26) |BIT(25) | BIT (24), 0x1f);
1642 pDM_Odm->is_nbi_enable = false;
1643 } else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40 && pHalData->CurrentChannel == 11){
1644 PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(9), 0x1); //enable notch filter
1645 PHY_SetBBReg(Adapter, rOFDM1_IntfDet, BIT(8)|BIT(7)|BIT(6), 0x2); //intf_TH
1646 PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(28) | BIT(27) | BIT(26) |BIT(25) | BIT (24), 0x1f);
1647 pDM_Odm->is_nbi_enable = false;
1648 } else {
1649 if(Adapter->registrypriv.notch_filter == 0)
1650 PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(9), 0x0); //disable notch filter
1651 }
1652 }
1653
1654 /*-----------------------------------------------------------------------------
1655 * Function: PHY_SetBWModeCallback8192C()
1656 *
1657 * Overview: Timer callback function for SetSetBWMode
1658 *
1659 * Input: PRT_TIMER pTimer
1660 *
1661 * Output: NONE
1662 *
1663 * Return: NONE
1664 *
1665 * Note: (1) We do not take j mode into consideration now
1666 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
1667 * concurrently?
1668 *---------------------------------------------------------------------------*/
1669 static VOID
_PHY_SetBWMode88E(IN PADAPTER Adapter)1670 _PHY_SetBWMode88E(
1671 IN PADAPTER Adapter
1672 )
1673 {
1674 // PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
1675 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1676 u8 regBwOpMode;
1677 u8 regRRSR_RSC;
1678
1679 //return;
1680
1681 // Added it for 20/40 mhz switch time evaluation by guangan 070531
1682 //u4Byte NowL, NowH;
1683 //u8Byte BeginTime, EndTime;
1684
1685 /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \
1686 pHalData->CurrentChannelBW == CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/
1687
1688 if(pHalData->rf_chip == RF_PSEUDO_11N)
1689 {
1690 //pHalData->SetBWModeInProgress= _FALSE;
1691 return;
1692 }
1693
1694 // There is no 40MHz mode in RF_8225.
1695 if(pHalData->rf_chip==RF_8225)
1696 return;
1697
1698 if (rtw_is_drv_stopped(Adapter))
1699 return;
1700
1701 // Added it for 20/40 mhz switch time evaluation by guangan 070531
1702 //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
1703 //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
1704 //BeginTime = ((u8Byte)NowH << 32) + NowL;
1705
1706 //3//
1707 //3//<1>Set MAC register
1708 //3//
1709 //Adapter->HalFunc.SetBWModeHandler();
1710
1711 regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
1712 regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
1713 //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)®BwOpMode);
1714
1715 switch(pHalData->CurrentChannelBW)
1716 {
1717 case CHANNEL_WIDTH_20:
1718 regBwOpMode |= BW_OPMODE_20MHZ;
1719 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
1720 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1721 break;
1722
1723 case CHANNEL_WIDTH_40:
1724 regBwOpMode &= ~BW_OPMODE_20MHZ;
1725 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
1726 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1727
1728 regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);
1729 rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
1730 break;
1731
1732 default:
1733 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C():
1734 unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/
1735 break;
1736 }
1737
1738 //3//
1739 //3//<2>Set PHY related register
1740 //3//
1741 switch(pHalData->CurrentChannelBW)
1742 {
1743 /* 20 MHz channel*/
1744 case CHANNEL_WIDTH_20:
1745 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
1746 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
1747 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);
1748
1749 break;
1750
1751
1752 /* 40 MHz channel*/
1753 case CHANNEL_WIDTH_40:
1754 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
1755 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
1756
1757 // Set Control channel to upper or lower. These settings are required only for 40MHz
1758 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
1759 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
1760 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);
1761
1762 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);
1763
1764 break;
1765
1766
1767
1768 default:
1769 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\
1770 ,pHalData->CurrentChannelBW));*/
1771 break;
1772
1773 }
1774 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
1775
1776 // Added it for 20/40 mhz switch time evaluation by guangan 070531
1777 //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
1778 //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
1779 //EndTime = ((u8Byte)NowH << 32) + NowL;
1780 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
1781
1782 //3<3>Set RF related register
1783 switch(pHalData->rf_chip)
1784 {
1785 case RF_8225:
1786 //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1787 break;
1788
1789 case RF_8256:
1790 // Please implement this function in Hal8190PciPhy8256.c
1791 //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW);
1792 break;
1793
1794 case RF_8258:
1795 // Please implement this function in Hal8190PciPhy8258.c
1796 // PHY_SetRF8258Bandwidth();
1797 break;
1798
1799 case RF_PSEUDO_11N:
1800 // Do Nothing
1801 break;
1802
1803 case RF_6052:
1804 rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
1805 break;
1806
1807 default:
1808 //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
1809 break;
1810 }
1811
1812 //pHalData->SetBWModeInProgress= FALSE;
1813
1814 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" ));
1815 }
1816
1817
1818 /*-----------------------------------------------------------------------------
1819 * Function: SetBWMode8190Pci()
1820 *
1821 * Overview: This function is export to "HalCommon" moudule
1822 *
1823 * Input: PADAPTER Adapter
1824 * CHANNEL_WIDTH Bandwidth //20M or 40M
1825 *
1826 * Output: NONE
1827 *
1828 * Return: NONE
1829 *
1830 * Note: We do not take j mode into consideration now
1831 *---------------------------------------------------------------------------*/
1832 VOID
PHY_SetBWMode8188E(IN PADAPTER Adapter,IN CHANNEL_WIDTH Bandwidth,IN unsigned char Offset)1833 PHY_SetBWMode8188E(
1834 IN PADAPTER Adapter,
1835 IN CHANNEL_WIDTH Bandwidth, // 20M or 40M
1836 IN unsigned char Offset // Upper, Lower, or Don't care
1837 )
1838 {
1839 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1840 CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
1841 // Modified it for 20/40 mhz switch by guangan 070531
1842 //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
1843
1844 //return;
1845
1846 //if(pHalData->SwChnlInProgress)
1847 // if(pMgntInfo->bScanInProgress)
1848 // {
1849 // RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n",
1850 // Bandwidth == CHANNEL_WIDTH_20?"20MHz":"40MHz"));
1851 // return;
1852 // }
1853
1854 // if(pHalData->SetBWModeInProgress)
1855 // {
1856 // // Modified it for 20/40 mhz switch by guangan 070531
1857 // RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n",
1858 // Bandwidth == CHANNEL_WIDTH_20?"20MHz":"40MHz"));
1859 // PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);
1860 // //return;
1861 // }
1862
1863 //if(pHalData->SetBWModeInProgress)
1864 // return;
1865
1866 //pHalData->SetBWModeInProgress= TRUE;
1867
1868 pHalData->CurrentChannelBW = Bandwidth;
1869
1870 #if 0
1871 if(Offset==EXTCHNL_OFFSET_LOWER)
1872 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1873 else if(Offset==EXTCHNL_OFFSET_UPPER)
1874 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1875 else
1876 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1877 #else
1878 pHalData->nCur40MhzPrimeSC = Offset;
1879 #endif
1880
1881 if (!RTW_CANNOT_RUN(Adapter)) {
1882 #if 0
1883 //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
1884 #else
1885 _PHY_SetBWMode88E(Adapter);
1886 #endif
1887 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
1888 if(IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
1889 phy_SpurCalibration_8188E( Adapter);
1890 #endif
1891 }
1892 else
1893 {
1894 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
1895 //pHalData->SetBWModeInProgress= FALSE;
1896 pHalData->CurrentChannelBW = tmpBW;
1897 }
1898
1899 }
1900
1901
_PHY_SwChnl8188E(PADAPTER Adapter,u8 channel)1902 static void _PHY_SwChnl8188E(PADAPTER Adapter, u8 channel)
1903 {
1904 u8 eRFPath;
1905 u32 param1, param2;
1906 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1907
1908 if ( Adapter->bNotifyChannelChange )
1909 {
1910 DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel );
1911 }
1912
1913 //s1. pre common command - CmdID_SetTxPowerLevel
1914 PHY_SetTxPowerLevel8188E(Adapter, channel);
1915
1916 //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel
1917 param1 = RF_CHNLBW;
1918 param2 = channel;
1919 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1920 {
1921 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
1922 PHY_SetRFReg(Adapter, eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
1923 }
1924
1925
1926 //s3. post common command - CmdID_End, None
1927
1928 }
1929 VOID
PHY_SwChnl8188E(IN PADAPTER Adapter,IN u8 channel)1930 PHY_SwChnl8188E( // Call after initialization
1931 IN PADAPTER Adapter,
1932 IN u8 channel
1933 )
1934 {
1935 //PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE);
1936 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1937 u8 tmpchannel = pHalData->CurrentChannel;
1938 BOOLEAN bResult = _TRUE;
1939
1940 if(pHalData->rf_chip == RF_PSEUDO_11N)
1941 {
1942 //pHalData->SwChnlInProgress=FALSE;
1943 return; //return immediately if it is peudo-phy
1944 }
1945
1946 //if(pHalData->SwChnlInProgress)
1947 // return;
1948
1949 //if(pHalData->SetBWModeInProgress)
1950 // return;
1951
1952 while(pHalData->odmpriv.RFCalibrateInfo.bLCKInProgress)
1953 {
1954 rtw_msleep_os(50);
1955 }
1956
1957 //--------------------------------------------
1958 switch(pHalData->CurrentWirelessMode)
1959 {
1960 case WIRELESS_MODE_A:
1961 case WIRELESS_MODE_N_5G:
1962 //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14"));
1963 break;
1964
1965 case WIRELESS_MODE_B:
1966 //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14"));
1967 break;
1968
1969 case WIRELESS_MODE_G:
1970 case WIRELESS_MODE_N_24G:
1971 //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14"));
1972 break;
1973
1974 default:
1975 //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode));
1976 break;
1977 }
1978 //--------------------------------------------
1979
1980 //pHalData->SwChnlInProgress = TRUE;
1981 if(channel == 0)
1982 channel = 1;
1983
1984 pHalData->CurrentChannel=channel;
1985
1986 //pHalData->SwChnlStage=0;
1987 //pHalData->SwChnlStep=0;
1988
1989 if (!RTW_CANNOT_RUN(Adapter)) {
1990 #if 0
1991 //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
1992 #else
1993 _PHY_SwChnl8188E(Adapter, channel);
1994 #endif
1995
1996 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
1997 if(IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
1998 phy_SpurCalibration_8188E( Adapter);
1999 #endif
2000
2001
2002
2003 if(bResult)
2004 {
2005 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));
2006 }
2007 else
2008 {
2009 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
2010 //if(IS_HARDWARE_TYPE_8192SU(Adapter))
2011 //{
2012 // pHalData->SwChnlInProgress = FALSE;
2013 pHalData->CurrentChannel = tmpchannel;
2014 //}
2015 }
2016
2017 }
2018 else
2019 {
2020 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));
2021 //if(IS_HARDWARE_TYPE_8192SU(Adapter))
2022 //{
2023 // pHalData->SwChnlInProgress = FALSE;
2024 pHalData->CurrentChannel = tmpchannel;
2025 //}
2026 }
2027 }
2028
2029 VOID
PHY_SetSwChnlBWMode8188E(IN PADAPTER Adapter,IN u8 channel,IN CHANNEL_WIDTH Bandwidth,IN u8 Offset40,IN u8 Offset80)2030 PHY_SetSwChnlBWMode8188E(
2031 IN PADAPTER Adapter,
2032 IN u8 channel,
2033 IN CHANNEL_WIDTH Bandwidth,
2034 IN u8 Offset40,
2035 IN u8 Offset80
2036 )
2037 {
2038 //DBG_871X("%s()===>\n",__FUNCTION__);
2039
2040 PHY_SwChnl8188E(Adapter, channel);
2041 PHY_SetBWMode8188E(Adapter, Bandwidth, Offset40);
2042
2043 //DBG_871X("<==%s()\n",__FUNCTION__);
2044 }
2045
2046
2047 //
2048 // Description:
2049 // Configure H/W functionality to enable/disable Monitor mode.
2050 // Note, because we possibly need to configure BB and RF in this function,
2051 // so caller should in PASSIVE_LEVEL. 080118, by rcnjko.
2052 //
2053 VOID
PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,IN BOOLEAN bEnableMonitorMode)2054 PHY_SetMonitorMode8192C(
2055 IN PADAPTER pAdapter,
2056 IN BOOLEAN bEnableMonitorMode
2057 )
2058 {
2059 #if 0
2060 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2061 BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
2062
2063 //2 Note: we may need to stop antenna diversity.
2064 if(bEnableMonitorMode)
2065 {
2066 bFilterOutNonAssociatedBSSID = FALSE;
2067 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
2068
2069 pHalData->bInMonitorMode = TRUE;
2070 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
2071 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
2072 }
2073 else
2074 {
2075 bFilterOutNonAssociatedBSSID = TRUE;
2076 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
2077
2078 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
2079 pHalData->bInMonitorMode = FALSE;
2080 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
2081 }
2082 #endif
2083 }
2084
2085
2086 /*-----------------------------------------------------------------------------
2087 * Function: PHYCheckIsLegalRfPath8190Pci()
2088 *
2089 * Overview: Check different RF type to execute legal judgement. If RF Path is illegal
2090 * We will return false.
2091 *
2092 * Input: NONE
2093 *
2094 * Output: NONE
2095 *
2096 * Return: NONE
2097 *
2098 * Revised History:
2099 * When Who Remark
2100 * 11/15/2007 MHC Create Version 0.
2101 *
2102 *---------------------------------------------------------------------------*/
2103 BOOLEAN
PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,IN u32 eRFPath)2104 PHY_CheckIsLegalRfPath8192C(
2105 IN PADAPTER pAdapter,
2106 IN u32 eRFPath)
2107 {
2108 // HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2109 BOOLEAN rtValue = _TRUE;
2110
2111 // NOt check RF Path now.!
2112 #if 0
2113 if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
2114 {
2115 rtValue = FALSE;
2116 }
2117 if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
2118 {
2119
2120 }
2121 #endif
2122 return rtValue;
2123
2124 } /* PHY_CheckIsLegalRfPath8192C */
2125
_PHY_SetRFPathSwitch(IN PADAPTER pAdapter,IN BOOLEAN bMain,IN BOOLEAN is2T)2126 static VOID _PHY_SetRFPathSwitch(
2127 IN PADAPTER pAdapter,
2128 IN BOOLEAN bMain,
2129 IN BOOLEAN is2T
2130 )
2131 {
2132 u8 u1bTmp;
2133
2134 if (!rtw_is_hw_init_completed(pAdapter)) {
2135 u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;
2136 rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);
2137 //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
2138 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
2139 }
2140
2141 if(is2T)
2142 {
2143 if(bMain)
2144 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
2145 else
2146 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
2147 }
2148 else
2149 {
2150
2151 if(bMain)
2152 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main
2153 else
2154 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux
2155 }
2156
2157 }
2158
2159 //return value TRUE => Main; FALSE => Aux
2160
_PHY_QueryRFPathSwitch(IN PADAPTER pAdapter,IN BOOLEAN is2T)2161 static BOOLEAN _PHY_QueryRFPathSwitch(
2162 IN PADAPTER pAdapter,
2163 IN BOOLEAN is2T
2164 )
2165 {
2166 // if(is2T)
2167 // return _TRUE;
2168
2169 if (!rtw_is_hw_init_completed(pAdapter)) {
2170 PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
2171 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
2172 }
2173
2174 if(is2T)
2175 {
2176 if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
2177 return _TRUE;
2178 else
2179 return _FALSE;
2180 }
2181 else
2182 {
2183 if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
2184 return _TRUE;
2185 else
2186 return _FALSE;
2187 }
2188 }
2189
2190
2191 static VOID
_PHY_DumpRFReg(IN PADAPTER pAdapter)2192 _PHY_DumpRFReg(IN PADAPTER pAdapter)
2193 {
2194 u32 rfRegValue,rfRegOffset;
2195
2196 //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n"));
2197
2198 for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){
2199 rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);
2200 //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue));
2201 }
2202 //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n"));
2203 }
2204
2205
2206 //
2207 // Move from phycfg.c to gen.c to be code independent later
2208 //
2209 //-------------------------Move to other DIR later----------------------------*/
2210 #ifdef CONFIG_USB_HCI
2211
2212 //
2213 // Description:
2214 // To dump all Tx FIFO LLT related link-list table.
2215 // Added by Roger, 2009.03.10.
2216 //
2217 VOID
DumpBBDbgPort_92CU(IN PADAPTER Adapter)2218 DumpBBDbgPort_92CU(
2219 IN PADAPTER Adapter
2220 )
2221 {
2222
2223 //RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"));
2224 //RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n"));
2225
2226 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000);
2227 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
2228
2229 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803);
2230 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
2231
2232 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06);
2233 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
2234
2235 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007);
2236 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
2237
2238 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
2239 PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000);
2240 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
2241
2242 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
2243 PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000);
2244 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
2245
2246 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord)));
2247 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord)));
2248 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord)));
2249 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord)));
2250 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord)));
2251
2252 }
2253 #endif
2254
2255