1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <dm/lists.h>
12 #include <dm/of.h>
13 #include <dm/of_access.h>
14 #include <dm/uclass-internal.h>
15 #include <generic-phy.h>
16 #include <linux/bitfield.h>
17 #include <linux/bitops.h>
18 #include <linux/usb/ch9.h>
19 #include <linux/usb/otg.h>
20 #include <regmap.h>
21 #include <reset.h>
22 #include <syscon.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/cpu.h>
25
26 #include <linux/usb/phy-rockchip-usbdp.h>
27
28 /* RK3588 USBDP PHY Register Definitions */
29
30 #define UDPHY_PCS 0x4000
31 #define UDPHY_PMA 0x8000
32
33 /* VO GRF Registers */
34 #define DP_SINK_HPD_CFG BIT(11)
35 #define DP_SINK_HPD_SEL BIT(10)
36 #define DP_AUX_DIN_SEL BIT(9)
37 #define DP_AUX_DOUT_SEL BIT(8)
38 #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
39 #define DP_LANE_SEL_ALL GENMASK(7, 0)
40
41 /* PMA CMN Registers */
42 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
43 #define CMN_DP_LANE_MUX_N(n) BIT((n) + 4)
44 #define CMN_DP_LANE_EN_N(n) BIT(n)
45 #define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
46 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
47
48 #define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */
49 #define CMN_DP_TX_LINK_BW GENMASK(6, 5)
50 #define CMN_DP_TX_LANE_SWAP_EN BIT(2)
51
52 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
53 #define CMN_ROPLL_SSC_EN BIT(1)
54 #define CMN_LCPLL_SSC_EN BIT(0)
55
56 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
57 #define CMN_ANA_LCPLL_LOCK_DONE BIT(7)
58 #define CMN_ANA_LCPLL_AFC_DONE BIT(6)
59
60 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
61 #define CMN_ANA_ROPLL_LOCK_DONE BIT(1)
62 #define CMN_ANA_ROPLL_AFC_DONE BIT(0)
63
64 #define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */
65 #define CMN_DP_INIT_RSTN BIT(3)
66 #define CMN_DP_CMN_RSTN BIT(2)
67 #define CMN_CDR_WTCHDG_EN BIT(1)
68 #define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0)
69
70 #define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */
71 #define LN_ANA_TX_SER_TXCLK_INV BIT(1)
72
73 #define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */
74 #define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
75
76 #define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
77 #define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
78
79 #define BIT_WRITEABLE_SHIFT 16
80 #define PHY_AUX_DP_DATA_POL_NORMAL 0
81 #define PHY_AUX_DP_DATA_POL_INVERT 1
82 #define PHY_LANE_MUX_USB 0
83 #define PHY_LANE_MUX_DP 1
84
85 enum {
86 DP_BW_RBR,
87 DP_BW_HBR,
88 DP_BW_HBR2,
89 DP_BW_HBR3,
90 };
91
92 enum {
93 UDPHY_MODE_NONE = 0,
94 UDPHY_MODE_USB = BIT(0),
95 UDPHY_MODE_DP = BIT(1),
96 UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
97 };
98
99 struct udphy_grf_reg {
100 unsigned int offset;
101 unsigned int bitend;
102 unsigned int bitstart;
103 unsigned int disable;
104 unsigned int enable;
105 };
106
107 /**
108 * struct reg_sequence - An individual write from a sequence of writes.
109 *
110 * @reg: Register address.
111 * @def: Register value.
112 * @delay_us: Delay to be applied after the register write in microseconds
113 *
114 * Register/value pairs for sequences of writes with an optional delay in
115 * microseconds to be applied after each write.
116 */
117 struct reg_sequence {
118 unsigned int reg;
119 unsigned int def;
120 unsigned int delay_us;
121 };
122
123 struct udphy_grf_cfg {
124 /* u2phy-grf */
125 struct udphy_grf_reg bvalid_phy_con;
126 struct udphy_grf_reg bvalid_grf_con;
127
128 /* usb-grf */
129 struct udphy_grf_reg usb3otg0_cfg;
130 struct udphy_grf_reg usb3otg1_cfg;
131
132 /* usbdpphy-grf */
133 struct udphy_grf_reg low_pwrn;
134 struct udphy_grf_reg rx_lfps;
135 };
136
137 struct udphy_vogrf_cfg {
138 /* vo-grf */
139 u32 dp_lane_reg;
140 };
141
142 struct dp_tx_drv_ctrl {
143 u32 trsv_reg0204;
144 u32 trsv_reg0205;
145 u32 trsv_reg0206;
146 u32 trsv_reg0207;
147 };
148
149 struct rockchip_udphy;
150
151 struct rockchip_udphy_cfg {
152 /* resets to be requested */
153 const char * const *rst_list;
154 int num_rsts;
155
156 struct udphy_grf_cfg grfcfg;
157 struct udphy_vogrf_cfg vogrfcfg[2];
158 const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4];
159 };
160
161 struct rockchip_udphy {
162 struct udevice *dev;
163 struct regmap *pma_regmap;
164 struct regmap *u2phygrf;
165 struct regmap *udphygrf;
166 struct regmap *usbgrf;
167 struct regmap *vogrf;
168 // struct typec_switch *sw;
169 // struct typec_mux *mux;
170
171 /* clocks and rests */
172 struct reset_ctl *rsts;
173
174 /* PHY status management */
175 bool flip;
176 bool mode_change;
177 u8 mode;
178 u8 status;
179
180 /* utilized for USB */
181 bool hs; /* flag for high-speed */
182
183 /* utilized for DP */
184 struct gpio_desc *sbu1_dc_gpio;
185 struct gpio_desc *sbu2_dc_gpio;
186 u32 lane_mux_sel[4];
187 u32 dp_lane_sel[4];
188 u32 dp_aux_dout_sel;
189 u32 dp_aux_din_sel;
190 u32 max_link_rate;
191 u8 bw; /* dp bandwidth */
192 int id;
193
194 /* PHY const config */
195 const struct rockchip_udphy_cfg *cfgs;
196 };
197
198 #ifdef CONFIG_ROCKCHIP_RK3576
199 static const struct dp_tx_drv_ctrl rk3576_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
200 /* voltage swing 0, pre-emphasis 0->3 */
201 {
202 { 0x20, 0x10, 0x42, 0xe5 },
203 { 0x26, 0x14, 0x42, 0xe5 },
204 { 0x29, 0x18, 0x42, 0xe5 },
205 { 0x2b, 0x1c, 0x43, 0xe7 },
206 },
207
208 /* voltage swing 1, pre-emphasis 0->2 */
209 {
210 { 0x23, 0x10, 0x42, 0xe7 },
211 { 0x2a, 0x17, 0x43, 0xe7 },
212 { 0x2b, 0x1a, 0x43, 0xe7 },
213 },
214
215 /* voltage swing 2, pre-emphasis 0->1 */
216 {
217 { 0x27, 0x10, 0x43, 0x67 },
218 { 0x2b, 0x17, 0x43, 0xe7 },
219 },
220
221 /* voltage swing 3, pre-emphasis 0 */
222 {
223 { 0x29, 0x10, 0x43, 0xe7 },
224 },
225 };
226 #endif
227
228 #ifdef CONFIG_ROCKCHIP_RK3588
229 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
230 /* voltage swing 0, pre-emphasis 0->3 */
231 {
232 { 0x20, 0x10, 0x42, 0xe5 },
233 { 0x26, 0x14, 0x42, 0xe5 },
234 { 0x29, 0x18, 0x42, 0xe5 },
235 { 0x2b, 0x1c, 0x43, 0xe7 },
236 },
237
238 /* voltage swing 1, pre-emphasis 0->2 */
239 {
240 { 0x23, 0x10, 0x42, 0xe7 },
241 { 0x2a, 0x17, 0x43, 0xe7 },
242 { 0x2b, 0x1a, 0x43, 0xe7 },
243 },
244
245 /* voltage swing 2, pre-emphasis 0->1 */
246 {
247 { 0x27, 0x10, 0x42, 0xe7 },
248 { 0x2b, 0x17, 0x43, 0xe7 },
249 },
250
251 /* voltage swing 3, pre-emphasis 0 */
252 {
253 { 0x29, 0x10, 0x43, 0xe7 },
254 },
255 };
256 #endif
257
258 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = {
259 /* voltage swing 0, pre-emphasis 0->3 */
260 {
261 { 0x21, 0x10, 0x42, 0xe5 },
262 { 0x26, 0x14, 0x42, 0xe5 },
263 { 0x26, 0x16, 0x43, 0xe5 },
264 { 0x2a, 0x19, 0x43, 0xe7 },
265 },
266
267 /* voltage swing 1, pre-emphasis 0->2 */
268 {
269 { 0x24, 0x10, 0x42, 0xe7 },
270 { 0x2a, 0x17, 0x43, 0xe7 },
271 { 0x2b, 0x1a, 0x43, 0xe7 },
272 },
273
274 /* voltage swing 2, pre-emphasis 0->1 */
275 {
276 { 0x28, 0x10, 0x42, 0xe7 },
277 { 0x2b, 0x17, 0x43, 0xe7 },
278 },
279
280 /* voltage swing 3, pre-emphasis 0 */
281 {
282 { 0x28, 0x10, 0x43, 0xe7 },
283 },
284 };
285
286 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = {
287 /* voltage swing 0, pre-emphasis 0->3 */
288 {
289 { 0x21, 0x10, 0x42, 0xe5 },
290 { 0x26, 0x14, 0x42, 0xe5 },
291 { 0x26, 0x16, 0x43, 0xe5 },
292 { 0x29, 0x18, 0x43, 0xe7 },
293 },
294
295 /* voltage swing 1, pre-emphasis 0->2 */
296 {
297 { 0x24, 0x10, 0x42, 0xe7 },
298 { 0x2a, 0x18, 0x43, 0xe7 },
299 { 0x2b, 0x1b, 0x43, 0xe7 }
300 },
301
302 /* voltage swing 2, pre-emphasis 0->1 */
303 {
304 { 0x27, 0x10, 0x42, 0xe7 },
305 { 0x2b, 0x18, 0x43, 0xe7 }
306 },
307
308 /* voltage swing 3, pre-emphasis 0 */
309 {
310 { 0x28, 0x10, 0x43, 0xe7 },
311 },
312 };
313
314 static const struct reg_sequence udphy_24m_refclk_cfg[] = {
315 {0x0090, 0x68}, {0x0094, 0x68},
316 {0x0128, 0x24}, {0x012c, 0x44},
317 {0x0130, 0x3f}, {0x0134, 0x44},
318 {0x015c, 0xa9}, {0x0160, 0x71},
319 {0x0164, 0x71}, {0x0168, 0xa9},
320 {0x0174, 0xa9}, {0x0178, 0x71},
321 {0x017c, 0x71}, {0x0180, 0xa9},
322 {0x018c, 0x41}, {0x0190, 0x00},
323 {0x0194, 0x05}, {0x01ac, 0x2a},
324 {0x01b0, 0x17}, {0x01b4, 0x17},
325 {0x01b8, 0x2a}, {0x01c8, 0x04},
326 {0x01cc, 0x08}, {0x01d0, 0x08},
327 {0x01d4, 0x04}, {0x01d8, 0x20},
328 {0x01dc, 0x01}, {0x01e0, 0x09},
329 {0x01e4, 0x03}, {0x01f0, 0x29},
330 {0x01f4, 0x02}, {0x01f8, 0x02},
331 {0x01fc, 0x29}, {0x0208, 0x2a},
332 {0x020c, 0x17}, {0x0210, 0x17},
333 {0x0214, 0x2a}, {0x0224, 0x20},
334 {0x03f0, 0x0a}, {0x03f4, 0x07},
335 {0x03f8, 0x07}, {0x03fc, 0x0c},
336 {0x0404, 0x12}, {0x0408, 0x1a},
337 {0x040c, 0x1a}, {0x0410, 0x3f},
338 {0x0ce0, 0x68}, {0x0ce8, 0xd0},
339 {0x0cf0, 0x87}, {0x0cf8, 0x70},
340 {0x0d00, 0x70}, {0x0d08, 0xa9},
341 {0x1ce0, 0x68}, {0x1ce8, 0xd0},
342 {0x1cf0, 0x87}, {0x1cf8, 0x70},
343 {0x1d00, 0x70}, {0x1d08, 0xa9},
344 {0x0a3c, 0xd0}, {0x0a44, 0xd0},
345 {0x0a48, 0x01}, {0x0a4c, 0x0d},
346 {0x0a54, 0xe0}, {0x0a5c, 0xe0},
347 {0x0a64, 0xa8}, {0x1a3c, 0xd0},
348 {0x1a44, 0xd0}, {0x1a48, 0x01},
349 {0x1a4c, 0x0d}, {0x1a54, 0xe0},
350 {0x1a5c, 0xe0}, {0x1a64, 0xa8}
351 };
352
353 static const struct reg_sequence udphy_init_sequence[] = {
354 {0x0104, 0x44}, {0x0234, 0xE8},
355 {0x0248, 0x44}, {0x028C, 0x18},
356 {0x081C, 0xE5}, {0x0878, 0x00},
357 {0x0994, 0x1C}, {0x0AF0, 0x00},
358 {0x181C, 0xE5}, {0x1878, 0x00},
359 {0x1994, 0x1C}, {0x1AF0, 0x00},
360 {0x0428, 0x60}, {0x0D58, 0x33},
361 {0x1D58, 0x33}, {0x0990, 0x74},
362 {0x0D64, 0x17}, {0x08C8, 0x13},
363 {0x1990, 0x74}, {0x1D64, 0x17},
364 {0x18C8, 0x13}, {0x0D90, 0x40},
365 {0x0DA8, 0x40}, {0x0DC0, 0x40},
366 {0x0DD8, 0x40}, {0x1D90, 0x40},
367 {0x1DA8, 0x40}, {0x1DC0, 0x40},
368 {0x1DD8, 0x40}, {0x03C0, 0x30},
369 {0x03C4, 0x06}, {0x0E10, 0x00},
370 {0x1E10, 0x00}, {0x043C, 0x0F},
371 {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
372 {0x0D34, 0x0F}, {0x1D34, 0x0F},
373 {0x08FC, 0x2A}, {0x0914, 0x28},
374 {0x0A30, 0x03}, {0x0E38, 0x03},
375 {0x0ECC, 0x27}, {0x0ED0, 0x22},
376 {0x0ED4, 0x26}, {0x18FC, 0x2A},
377 {0x1914, 0x28}, {0x1A30, 0x03},
378 {0x1E38, 0x03}, {0x1ECC, 0x27},
379 {0x1ED0, 0x22}, {0x1ED4, 0x26},
380 {0x0048, 0x0F}, {0x0060, 0x3C},
381 {0x0064, 0xF7}, {0x006C, 0x20},
382 {0x0070, 0x7D}, {0x0074, 0x68},
383 {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
384 {0x0440, 0x3F}, {0x10D4, 0x08},
385 {0x20D4, 0x08}, {0x00D4, 0x30},
386 {0x0024, 0x6e},
387 };
388
grfreg_write(struct regmap * base,const struct udphy_grf_reg * reg,bool en)389 static inline int grfreg_write(struct regmap *base,
390 const struct udphy_grf_reg *reg, bool en)
391 {
392 u32 val, mask, tmp;
393
394 tmp = en ? reg->enable : reg->disable;
395 mask = GENMASK(reg->bitend, reg->bitstart);
396 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
397
398 return regmap_write(base, reg->offset, val);
399 }
400
__regmap_multi_reg_write(struct regmap * map,const struct reg_sequence * regs,int num_regs)401 static int __regmap_multi_reg_write(struct regmap *map,
402 const struct reg_sequence *regs, int num_regs)
403 {
404 int i, ret = 0;
405
406 for (i = 0; i < num_regs; i++) {
407 ret = regmap_write(map, regs[i].reg, regs[i].def);
408
409 if (regs[i].delay_us)
410 udelay(regs[i].delay_us);
411 }
412
413 return ret;
414 }
415
udphy_clk_init(struct rockchip_udphy * udphy,struct udevice * dev)416 static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)
417 {
418 return 0;
419 }
420
udphy_reset_init(struct rockchip_udphy * udphy,struct udevice * dev)421 static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)
422 {
423 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
424 int idx;
425 int ret;
426
427 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
428 sizeof(*udphy->rsts), GFP_KERNEL);
429 if (!udphy->rsts)
430 return -ENOMEM;
431
432 for (idx = 0; idx < cfg->num_rsts; idx++) {
433 const char *name = cfg->rst_list[idx];
434
435 ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);
436 if (ret) {
437 dev_err(dev, "failed to get %s reset\n", name);
438 goto err;
439 }
440
441 reset_assert(&udphy->rsts[idx]);
442 }
443
444 return 0;
445
446 err:
447 devm_kfree(dev, udphy->rsts);
448 return ret;
449 }
450
udphy_get_rst_idx(const char * const * list,int num,char * name)451 static int udphy_get_rst_idx(const char * const *list, int num, char *name)
452 {
453 int idx;
454
455 for (idx = 0; idx < num; idx++) {
456 if (!strcmp(list[idx], name))
457 return idx;
458 }
459
460 return -EINVAL;
461 }
462
udphy_reset_assert(struct rockchip_udphy * udphy,char * name)463 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
464 {
465 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
466 int idx;
467
468 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
469 if (idx < 0)
470 return idx;
471
472 return reset_assert(&udphy->rsts[idx]);
473 }
474
udphy_reset_deassert(struct rockchip_udphy * udphy,char * name)475 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
476 {
477 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
478 int idx;
479
480 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
481 if (idx < 0)
482 return idx;
483
484 return reset_deassert(&udphy->rsts[idx]);
485 }
486
udphy_u3_port_disable(struct rockchip_udphy * udphy,u8 disable)487 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
488 {
489 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
490 const struct udphy_grf_reg *preg;
491
492 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
493 grfreg_write(udphy->usbgrf, preg, disable);
494 }
495
496 __maybe_unused
udphy_usb_bvalid_enable(struct rockchip_udphy * udphy,u8 enable)497 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
498 {
499 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
500
501 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
502 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
503 }
504
505 /*
506 * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
507 *
508 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
509 * ---------------------------------------------------------------------------
510 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
511 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
512 * C/E(Normal) dpln3 dpln2 dpln0 dpln1
513 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
514 * D/F(Normal) usbrx usbtx dpln0 dpln1
515 * D/F(Flip ) dpln0 dpln1 usbrx usbtx
516 * A(Normal ) dpln3 dpln1 dpln2 dpln0
517 * A(Flip ) dpln2 dpln0 dpln3 dpln1
518 * B(Normal ) usbrx usbtx dpln1 dpln0
519 * B(Flip ) dpln1 dpln0 usbrx usbtx
520 * ---------------------------------------------------------------------------
521 *
522 * 2 Mapping the lanes in dtsi
523 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
524 * sample as follow:
525 * ---------------------------------------------------------------------------
526 * B11-B10 A2-A3 A11-A10 B2-B3
527 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
528 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
529 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
530 * ---------------------------------------------------------------------------
531 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
532 * sample as follow:
533 * ---------------------------------------------------------------------------
534 * B11-B10 A2-A3 A11-A10 B2-B3
535 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
536 * <0 1> dpln0 dpln1 usbrx usbtx
537 * <2 3> usbrx usbtx dpln0 dpln1
538 * ---------------------------------------------------------------------------
539 */
udphy_dplane_select(struct rockchip_udphy * udphy)540 static int udphy_dplane_select(struct rockchip_udphy *udphy)
541 {
542 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
543 u32 value = 0;
544
545 switch (udphy->mode) {
546 case UDPHY_MODE_DP:
547 value |= 2 << udphy->dp_lane_sel[2] * 2;
548 value |= 3 << udphy->dp_lane_sel[3] * 2;
549 case UDPHY_MODE_DP_USB:
550 value |= 0 << udphy->dp_lane_sel[0] * 2;
551 value |= 1 << udphy->dp_lane_sel[1] * 2;
552 break;
553 case UDPHY_MODE_USB:
554 break;
555 default:
556 break;
557 }
558
559 regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg,
560 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
561 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
562 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
563
564 return 0;
565 }
566
udphy_dplane_get(struct rockchip_udphy * udphy)567 static int udphy_dplane_get(struct rockchip_udphy *udphy)
568 {
569 int dp_lanes;
570
571 switch (udphy->mode) {
572 case UDPHY_MODE_DP:
573 dp_lanes = 4;
574 break;
575 case UDPHY_MODE_DP_USB:
576 dp_lanes = 2;
577 break;
578 case UDPHY_MODE_USB:
579 /* fallthrough; */
580 default:
581 dp_lanes = 0;
582 break;
583 }
584
585 return dp_lanes;
586 }
587
udphy_dplane_enable(struct rockchip_udphy * udphy,int dp_lanes)588 static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
589 {
590 int i;
591 u32 val = 0;
592
593 for (i = 0; i < dp_lanes; i++)
594 val |= BIT(udphy->dp_lane_sel[i]);
595
596 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
597 FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
598
599 if (!dp_lanes)
600 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
601 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
602
603 return 0;
604 }
605
606
607 __maybe_unused
udphy_set_typec_default_mapping(struct rockchip_udphy * udphy)608 static int udphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
609 {
610 if (udphy->flip) {
611 udphy->dp_lane_sel[0] = 0;
612 udphy->dp_lane_sel[1] = 1;
613 udphy->dp_lane_sel[2] = 3;
614 udphy->dp_lane_sel[3] = 2;
615 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
616 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
617 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
618 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
619 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
620 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
621 } else {
622 udphy->dp_lane_sel[0] = 2;
623 udphy->dp_lane_sel[1] = 3;
624 udphy->dp_lane_sel[2] = 1;
625 udphy->dp_lane_sel[3] = 0;
626 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
627 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
628 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
629 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
630 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
631 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
632 }
633
634 udphy->mode = UDPHY_MODE_DP_USB;
635
636 return 0;
637 }
638
udphy_refclk_set(struct rockchip_udphy * udphy)639 static int udphy_refclk_set(struct rockchip_udphy *udphy)
640 {
641 int ret;
642
643 /* configure phy reference clock */
644 ret = __regmap_multi_reg_write(udphy->pma_regmap, udphy_24m_refclk_cfg,
645 ARRAY_SIZE(udphy_24m_refclk_cfg));
646 if (ret)
647 return ret;
648
649 return 0;
650 }
651
udphy_status_check(struct rockchip_udphy * udphy)652 static int udphy_status_check(struct rockchip_udphy *udphy)
653 {
654 unsigned int val;
655 int ret;
656
657 /* LCPLL check */
658 if (udphy->mode & UDPHY_MODE_USB) {
659 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
660 val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
661 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100);
662 if (ret) {
663 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
664 return ret;
665 }
666 }
667
668 if (udphy->mode & UDPHY_MODE_USB) {
669 if (!udphy->flip) {
670 ret = regmap_read_poll_timeout(udphy->pma_regmap,
671 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
672 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
673 200, 100);
674 if (ret)
675 dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
676 } else {
677 ret = regmap_read_poll_timeout(udphy->pma_regmap,
678 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
679 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
680 200, 100);
681 if (ret)
682 dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
683 }
684 }
685
686 return 0;
687 }
688
udphy_init(struct rockchip_udphy * udphy)689 static int udphy_init(struct rockchip_udphy *udphy)
690 {
691 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
692 int ret;
693
694 /* enable rx lfps for usb */
695 if (udphy->mode & UDPHY_MODE_USB)
696 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
697
698 /* Step 1: power on pma and deassert apb rstn */
699 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
700
701 udphy_reset_deassert(udphy, "pma_apb");
702 udphy_reset_deassert(udphy, "pcs_apb");
703
704 /* Step 2: set init sequence and phy refclk */
705 ret = __regmap_multi_reg_write(udphy->pma_regmap, udphy_init_sequence,
706 ARRAY_SIZE(udphy_init_sequence));
707 if (ret) {
708 dev_err(udphy->dev, "init sequence set error %d\n", ret);
709 goto assert_apb;
710 }
711
712 ret = udphy_refclk_set(udphy);
713 if (ret) {
714 dev_err(udphy->dev, "refclk set error %d\n", ret);
715 goto assert_apb;
716 }
717
718 /* Step 3: configure lane mux */
719 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
720 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
721 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
722 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
723 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
724 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
725 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
726
727 /* Step 4: deassert init rstn and wait for 200ns from datasheet */
728 if (udphy->mode & UDPHY_MODE_USB)
729 udphy_reset_deassert(udphy, "init");
730
731 if (udphy->mode & UDPHY_MODE_DP) {
732 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
733 CMN_DP_INIT_RSTN,
734 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
735 }
736
737 udelay(1);
738
739 /* Step 5: deassert cmn/lane rstn */
740 if (udphy->mode & UDPHY_MODE_USB) {
741 udphy_reset_deassert(udphy, "cmn");
742 udphy_reset_deassert(udphy, "lane");
743 }
744
745 /* Step 6: wait for lock done of pll */
746 ret = udphy_status_check(udphy);
747 if (ret)
748 goto assert_phy;
749
750 return 0;
751
752 assert_phy:
753 udphy_reset_assert(udphy, "init");
754 udphy_reset_assert(udphy, "cmn");
755 udphy_reset_assert(udphy, "lane");
756
757 assert_apb:
758 udphy_reset_assert(udphy, "pma_apb");
759 udphy_reset_assert(udphy, "pcs_apb");
760 return ret;
761 }
762
udphy_setup(struct rockchip_udphy * udphy)763 static int udphy_setup(struct rockchip_udphy *udphy)
764 {
765 int ret = 0;
766
767 ret = udphy_init(udphy);
768 if (ret)
769 dev_err(udphy->dev, "failed to init combophy\n");
770
771 return ret;
772 }
773
udphy_disable(struct rockchip_udphy * udphy)774 static int udphy_disable(struct rockchip_udphy *udphy)
775 {
776 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
777 int i;
778
779 for (i = 0; i < cfg->num_rsts; i++)
780 reset_assert(&udphy->rsts[i]);
781
782 return 0;
783 }
784
udphy_parse_lane_mux_data(struct rockchip_udphy * udphy,struct udevice * dev)785 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct udevice *dev)
786 {
787 const void *prop;
788 int ret, i, len, num_lanes;
789
790 prop = dev_read_prop(dev, "rockchip,dp-lane-mux", &len);
791 if (!prop) {
792 dev_dbg(dev, "failed to find dp lane mux, following dp alt mode\n");
793 udphy->mode = UDPHY_MODE_USB;
794 return 0;
795 }
796
797 num_lanes = len / sizeof(u32);
798
799 if (num_lanes != 2 && num_lanes != 4) {
800 dev_err(dev, "invalid number of lane mux\n");
801 return -EINVAL;
802 }
803
804 ret = dev_read_u32_array(dev, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
805 if (ret) {
806 dev_err(dev, "get dp lane mux failed\n");
807 return -EINVAL;
808 }
809
810 for (i = 0; i < num_lanes; i++) {
811 int j;
812
813 if (udphy->dp_lane_sel[i] > 3) {
814 dev_err(dev, "lane mux between 0 and 3, exceeding the range\n");
815 return -EINVAL;
816 }
817
818 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
819
820 for (j = i + 1; j < num_lanes; j++) {
821 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
822 dev_err(dev, "set repeat lane mux value\n");
823 return -EINVAL;
824 }
825 }
826 }
827
828 udphy->mode = UDPHY_MODE_DP;
829 if (num_lanes == 2) {
830 udphy->mode |= UDPHY_MODE_USB;
831 udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;
832 }
833
834 return 0;
835 }
836
udphy_parse_dt(struct rockchip_udphy * udphy,struct udevice * dev)837 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
838 {
839 enum usb_device_speed maximum_speed;
840 int ret;
841
842 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,u2phy-grf");
843 if (IS_ERR(udphy->u2phygrf)) {
844 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
845 dev_warn(dev, "missing u2phy-grf dt node\n");
846 udphy->u2phygrf = NULL;
847 } else {
848 return PTR_ERR(udphy->u2phygrf);
849 }
850 }
851
852 udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usbdpphy-grf");
853 if (IS_ERR(udphy->udphygrf)) {
854 if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
855 dev_warn(dev, "missing usbdpphy-grf dt node\n");
856 udphy->udphygrf = NULL;
857 } else {
858 return PTR_ERR(udphy->udphygrf);
859 }
860 }
861
862 udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usb-grf");
863 if (IS_ERR(udphy->usbgrf)) {
864 if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
865 dev_warn(dev, "missing usb-grf dt node\n");
866 udphy->usbgrf = NULL;
867 } else {
868 return PTR_ERR(udphy->usbgrf);
869 }
870 }
871
872 udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");
873 if (IS_ERR(udphy->vogrf)) {
874 if (PTR_ERR(udphy->vogrf) == -ENODEV) {
875 dev_warn(dev, "missing vo-grf dt node\n");
876 udphy->vogrf = NULL;
877 } else {
878 return PTR_ERR(udphy->vogrf);
879 }
880 }
881
882 ret = udphy_parse_lane_mux_data(udphy, dev);
883 if (ret)
884 return ret;
885
886 if (dev_read_prop(dev, "maximum-speed", NULL)) {
887 maximum_speed = usb_get_maximum_speed(dev->node);
888 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
889 }
890
891 ret = udphy_clk_init(udphy, dev);
892 if (ret)
893 return ret;
894
895 ret = udphy_reset_init(udphy, dev);
896 if (ret)
897 return ret;
898
899 return 0;
900 }
901
udphy_power_on(struct rockchip_udphy * udphy,u8 mode)902 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
903 {
904 int ret;
905
906 if (!(udphy->mode & mode)) {
907 printf("%s: mode 0x%02x is not support\n", udphy->dev->name,
908 mode);
909 return -EINVAL;
910 }
911
912 if (udphy->status == UDPHY_MODE_NONE) {
913 udphy->mode_change = false;
914 ret = udphy_setup(udphy);
915 if (ret)
916 return ret;
917
918 if (udphy->mode & UDPHY_MODE_USB)
919 udphy_u3_port_disable(udphy, false);
920 } else if (udphy->mode_change) {
921 udphy->mode_change = false;
922 udphy->status = UDPHY_MODE_NONE;
923 if (udphy->mode == UDPHY_MODE_DP)
924 udphy_u3_port_disable(udphy, true);
925
926 ret = udphy_disable(udphy);
927 if (ret)
928 return ret;
929 ret = udphy_setup(udphy);
930 if (ret)
931 return ret;
932 }
933
934 udphy->status |= mode;
935
936 return 0;
937 }
938
udphy_power_off(struct rockchip_udphy * udphy,u8 mode)939 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
940 {
941 int ret;
942
943 if (!(udphy->mode & mode)) {
944 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
945 return 0;
946 }
947
948 if (!udphy->status)
949 return 0;
950
951 udphy->status &= ~mode;
952
953 if (udphy->status == UDPHY_MODE_NONE) {
954 ret = udphy_disable(udphy);
955 if (ret)
956 return ret;
957 }
958
959 return 0;
960 }
961
rockchip_dpphy_power_on(struct phy * phy)962 static int rockchip_dpphy_power_on(struct phy *phy)
963 {
964 struct udevice *parent = phy->dev->parent;
965 struct rockchip_udphy *udphy = dev_get_priv(parent);
966 int ret, dp_lanes;
967
968 dp_lanes = udphy_dplane_get(udphy);
969 phy->attrs.bus_width = dp_lanes;
970 phy->attrs.max_link_rate = udphy->max_link_rate;
971
972 ret = udphy_power_on(udphy, UDPHY_MODE_DP);
973 if (ret)
974 return ret;
975
976 ret = udphy_dplane_enable(udphy, dp_lanes);
977 if (ret)
978 return ret;
979
980 return udphy_dplane_select(udphy);
981 }
982
rockchip_dpphy_power_off(struct phy * phy)983 static int rockchip_dpphy_power_off(struct phy *phy)
984 {
985 struct udevice *parent = phy->dev->parent;
986 struct rockchip_udphy *udphy = dev_get_priv(parent);
987 int ret;
988
989 ret = udphy_dplane_enable(udphy, 0);
990 if (ret)
991 return ret;
992
993 return udphy_power_off(udphy, UDPHY_MODE_DP);
994 }
995
rockchip_dpphy_verify_config(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)996 static int rockchip_dpphy_verify_config(struct rockchip_udphy *udphy,
997 struct phy_configure_opts_dp *dp)
998 {
999 int i;
1000
1001 /* If changing link rate was required, verify it's supported. */
1002 if (dp->set_rate) {
1003 switch (dp->link_rate) {
1004 case 1620:
1005 case 2700:
1006 case 5400:
1007 case 8100:
1008 /* valid bit rate */
1009 break;
1010 default:
1011 return -EINVAL;
1012 }
1013 }
1014
1015 /* Verify lane count. */
1016 switch (dp->lanes) {
1017 case 1:
1018 case 2:
1019 case 4:
1020 /* valid lane count. */
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 /*
1027 * If changing voltages is required, check swing and pre-emphasis
1028 * levels, per-lane.
1029 */
1030 if (dp->set_voltages) {
1031 /* Lane count verified previously. */
1032 for (i = 0; i < dp->lanes; i++) {
1033 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1034 return -EINVAL;
1035
1036 /*
1037 * Sum of voltage swing and pre-emphasis levels cannot
1038 * exceed 3.
1039 */
1040 if (dp->voltage[i] + dp->pre[i] > 3)
1041 return -EINVAL;
1042 }
1043 }
1044
1045 return 0;
1046 }
1047
dp_phy_set_rate(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)1048 static int dp_phy_set_rate(struct rockchip_udphy *udphy,
1049 struct phy_configure_opts_dp *dp)
1050 {
1051 u32 val;
1052 int ret;
1053
1054 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1055 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
1056
1057 switch (dp->link_rate) {
1058 case 1620:
1059 udphy->bw = DP_BW_RBR;
1060 break;
1061 case 2700:
1062 udphy->bw = DP_BW_HBR;
1063 break;
1064 case 5400:
1065 udphy->bw = DP_BW_HBR2;
1066 break;
1067 case 8100:
1068 udphy->bw = DP_BW_HBR3;
1069 break;
1070 default:
1071 return -EINVAL;
1072 }
1073
1074 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
1075 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));
1076 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
1077 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
1078 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
1079 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
1080
1081 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
1082 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
1083 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
1084 0, 1000);
1085 if (ret) {
1086 printf("ROPLL is not lock\n");
1087 return ret;
1088 }
1089
1090 return 0;
1091 }
1092
dp_phy_set_voltage(struct rockchip_udphy * udphy,u8 bw,u32 voltage,u32 pre,u32 lane)1093 static void dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw,
1094 u32 voltage, u32 pre, u32 lane)
1095 {
1096 u32 offset = 0x800 * lane;
1097 u32 val;
1098 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1099 const struct dp_tx_drv_ctrl (*dp_ctrl)[4];
1100
1101 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw];
1102 val = dp_ctrl[voltage][pre].trsv_reg0204;
1103 regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
1104
1105 val = dp_ctrl[voltage][pre].trsv_reg0205;
1106 regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
1107
1108 val = dp_ctrl[voltage][pre].trsv_reg0206;
1109 regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
1110
1111 val = dp_ctrl[voltage][pre].trsv_reg0207;
1112 regmap_write(udphy->pma_regmap, 0x081c + offset, val);
1113 }
1114
dp_phy_set_voltages(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)1115 static int dp_phy_set_voltages(struct rockchip_udphy *udphy,
1116 struct phy_configure_opts_dp *dp)
1117 {
1118 u32 i, lane;
1119
1120 for (i = 0; i < dp->lanes; i++) {
1121 lane = udphy->dp_lane_sel[i];
1122 switch (dp->link_rate) {
1123 case 1620:
1124 case 2700:
1125 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
1126 LN_ANA_TX_SER_TXCLK_INV,
1127 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
1128 udphy->lane_mux_sel[lane]));
1129 break;
1130 case 5400:
1131 case 8100:
1132 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
1133 LN_ANA_TX_SER_TXCLK_INV,
1134 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
1135 break;
1136 }
1137
1138 dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane);
1139 }
1140
1141 return 0;
1142 }
1143
rockchip_dpphy_configure(struct phy * phy,union phy_configure_opts * opts)1144 static int rockchip_dpphy_configure(struct phy *phy,
1145 union phy_configure_opts *opts)
1146 {
1147 struct udevice *parent = phy->dev->parent;
1148 struct rockchip_udphy *udphy = dev_get_priv(parent);
1149 int ret;
1150
1151 ret = rockchip_dpphy_verify_config(udphy, &opts->dp);
1152 if (ret)
1153 return ret;
1154
1155 if (opts->dp.set_rate) {
1156 ret = dp_phy_set_rate(udphy, &opts->dp);
1157 if (ret) {
1158 printf("%s: rockchip_hdptx_phy_set_rate failed\n",
1159 udphy->dev->name);
1160 return ret;
1161 }
1162 }
1163
1164 if (opts->dp.set_voltages) {
1165 ret = dp_phy_set_voltages(udphy, &opts->dp);
1166 if (ret) {
1167 printf("%s: rockchip_dp_phy_set_voltages failed\n",
1168 udphy->dev->name);
1169 return ret;
1170 }
1171 }
1172
1173 return 0;
1174 }
1175
1176 static const struct phy_ops rockchip_dpphy_ops = {
1177 .power_on = rockchip_dpphy_power_on,
1178 .power_off = rockchip_dpphy_power_off,
1179 .configure = rockchip_dpphy_configure,
1180 };
1181
rockchip_u3phy_init(struct phy * phy)1182 static int rockchip_u3phy_init(struct phy *phy)
1183 {
1184 struct udevice *parent = phy->dev->parent;
1185 struct rockchip_udphy *udphy = dev_get_priv(parent);
1186
1187 /* DP only or high-speed, disable U3 port */
1188 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
1189 udphy_u3_port_disable(udphy, true);
1190 return 0;
1191 }
1192
1193 return udphy_power_on(udphy, UDPHY_MODE_USB);
1194 }
1195
rockchip_u3phy_exit(struct phy * phy)1196 static int rockchip_u3phy_exit(struct phy *phy)
1197 {
1198 struct udevice *parent = phy->dev->parent;
1199 struct rockchip_udphy *udphy = dev_get_priv(parent);
1200
1201 /* DP only or high-speed */
1202 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
1203 return 0;
1204
1205 return udphy_power_off(udphy, UDPHY_MODE_USB);
1206 }
1207
1208 static const struct phy_ops rockchip_u3phy_ops = {
1209 .init = rockchip_u3phy_init,
1210 .exit = rockchip_u3phy_exit,
1211 };
1212
rockchip_u3phy_uboot_init(fdt_addr_t phy_addr)1213 int rockchip_u3phy_uboot_init(fdt_addr_t phy_addr)
1214 {
1215 struct udevice *udev = NULL;
1216 struct udevice *dev;
1217 struct uclass *uc;
1218 const struct driver *find_drv;
1219 struct rockchip_udphy *udphy;
1220 unsigned int val;
1221 int ret;
1222
1223 ret = uclass_get(UCLASS_PHY, &uc);
1224 if (ret)
1225 return ret;
1226
1227 find_drv = DM_GET_DRIVER(rockchip_udphy);
1228 list_for_each_entry(dev, &uc->dev_head, uclass_node) {
1229 if (dev->driver == find_drv && dev_read_addr(dev) == phy_addr) {
1230 ret = uclass_get_device_tail(dev, 0, &udev);
1231 break;
1232 }
1233 }
1234
1235 if (!udev || ret) {
1236 ret = ret ? ret : -ENODEV;
1237 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret);
1238 return ret;
1239 }
1240
1241 /* DP only or high-speed, disable U3 port */
1242 udphy = dev_get_priv(udev);
1243 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
1244 pr_err("%s: udphy mode not support usb3\n", __func__);
1245 goto disable_u3;
1246 }
1247
1248 udphy->flip = false;
1249 udphy_set_typec_default_mapping(udphy);
1250
1251 ret = udphy_power_on(udphy, UDPHY_MODE_USB);
1252 if (ret) {
1253 pr_err("%s: udphy power on failed: %d\n", __func__, ret);
1254 goto disable_u3;
1255 }
1256
1257 ret = regmap_read_poll_timeout(udphy->pma_regmap,
1258 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
1259 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
1260 200, 100);
1261 if (ret) {
1262 pr_err("%s: udphy rx cdr lock timeout\n", __func__);
1263 goto disable_u3;
1264 }
1265
1266 return 0;
1267
1268 disable_u3:
1269 udphy_u3_port_disable(udphy, true);
1270
1271 return -EOPNOTSUPP;
1272 }
1273
rockchip_udphy_probe(struct udevice * dev)1274 static int rockchip_udphy_probe(struct udevice *dev)
1275 {
1276 struct rockchip_udphy *udphy = dev_get_priv(dev);
1277 const struct rockchip_udphy_cfg *phy_cfgs;
1278 int id, ret;
1279
1280 udphy->dev = dev;
1281
1282 id = of_alias_get_id(ofnode_to_np(dev->node), "usbdp");
1283 if (id < 0)
1284 id = 0;
1285 udphy->id = id;
1286
1287 phy_cfgs = (const struct rockchip_udphy_cfg *) dev_get_driver_data(dev);
1288 if (!phy_cfgs) {
1289 dev_err(dev, "unable to get phy_cfgs\n");
1290 return -EINVAL;
1291 }
1292 udphy->cfgs = phy_cfgs;
1293
1294 ret = regmap_init_mem(dev, &udphy->pma_regmap);
1295 if (ret)
1296 return ret;
1297 udphy->pma_regmap->base += UDPHY_PMA;
1298
1299 ret = udphy_parse_dt(udphy, dev);
1300 if (ret)
1301 return ret;
1302
1303 return 0;
1304 }
1305
rockchip_udphy_bind(struct udevice * parent)1306 static int rockchip_udphy_bind(struct udevice *parent)
1307 {
1308 struct udevice *child;
1309 ofnode subnode;
1310 const char *node_name;
1311 int ret;
1312
1313 dev_for_each_subnode(subnode, parent) {
1314 if (!ofnode_valid(subnode)) {
1315 printf("%s: no subnode for %s\n", __func__, parent->name);
1316 return -ENXIO;
1317 }
1318
1319 node_name = ofnode_get_name(subnode);
1320 debug("%s: subnode %s\n", __func__, node_name);
1321
1322 if (!strcasecmp(node_name, "u3-port")) {
1323 ret = device_bind_driver_to_node(parent,
1324 "rockchip_udphy_u3_port",
1325 node_name, subnode, &child);
1326 if (ret) {
1327 printf("%s: '%s' cannot bind its driver\n",
1328 __func__, node_name);
1329 return ret;
1330 }
1331 } else if (!strcasecmp(node_name, "dp-port")) {
1332 ret = device_bind_driver_to_node(parent,
1333 "rockchip_udphy_dp_port",
1334 node_name, subnode, &child);
1335 if (ret) {
1336 printf("%s: '%s' cannot bind its driver\n",
1337 __func__, node_name);
1338 return ret;
1339 }
1340 }
1341 }
1342
1343 return 0;
1344 }
1345
rockchip_dpphy_probe(struct udevice * dev)1346 static int rockchip_dpphy_probe(struct udevice *dev)
1347 {
1348 struct rockchip_udphy *udphy = dev_get_priv(dev->parent);
1349 u32 max_link_rate;
1350
1351 max_link_rate = dev_read_u32_default(dev, "max-link-rate", 8100);
1352 switch (max_link_rate) {
1353 case 1620:
1354 case 2700:
1355 case 5400:
1356 case 8100:
1357 break;
1358 default:
1359 dev_warn(dev, "invalid max-link-rate %d, using 8100\n", max_link_rate);
1360 max_link_rate = 8100;
1361 break;
1362 }
1363
1364 udphy->max_link_rate = max_link_rate;
1365
1366 return 0;
1367 }
1368
1369 static const char * const udphy_rst_list[] = {
1370 "init", "cmn", "lane", "pcs_apb", "pma_apb"
1371 };
1372
1373 #ifdef CONFIG_ROCKCHIP_RK3576
1374 static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = {
1375 .num_rsts = ARRAY_SIZE(udphy_rst_list),
1376 .rst_list = udphy_rst_list,
1377 .grfcfg = {
1378 /* u2phy-grf */
1379 .bvalid_phy_con = { 0x0010, 1, 0, 0x2, 0x3 },
1380 .bvalid_grf_con = { 0x0000, 15, 14, 0x1, 0x3 },
1381
1382 /* usb-grf */
1383 .usb3otg0_cfg = { 0x0030, 15, 0, 0x1100, 0x0188 },
1384
1385 /* usbdpphy-grf */
1386 .low_pwrn = { 0x0004, 13, 13, 0, 1 },
1387 .rx_lfps = { 0x0004, 14, 14, 0, 1 },
1388 },
1389 .vogrfcfg = {
1390 {
1391 .dp_lane_reg = 0x0000,
1392 },
1393 {
1394 .dp_lane_reg = 0x0008,
1395 },
1396 },
1397 .dp_tx_ctrl_cfg = {
1398 rk3576_dp_tx_drv_ctrl_rbr_hbr,
1399 rk3576_dp_tx_drv_ctrl_rbr_hbr,
1400 rk3588_dp_tx_drv_ctrl_hbr2,
1401 rk3588_dp_tx_drv_ctrl_hbr3,
1402 },
1403 };
1404 #endif
1405
1406 #ifdef CONFIG_ROCKCHIP_RK3588
1407 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
1408 .num_rsts = ARRAY_SIZE(udphy_rst_list),
1409 .rst_list = udphy_rst_list,
1410 .grfcfg = {
1411 /* u2phy-grf */
1412 .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 },
1413 .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 },
1414
1415 /* usb-grf */
1416 .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 },
1417 .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 },
1418
1419 /* usbdpphy-grf */
1420 .low_pwrn = { 0x0004, 13, 13, 0, 1 },
1421 .rx_lfps = { 0x0004, 14, 14, 0, 1 },
1422 },
1423 .vogrfcfg = {
1424 {
1425 .dp_lane_reg = 0x0000,
1426 },
1427 {
1428 .dp_lane_reg = 0x0008,
1429 },
1430 },
1431 .dp_tx_ctrl_cfg = {
1432 rk3588_dp_tx_drv_ctrl_rbr_hbr,
1433 rk3588_dp_tx_drv_ctrl_rbr_hbr,
1434 rk3588_dp_tx_drv_ctrl_hbr2,
1435 rk3588_dp_tx_drv_ctrl_hbr3,
1436 },
1437 };
1438 #endif
1439
1440 static const struct udevice_id rockchip_udphy_dt_match[] = {
1441 #ifdef CONFIG_ROCKCHIP_RK3576
1442 {
1443 .compatible = "rockchip,rk3576-usbdp-phy",
1444 .data = (ulong)&rk3576_udphy_cfgs
1445 },
1446 #endif
1447 #ifdef CONFIG_ROCKCHIP_RK3588
1448 {
1449 .compatible = "rockchip,rk3588-usbdp-phy",
1450 .data = (ulong)&rk3588_udphy_cfgs
1451 },
1452 #endif
1453 { /* sentinel */ }
1454 };
1455
1456 U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
1457 .name = "rockchip_udphy_u3_port",
1458 .id = UCLASS_PHY,
1459 .ops = &rockchip_u3phy_ops,
1460 };
1461
1462 U_BOOT_DRIVER(rockchip_udphy_dp_port) = {
1463 .name = "rockchip_udphy_dp_port",
1464 .id = UCLASS_PHY,
1465 .ops = &rockchip_dpphy_ops,
1466 .probe = rockchip_dpphy_probe,
1467 };
1468
1469 U_BOOT_DRIVER(rockchip_udphy) = {
1470 .name = "rockchip_udphy",
1471 .id = UCLASS_PHY,
1472 .of_match = rockchip_udphy_dt_match,
1473 .probe = rockchip_udphy_probe,
1474 .bind = rockchip_udphy_bind,
1475 .priv_auto_alloc_size = sizeof(struct rockchip_udphy),
1476 };
1477