1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTL8703B_PHYCFG_C_
16
17 #include <rtl8703b_hal.h>
18
19
20 /*---------------------------Define Local Constant---------------------------*/
21 /* Channel switch:The size of command tables for switch channel*/
22 #define MAX_PRECMD_CNT 16
23 #define MAX_RFDEPENDCMD_CNT 16
24 #define MAX_POSTCMD_CNT 16
25
26 #define MAX_DOZE_WAITING_TIMES_9x 64
27
28 /*---------------------------Define Local Constant---------------------------*/
29
30
31 /*------------------------Define global variable-----------------------------*/
32
33 /*------------------------Define local variable------------------------------*/
34
35
36 /*--------------------Define export function prototype-----------------------*/
37 /* Please refer to header file
38 *--------------------Define export function prototype-----------------------*/
39
40 /*----------------------------Function Body----------------------------------*/
41 /*
42 * 1. BB register R/W API
43 * */
44
45 /**
46 * Function: phy_CalculateBitShift
47 *
48 * OverView: Get shifted position of the BitMask
49 *
50 * Input:
51 * u32 BitMask,
52 *
53 * Output: none
54 * Return: u32 Return the shift bit bit position of the mask
55 */
56 static u32
phy_CalculateBitShift(u32 BitMask)57 phy_CalculateBitShift(
58 u32 BitMask
59 )
60 {
61 u32 i;
62
63 for (i = 0; i <= 31; i++) {
64 if (((BitMask >> i) & 0x1) == 1)
65 break;
66 }
67
68 return i;
69 }
70
71
72 /**
73 * Function: PHY_QueryBBReg
74 *
75 * OverView: Read "sepcific bits" from BB register
76 *
77 * Input:
78 * PADAPTER Adapter,
79 * u32 RegAddr, //The target address to be readback
80 * u32 BitMask //The target bit position in the target address
81 * //to be readback
82 * Output: None
83 * Return: u32 Data //The readback register value
84 * Note: This function is equal to "GetRegSetting" in PHY programming guide
85 */
86 u32
PHY_QueryBBReg_8703B(PADAPTER Adapter,u32 RegAddr,u32 BitMask)87 PHY_QueryBBReg_8703B(
88 PADAPTER Adapter,
89 u32 RegAddr,
90 u32 BitMask
91 )
92 {
93 u32 ReturnValue = 0, OriginalValue, BitShift;
94 u16 BBWaitCounter = 0;
95
96 #if (DISABLE_BB_RF == 1)
97 return 0;
98 #endif
99
100
101 OriginalValue = rtw_read32(Adapter, RegAddr);
102 BitShift = phy_CalculateBitShift(BitMask);
103 ReturnValue = (OriginalValue & BitMask) >> BitShift;
104
105 return ReturnValue;
106
107 }
108
109
110 /**
111 * Function: PHY_SetBBReg
112 *
113 * OverView: Write "Specific bits" to BB register (page 8~)
114 *
115 * Input:
116 * PADAPTER Adapter,
117 * u32 RegAddr, //The target address to be modified
118 * u32 BitMask //The target bit position in the target address
119 * //to be modified
120 * u32 Data //The new register value in the target bit position
121 * //of the target address
122 *
123 * Output: None
124 * Return: None
125 * Note: This function is equal to "PutRegSetting" in PHY programming guide
126 */
127
128 void
PHY_SetBBReg_8703B(PADAPTER Adapter,u32 RegAddr,u32 BitMask,u32 Data)129 PHY_SetBBReg_8703B(
130 PADAPTER Adapter,
131 u32 RegAddr,
132 u32 BitMask,
133 u32 Data
134 )
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
137 /* u16 BBWaitCounter = 0; */
138 u32 OriginalValue, BitShift;
139
140 #if (DISABLE_BB_RF == 1)
141 return;
142 #endif
143
144
145 if (BitMask != bMaskDWord) { /* if not "double word" write */
146 OriginalValue = rtw_read32(Adapter, RegAddr);
147 BitShift = phy_CalculateBitShift(BitMask);
148 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
149 }
150
151 rtw_write32(Adapter, RegAddr, Data);
152
153 }
154
155
156 /*
157 * 2. RF register R/W API
158 * */
159 static u32
phy_RFSerialRead_8703B(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset)160 phy_RFSerialRead_8703B(
161 PADAPTER Adapter,
162 enum rf_path eRFPath,
163 u32 Offset
164 )
165 {
166 u32 retValue = 0;
167 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
168 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
169 u32 NewOffset;
170 u32 tmplong, tmplong2;
171 u8 RfPiEnable = 0;
172 u32 MaskforPhySet = 0;
173 int i = 0;
174
175 _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
176 /* */
177 /* Make sure RF register offset is correct */
178 /* */
179 Offset &= 0xff;
180
181 NewOffset = Offset;
182
183 if (eRFPath == RF_PATH_A) {
184 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
185 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
186 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
187 } else {
188 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
189 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
190 phy_set_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
191 }
192
193 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
194 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
195 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
196
197 rtw_udelay_os(10);
198
199 for (i = 0; i < 2; i++)
200 rtw_udelay_os(MAX_STALL_TIME);
201 rtw_udelay_os(10);
202
203 if (eRFPath == RF_PATH_A)
204 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
205 else if (eRFPath == RF_PATH_B)
206 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
207
208 if (RfPiEnable) {
209 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
210 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
211
212 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
213 } else {
214 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
215 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
216
217 /* RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
218 }
219 _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
220 return retValue;
221
222 }
223
224 /**
225 * Function: phy_RFSerialWrite_8703B
226 *
227 * OverView: Write data to RF register (page 8~)
228 *
229 * Input:
230 * PADAPTER Adapter,
231 enum rf_path eRFPath, //Radio path of A/B/C/D
232 * u32 Offset, //The target address to be read
233 * u32 Data //The new register Data in the target bit position
234 * //of the target to be read
235 *
236 * Output: None
237 * Return: None
238 * Note: Threre are three types of serial operations:
239 * 1. Software serial write
240 * 2. Hardware LSSI-Low Speed Serial Interface
241 * 3. Hardware HSSI-High speed
242 * serial write. Driver need to implement (1) and (2).
243 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
244 *
245 * Note: For RF8256 only
246 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
247 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
248 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
249 * programming guide" for more details.
250 * Thus, we define a sub-finction for RTL8526 register address conversion
251 * ===========================================================
252 * Register Mode RegCTL[1] RegCTL[0] Note
253 * (Reg00[12]) (Reg00[10])
254 * ===========================================================
255 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
256 * ------------------------------------------------------------------
257 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
258 * ------------------------------------------------------------------
259 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
260 * ------------------------------------------------------------------
261 *
262 * 2008/09/02 MH Add 92S RF definition
263 *
264 *
265 *
266 */
267 static void
phy_RFSerialWrite_8703B(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset,u32 Data)268 phy_RFSerialWrite_8703B(
269 PADAPTER Adapter,
270 enum rf_path eRFPath,
271 u32 Offset,
272 u32 Data
273 )
274 {
275 u32 DataAndAddr = 0;
276 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
277 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
278 u32 NewOffset;
279
280 Offset &= 0xff;
281
282 /* */
283 /* Shadow Update */
284 /* */
285 /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
286
287 /* */
288 /* Switch page for 8256 RF IC */
289 /* */
290 NewOffset = Offset;
291
292 /* */
293 /* Put write addr in [5:0] and write data in [31:16] */
294 /* */
295 /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
296 DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
297
298 /* */
299 /* Write Operation */
300 /* */
301 phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
302 /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
303
304 }
305
306
307 /**
308 * Function: PHY_QueryRFReg
309 *
310 * OverView: Query "Specific bits" to RF register (page 8~)
311 *
312 * Input:
313 * PADAPTER Adapter,
314 enum rf_path eRFPath, //Radio path of A/B/C/D
315 * u32 RegAddr, //The target address to be read
316 * u32 BitMask //The target bit position in the target address
317 * //to be read
318 *
319 * Output: None
320 * Return: u32 Readback value
321 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
322 */
323 u32
PHY_QueryRFReg_8703B(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)324 PHY_QueryRFReg_8703B(
325 PADAPTER Adapter,
326 enum rf_path eRFPath,
327 u32 RegAddr,
328 u32 BitMask
329 )
330 {
331 u32 Original_Value, Readback_Value, BitShift;
332
333 if (eRFPath >= MAX_RF_PATH)
334 return 0;
335
336 #if (DISABLE_BB_RF == 1)
337 return 0;
338 #endif
339
340 Original_Value = phy_RFSerialRead_8703B(Adapter, eRFPath, RegAddr);
341
342 BitShift = phy_CalculateBitShift(BitMask);
343 Readback_Value = (Original_Value & BitMask) >> BitShift;
344
345 return Readback_Value;
346 }
347
348 /**
349 * Function: PHY_SetRFReg
350 *
351 * OverView: Write "Specific bits" to RF register (page 8~)
352 *
353 * Input:
354 * PADAPTER Adapter,
355 enum rf_path eRFPath, //Radio path of A/B/C/D
356 * u32 RegAddr, //The target address to be modified
357 * u32 BitMask //The target bit position in the target address
358 * //to be modified
359 * u32 Data //The new register Data in the target bit position
360 * //of the target address
361 *
362 * Output: None
363 * Return: None
364 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
365 */
366 void
PHY_SetRFReg_8703B(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)367 PHY_SetRFReg_8703B(
368 PADAPTER Adapter,
369 enum rf_path eRFPath,
370 u32 RegAddr,
371 u32 BitMask,
372 u32 Data
373 )
374 {
375 u32 Original_Value, BitShift;
376
377 if (eRFPath >= MAX_RF_PATH)
378 return;
379
380 #if (DISABLE_BB_RF == 1)
381 return;
382 #endif
383
384 /* RF data is 12 bits only */
385 if (BitMask != bRFRegOffsetMask) {
386 Original_Value = phy_RFSerialRead_8703B(Adapter, eRFPath, RegAddr);
387 BitShift = phy_CalculateBitShift(BitMask);
388 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
389 }
390
391 phy_RFSerialWrite_8703B(Adapter, eRFPath, RegAddr, Data);
392 }
393
394
395 /*
396 * 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
397 * */
398
399
400 /*-----------------------------------------------------------------------------
401 * Function: PHY_MACConfig8192C
402 *
403 * Overview: Condig MAC by header file or parameter file.
404 *
405 * Input: NONE
406 *
407 * Output: NONE
408 *
409 * Return: NONE
410 *
411 * Revised History:
412 * When Who Remark
413 * 08/12/2008 MHC Create Version 0.
414 *
415 *---------------------------------------------------------------------------*/
PHY_MACConfig8703B(PADAPTER Adapter)416 s32 PHY_MACConfig8703B(PADAPTER Adapter)
417 {
418 int rtStatus = _SUCCESS;
419 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
420
421 /* */
422 /* Config MAC */
423 /* */
424 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
425 rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
426 if (rtStatus == _FAIL)
427 #endif
428 {
429 #ifdef CONFIG_EMBEDDED_FWIMG
430 odm_config_mac_with_header_file(&pHalData->odmpriv);
431 rtStatus = _SUCCESS;
432 #endif/* CONFIG_EMBEDDED_FWIMG */
433 }
434
435 return rtStatus;
436 }
437
438 /**
439 * Function: phy_InitBBRFRegisterDefinition
440 *
441 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
442 *
443 * Input:
444 * PADAPTER Adapter,
445 *
446 * Output: None
447 * Return: None
448 * Note: The initialization value is constant and it should never be changes
449 */
450 static void
phy_InitBBRFRegisterDefinition(PADAPTER Adapter)451 phy_InitBBRFRegisterDefinition(
452 PADAPTER Adapter
453 )
454 {
455 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
456
457 /* RF Interface Sowrtware Control */
458 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
459 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
460
461 /* RF Interface Output (and Enable) */
462 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
463 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
464
465 /* RF Interface (Output and) Enable */
466 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
467 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
468
469 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
470 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
471
472 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
473 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */
474
475 /* Tranceiver Readback LSSI/HSPI mode */
476 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
477 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
478 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
479 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
480
481 }
482
483 static int
phy_BB8703b_Config_ParaFile(PADAPTER Adapter)484 phy_BB8703b_Config_ParaFile(
485 PADAPTER Adapter
486 )
487 {
488 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
489 int rtStatus = _SUCCESS;
490
491 /* */
492 /* 1. Read PHY_REG.TXT BB INIT!! */
493 /* */
494 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
495 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
496 #endif
497 {
498 #ifdef CONFIG_EMBEDDED_FWIMG
499 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
500 rtStatus = _FAIL;
501 #endif
502 }
503
504 if (rtStatus != _SUCCESS) {
505 RTW_INFO("%s():Write BB Reg Fail!!", __func__);
506 goto phy_BB8190_Config_ParaFile_Fail;
507 }
508
509 #if MP_DRIVER == 1
510 if (Adapter->registrypriv.mp_mode == 1) {
511 /* */
512 /* 1.1 Read PHY_REG_MP.TXT BB INIT!! */
513 /* */
514 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
515 if (phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP) == _FAIL)
516 #endif
517 {
518 #ifdef CONFIG_EMBEDDED_FWIMG
519 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))
520 rtStatus = _FAIL;
521 #endif
522 }
523
524 if (rtStatus != _SUCCESS) {
525 RTW_INFO("%s():Write BB Reg MP Fail!!", __func__);
526 goto phy_BB8190_Config_ParaFile_Fail;
527 }
528 }
529 #endif /* #if (MP_DRIVER == 1) */
530
531 /* */
532 /* 2. Read BB AGC table Initialization */
533 /* */
534 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
535 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
536 #endif
537 {
538 #ifdef CONFIG_EMBEDDED_FWIMG
539 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
540 rtStatus = _FAIL;
541 #endif
542 }
543
544 if (rtStatus != _SUCCESS) {
545 RTW_INFO("%s():AGC Table Fail\n", __func__);
546 goto phy_BB8190_Config_ParaFile_Fail;
547 }
548
549 phy_BB8190_Config_ParaFile_Fail:
550
551 return rtStatus;
552 }
553
554
555 int
PHY_BBConfig8703B(PADAPTER Adapter)556 PHY_BBConfig8703B(
557 PADAPTER Adapter
558 )
559 {
560 int rtStatus = _SUCCESS;
561 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
562 u16 RegVal;
563 u8 TmpU1B = 0;
564 u8 value8;
565
566 phy_InitBBRFRegisterDefinition(Adapter);
567
568 /* Enable BB and RF */
569 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
570
571 RegVal |= BIT13 | FEN_BB_GLB_RSTn | FEN_BBRSTB;
572 rtw_write16(Adapter, REG_SYS_FUNC_EN, RegVal);
573
574 rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
575
576 rtw_usleep_os(10);
577
578 phy_set_rf_reg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
579
580 #if 0
581 /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
582 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
583 rtw_write8(Adapter, REG_AFE_PLL_CTRL + 1, 0xdb);
584 #endif
585
586
587
588 rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
589
590 /* */
591 /* Config BB and AGC */
592 /* */
593 rtStatus = phy_BB8703b_Config_ParaFile(Adapter);
594
595 if (rtw_phydm_set_crystal_cap(Adapter, pHalData->crystal_cap) == _FALSE) {
596 RTW_ERR("Init crystal_cap failed\n");
597 rtw_warn_on(1);
598 rtStatus = _FAIL;
599 }
600
601 return rtStatus;
602 }
603
phy_LCK_8703B(PADAPTER Adapter)604 void phy_LCK_8703B(
605 PADAPTER Adapter
606 )
607 {
608 phy_set_rf_reg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);
609 phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);
610 rtw_mdelay_os(200);
611 phy_set_rf_reg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);
612 }
613
614 #if 0
615 /* Block & Path enable */
616 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
617 #define bOFDMEN_Jaguar 0x20000000
618 #define bCCKEN_Jaguar 0x10000000
619 #define rRxPath_Jaguar 0x808 /* Rx antenna */
620 #define bRxPath_Jaguar 0xff
621 #define rTxPath_Jaguar 0x80c /* Tx antenna */
622 #define bTxPath_Jaguar 0x0fffffff
623 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
624 #define bCCK_RX_Jaguar 0x0c000000
625 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
626 void
627 PHY_BB8703B_Config_1T(
628 PADAPTER Adapter
629 )
630 {
631 /* BB OFDM RX Path_A */
632 phy_set_bb_reg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
633 /* BB OFDM TX Path_A */
634 phy_set_bb_reg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
635 /* BB CCK R/Rx Path_A */
636 phy_set_bb_reg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
637 /* MCS support */
638 phy_set_bb_reg(Adapter, 0x8bc, 0xc0000060, 0x4);
639 /* RF Path_B HSSI OFF */
640 phy_set_bb_reg(Adapter, 0xe00, 0xf, 0x4);
641 /* RF Path_B Power Down */
642 phy_set_bb_reg(Adapter, 0xe90, bMaskDWord, 0);
643 /* ADDA Path_B OFF */
644 phy_set_bb_reg(Adapter, 0xe60, bMaskDWord, 0);
645 phy_set_bb_reg(Adapter, 0xe64, bMaskDWord, 0);
646 }
647 #endif
648
649 int
PHY_RFConfig8703B(PADAPTER Adapter)650 PHY_RFConfig8703B(
651 PADAPTER Adapter
652 )
653 {
654 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
655 int rtStatus = _SUCCESS;
656
657 /* */
658 /* RF config */
659 /* */
660 rtStatus = PHY_RF6052_Config8703B(Adapter);
661
662 phy_LCK_8703B(Adapter);
663 /* PHY_BB8703B_Config_1T(Adapter); */
664
665 return rtStatus;
666 }
667
668 /*-----------------------------------------------------------------------------
669 * Function: PHY_ConfigRFWithParaFile()
670 *
671 * Overview: This function read RF parameters from general file format, and do RF 3-wire
672 *
673 * Input: PADAPTER Adapter
674 * ps1Byte pFileName
675 * enum rf_path eRFPath
676 *
677 * Output: NONE
678 *
679 * Return: RT_STATUS_SUCCESS: configuration file exist
680 *
681 * Note: Delay may be required for RF configuration
682 *---------------------------------------------------------------------------*/
683 int
PHY_ConfigRFWithParaFile_8703B(PADAPTER Adapter,u8 * pFileName,enum rf_path eRFPath)684 PHY_ConfigRFWithParaFile_8703B(
685 PADAPTER Adapter,
686 u8 *pFileName,
687 enum rf_path eRFPath
688 )
689 {
690 return _SUCCESS;
691 }
692
693 /**************************************************************************************************************
694 * Description:
695 * The low-level interface to set TxAGC , called by both MP and Normal Driver.
696 *
697 * <20120830, Kordan>
698 **************************************************************************************************************/
699
700 void
PHY_SetTxPowerIndex_8703B(PADAPTER Adapter,u32 PowerIndex,enum rf_path RFPath,u8 Rate)701 PHY_SetTxPowerIndex_8703B(
702 PADAPTER Adapter,
703 u32 PowerIndex,
704 enum rf_path RFPath,
705 u8 Rate
706 )
707 {
708 if (RFPath == RF_PATH_A || RFPath == RF_PATH_B) {
709 switch (Rate) {
710 case MGN_1M:
711 phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
712 break;
713 case MGN_2M:
714 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
715 break;
716 case MGN_5_5M:
717 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
718 break;
719 case MGN_11M:
720 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
721 break;
722
723 case MGN_6M:
724 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
725 break;
726 case MGN_9M:
727 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
728 break;
729 case MGN_12M:
730 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
731 break;
732 case MGN_18M:
733 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
734 break;
735
736 case MGN_24M:
737 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
738 break;
739 case MGN_36M:
740 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
741 break;
742 case MGN_48M:
743 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
744 break;
745 case MGN_54M:
746 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
747 break;
748
749 case MGN_MCS0:
750 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
751 break;
752 case MGN_MCS1:
753 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
754 break;
755 case MGN_MCS2:
756 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
757 break;
758 case MGN_MCS3:
759 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
760 break;
761
762 case MGN_MCS4:
763 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
764 break;
765 case MGN_MCS5:
766 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
767 break;
768 case MGN_MCS6:
769 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
770 break;
771 case MGN_MCS7:
772 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
773 break;
774
775 default:
776 RTW_INFO("Invalid Rate!!\n");
777 break;
778 }
779 }
780 }
781
782 void
PHY_SetTxPowerLevel8703B(PADAPTER Adapter,u8 Channel)783 PHY_SetTxPowerLevel8703B(
784 PADAPTER Adapter,
785 u8 Channel
786 )
787 {
788 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
789 u8 cur_antenna;
790 enum rf_path RFPath = RF_PATH_A;
791
792 #ifdef CONFIG_ANTENNA_DIVERSITY
793 rtw_hal_get_odm_var(Adapter, HAL_ODM_ANTDIV_SELECT, &cur_antenna, NULL);
794
795 if (pHalData->AntDivCfg) /* antenna diversity Enable */
796 RFPath = ((cur_antenna == MAIN_ANT) ? RF_PATH_A : RF_PATH_B);
797 else /* antenna diversity disable */
798 #endif
799 RFPath = pHalData->ant_path;
800
801
802
803 phy_set_tx_power_level_by_path(Adapter, Channel, RFPath);
804
805 }
806
807 /* <20130321, VincentLan> A workaround to eliminate the 2440MHz & 2480MHz spur of 8703B. (Asked by Rock.) */
808 void
phy_SpurCalibration_8703B(PADAPTER pAdapter,u8 ToChannel,u8 threshold)809 phy_SpurCalibration_8703B(
810 PADAPTER pAdapter,
811 u8 ToChannel,
812 u8 threshold
813 )
814 {
815 u32 freq[6] = {0xFCCD, 0xFC4D, 0xFFCD, 0xFF4D, 0xFCCD, 0xFF9A}; /* {chnl 5, 6, 7, 8, 13, 14} */
816 u8 idx = 0;
817 u8 b_doNotch = FALSE;
818 u8 initial_gain;
819 BOOLEAN bHW_Ctrl = FALSE, bSW_Ctrl = FALSE, bHW_Ctrl_S1 = FALSE, bSW_Ctrl_S1 = FALSE;
820 u32 reg948;
821
822 /* add for notch */
823 u32 wlan_channel, CurrentChannel, Is40MHz;
824 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
825 /* PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); */
826 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
827 /* struct dm_struct *pDM_Odm = &pHalData->DM_OutSrc; */
828
829 /* check threshold */
830 if (threshold <= 0x0)
831 threshold = 0x16;
832
833 RTW_INFO("===>phy_SpurCalibration_8703B: Channel = %d\n", ToChannel);
834
835 if (ToChannel == 5)
836 idx = 0;
837 else if (ToChannel == 6)
838 idx = 1;
839 else if (ToChannel == 7)
840 idx = 2;
841 else if (ToChannel == 8)
842 idx = 3;
843 else if (ToChannel == 13)
844 idx = 4;
845 else if (ToChannel == 14)
846 idx = 5;
847 else
848 idx = 10;
849
850 reg948 = phy_query_bb_reg(pAdapter, rS0S1_PathSwitch, bMaskDWord);
851 if ((reg948 & BIT6) == 0x0)
852 bSW_Ctrl = TRUE;
853 else
854 bHW_Ctrl = TRUE;
855
856 if (bHW_Ctrl)
857 bHW_Ctrl_S1 = (phy_query_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1) ? TRUE : FALSE;
858 else if (bSW_Ctrl)
859 bSW_Ctrl_S1 = ((reg948 & BIT9) == 0x0) ? TRUE : FALSE;
860
861 /* If wlan at S1 (both HW control & SW control) and current channel=5,6,7,8,13,14 */
862 if ((bHW_Ctrl_S1 || bSW_Ctrl_S1) && (idx <= 5)) {
863 initial_gain = (u8)(odm_get_bb_reg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
864 odm_write_dig(pDM_Odm, 0x30);
865 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0); /* disable 3-wire */
866
867 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* Setup PSD */
868 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD */
869
870 rtw_msleep_os(30);
871
872 if (phy_query_bb_reg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
873 b_doNotch = TRUE;
874
875 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
876 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0); /* enable 3-wire */
877 odm_write_dig(pDM_Odm, initial_gain);
878 }
879
880 /* --- Notch Filter --- Asked by Rock */
881 if (b_doNotch) {
882 CurrentChannel = odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
883 wlan_channel = CurrentChannel & 0x0f; /* Get center frequency */
884
885 switch (wlan_channel) { /* Set notch filter */
886 case 5:
887 case 13:
888 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xB);
889 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /* enable notch filter */
890 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x06000000);
891 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
892 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
893 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
894 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /* enable CSI mask */
895 break;
896 case 6:
897 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x4);
898 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /* enable notch filter */
899 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000600);
900 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
901 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
902 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
903 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /* enable CSI mask */
904 break;
905 case 7:
906 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x3);
907 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /* enable notch filter */
908 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
909 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
910 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
911 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x06000000);
912 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /* enable CSI mask */
913 break;
914 case 8:
915 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xA);
916 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /* enable notch filter */
917 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
918 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
919 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
920 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000380);
921 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /* enable CSI mask */
922 break;
923 case 14:
924 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x5);
925 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /* enable notch filter */
926 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
927 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
928 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
929 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00180000);
930 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /* enable CSI mask */
931 break;
932 default:
933 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0); /* disable notch filter */
934 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0); /* disable CSI mask function */
935 break;
936 } /* switch(wlan_channel) */
937 return;
938 }
939
940 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0); /* disable notch filter */
941 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0); /* disable CSI mask */
942
943 }
944
945 void
phy_SetRegBW_8703B(PADAPTER Adapter,enum channel_width CurrentBW)946 phy_SetRegBW_8703B(
947 PADAPTER Adapter,
948 enum channel_width CurrentBW
949 )
950 {
951 u16 RegRfMod_BW, u2tmp = 0;
952 RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8703B);
953
954 switch (CurrentBW) {
955 case CHANNEL_WIDTH_20:
956 rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
957 break;
958
959 case CHANNEL_WIDTH_40:
960 u2tmp = RegRfMod_BW | BIT7;
961 rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
962 break;
963
964 case CHANNEL_WIDTH_80:
965 u2tmp = RegRfMod_BW | BIT8;
966 rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
967 break;
968
969 default:
970 RTW_INFO("phy_PostSetBWMode8703B(): unknown Bandwidth: %#X\n", CurrentBW);
971 break;
972 }
973 }
974
975 u8
phy_GetSecondaryChnl_8703B(PADAPTER Adapter)976 phy_GetSecondaryChnl_8703B(
977 PADAPTER Adapter
978 )
979 {
980 u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
981 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
982
983 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
984 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
985 SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
986 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
987 SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
988
989
990 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
991 SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
992 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
993 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
994 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
995 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
996 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
997 SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
998
999 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
1000
1001 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1002 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1003 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1004 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1005
1006 }
1007
1008 barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */
1009 return (SCSettingOf40 << 4) | SCSettingOf20;
1010 }
1011
1012 void
phy_PostSetBwMode8703B(PADAPTER Adapter)1013 phy_PostSetBwMode8703B(
1014 PADAPTER Adapter
1015 )
1016 {
1017 u8 SubChnlNum = 0;
1018 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1019 u8 u1TmpVal = 0;
1020
1021 /* 3 Set Reg668 Reg440 BW */
1022 phy_SetRegBW_8703B(Adapter, pHalData->current_channel_bw);
1023
1024 /* 3 Set Reg483 */
1025 SubChnlNum = phy_GetSecondaryChnl_8703B(Adapter);
1026 rtw_write8(Adapter, REG_DATA_SC_8703B, SubChnlNum);
1027
1028 /* 3 */
1029 /* 3 */ /* <2>Set PHY related register */
1030 /* 3 */
1031 switch (pHalData->current_channel_bw) {
1032 /* 20 MHz channel*/
1033 case CHANNEL_WIDTH_20:
1034 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
1035
1036 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
1037
1038 /* phy_set_bb_reg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
1039
1040 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31 | BIT30), 0x0);
1041
1042 /* 8703B new Add */
1043 phy_set_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord, pHalData->RegForRecover[2].value);
1044 phy_set_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord, pHalData->RegForRecover[3].value);
1045 phy_set_rf_reg(Adapter, RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask, pHalData->RegForRecover[4].value);
1046
1047 break;
1048
1049
1050 /* 40 MHz channel*/
1051 case CHANNEL_WIDTH_40:
1052 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
1053
1054 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
1055
1056 /* 8703B new Add*/
1057 phy_set_bb_reg(Adapter, rBBrx_DFIR, bMaskDWord, 0x40100000);
1058 phy_set_bb_reg(Adapter, rOFDM0_XATxAFE, bMaskDWord, 0x51F60000);
1059 phy_set_rf_reg(Adapter, RF_PATH_A, 0x1E, bRFRegOffsetMask, 0x00C4C);
1060
1061 /* Set Control channel to upper or lower. These settings are required only for 40MHz*/
1062 phy_set_bb_reg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
1063
1064 phy_set_bb_reg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
1065
1066 phy_set_bb_reg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1067
1068 u1TmpVal = rtw_read8(Adapter, REG_DATA_SC_8703B);
1069 u1TmpVal &= 0xF0;
1070 u1TmpVal |= ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1071 rtw_write8(Adapter, REG_DATA_SC_8703B, u1TmpVal);
1072
1073 break;
1074
1075
1076
1077 default:
1078 break;
1079
1080 }
1081
1082 /* 3<3>Set RF related register */
1083 PHY_RF6052SetBandwidth8703B(Adapter, pHalData->current_channel_bw);
1084 }
1085
1086 void
phy_SwChnl8703B(PADAPTER pAdapter)1087 phy_SwChnl8703B(
1088 PADAPTER pAdapter
1089 )
1090 {
1091 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1092 u8 channelToSW = pHalData->current_channel;
1093 u8 i = 0;
1094
1095 if (pHalData->rf_chip == RF_PSEUDO_11N) {
1096 RTW_INFO("phy_SwChnl8703B: return for PSEUDO\n");
1097 return;
1098 }
1099
1100 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
1101 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
1102 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
1103
1104 /* BB Setting for some channels (requested by BB Neil) */
1105 switch (channelToSW) {
1106 case 14:
1107 /*Channel 14 in CCK, need to set 0xA26~0xA29 to 0 */
1108 phy_set_bb_reg(pAdapter, rCCK0_TxFilter2, bMaskHWord, 0);
1109 phy_set_bb_reg(pAdapter, rCCK0_DebugPort, bMaskLWord, 0);
1110 break;
1111 default:
1112 /*Normal setting for 8703B, just recover to the default setting. */
1113 /*This hardcore values refer to the parameter which BB team gave. */
1114 for (i = 0 ; i < 2 ; ++i)
1115 phy_set_bb_reg(pAdapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
1116 }
1117
1118 phy_SpurCalibration_8703B(pAdapter, channelToSW, 0x16);
1119
1120 RTW_INFO("===>phy_SwChnl8703B: Channel = %d\n", channelToSW);
1121 }
1122
1123 void
phy_SwChnlAndSetBwMode8703B(PADAPTER Adapter)1124 phy_SwChnlAndSetBwMode8703B(
1125 PADAPTER Adapter
1126 )
1127 {
1128 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1129
1130 if (Adapter->bNotifyChannelChange) {
1131 RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
1132 __FUNCTION__,
1133 pHalData->bSwChnl,
1134 pHalData->current_channel,
1135 pHalData->bSetChnlBW,
1136 pHalData->current_channel_bw);
1137 }
1138
1139 if (RTW_CANNOT_RUN(Adapter))
1140 return;
1141
1142 if (pHalData->bSwChnl) {
1143 phy_SwChnl8703B(Adapter);
1144 pHalData->bSwChnl = _FALSE;
1145 }
1146
1147 if (pHalData->bSetChnlBW) {
1148 phy_PostSetBwMode8703B(Adapter);
1149 pHalData->bSetChnlBW = _FALSE;
1150 }
1151
1152 if (pHalData->bNeedIQK == _TRUE) {
1153 if (pHalData->neediqk_24g == _TRUE) {
1154
1155 halrf_iqk_trigger(&pHalData->odmpriv, _FALSE);
1156 pHalData->bIQKInitialized = _TRUE;
1157 pHalData->neediqk_24g = _FALSE;
1158 }
1159 pHalData->bNeedIQK = _FALSE;
1160 }
1161
1162 rtw_hal_set_tx_power_level(Adapter, pHalData->current_channel);
1163 }
1164
1165 void
PHY_HandleSwChnlAndSetBW8703B(PADAPTER Adapter,BOOLEAN bSwitchChannel,BOOLEAN bSetBandWidth,u8 ChannelNum,enum channel_width ChnlWidth,EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,u8 CenterFrequencyIndex1)1166 PHY_HandleSwChnlAndSetBW8703B(
1167 PADAPTER Adapter,
1168 BOOLEAN bSwitchChannel,
1169 BOOLEAN bSetBandWidth,
1170 u8 ChannelNum,
1171 enum channel_width ChnlWidth,
1172 EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,
1173 EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,
1174 u8 CenterFrequencyIndex1
1175 )
1176 {
1177 /* static BOOLEAN bInitialzed = _FALSE; */
1178 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1179 u8 tmpChannel = pHalData->current_channel;
1180 enum channel_width tmpBW = pHalData->current_channel_bw;
1181 u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
1182 u8 tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
1183 u8 tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
1184 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1185
1186 /* RTW_INFO("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n",bSwitchChannel,bSetBandWidth); */
1187
1188 /* check is swchnl or setbw */
1189 if (!bSwitchChannel && !bSetBandWidth) {
1190 RTW_INFO("PHY_HandleSwChnlAndSetBW8812: not switch channel and not set bandwidth\n");
1191 return;
1192 }
1193
1194 /* skip change for channel or bandwidth is the same */
1195 if (bSwitchChannel) {
1196 /* if(pHalData->current_channel != ChannelNum) */
1197 {
1198 if (HAL_IsLegalChannel(Adapter, ChannelNum))
1199 pHalData->bSwChnl = _TRUE;
1200 }
1201 }
1202
1203 if (bSetBandWidth) {
1204 #if 0
1205 if (bInitialzed == _FALSE) {
1206 bInitialzed = _TRUE;
1207 pHalData->bSetChnlBW = _TRUE;
1208 } else if ((pHalData->current_channel_bw != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
1209 pHalData->bSetChnlBW = _TRUE;
1210 #else
1211 pHalData->bSetChnlBW = _TRUE;
1212 #endif
1213 }
1214
1215 if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
1216 /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1217 return;
1218 }
1219
1220
1221 if (pHalData->bSwChnl) {
1222 pHalData->current_channel = ChannelNum;
1223 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
1224 }
1225
1226
1227 if (pHalData->bSetChnlBW) {
1228 pHalData->current_channel_bw = ChnlWidth;
1229 #if 0
1230 if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_LOWER)
1231 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1232 else if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_UPPER)
1233 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1234 else
1235 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1236
1237 if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_LOWER)
1238 pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1239 else if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_UPPER)
1240 pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1241 else
1242 pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1243 #else
1244 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
1245 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
1246 #endif
1247
1248 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1249 }
1250
1251 /* Switch workitem or set timer to do switch channel or setbandwidth operation */
1252 if (!RTW_CANNOT_RUN(Adapter))
1253 phy_SwChnlAndSetBwMode8703B(Adapter);
1254 else {
1255 if (pHalData->bSwChnl) {
1256 pHalData->current_channel = tmpChannel;
1257 pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
1258 }
1259 if (pHalData->bSetChnlBW) {
1260 pHalData->current_channel_bw = tmpBW;
1261 pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1262 pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1263 pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1264 }
1265 }
1266
1267 /* RTW_INFO("Channel %d ChannelBW %d ",pHalData->current_channel, pHalData->current_channel_bw); */
1268 /* RTW_INFO("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); */
1269 /* RTW_INFO("CenterFrequencyIndex1 %d\n",pHalData->CurrentCenterFrequencyIndex1); */
1270
1271 /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1272
1273 }
1274
1275 void
PHY_SetSwChnlBWMode8703B(PADAPTER Adapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)1276 PHY_SetSwChnlBWMode8703B(
1277 PADAPTER Adapter,
1278 u8 channel,
1279 enum channel_width Bandwidth,
1280 u8 Offset40,
1281 u8 Offset80
1282 )
1283 {
1284 /* RTW_INFO("%s()===>\n",__FUNCTION__); */
1285
1286 PHY_HandleSwChnlAndSetBW8703B(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
1287
1288 /* RTW_INFO("<==%s()\n",__FUNCTION__); */
1289 }
1290