1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 #ifndef __PHYDMRAINFO_H__ 22 #define __PHYDMRAINFO_H__ 23 24 /*#define RAINFO_VERSION "2.0" //2014.11.04*/ 25 /*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/ 26 /*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/ 27 /*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/ 28 /*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ 29 /*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */ 30 #define RAINFO_VERSION "4.1" /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ 31 32 #define H2C_0X42_LENGTH 5 33 34 #define RA_FLOOR_UP_GAP 3 35 #define RA_FLOOR_TABLE_SIZE 7 36 37 #define ACTIVE_TP_THRESHOLD 150 38 #define RA_RETRY_DESCEND_NUM 2 39 #define RA_RETRY_LIMIT_LOW 4 40 #define RA_RETRY_LIMIT_HIGH 32 41 42 #define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL 43 #define RAINFO_STBC_STATE BIT1 44 //#define RAINFO_LDPC_STATE BIT2 45 #define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection 46 #define RAINFO_SHURTCUT_STATE BIT3 47 #define RAINFO_SHURTCUT_FLAG BIT4 48 #define RAINFO_INIT_RSSI_RATE_STATE BIT5 49 #define RAINFO_BF_STATE BIT6 50 #define RAINFO_BE_TX_STATE BIT7 // 1:TX 51 52 #define RA_MASK_CCK 0xf 53 #define RA_MASK_OFDM 0xff0 54 #define RA_MASK_HT1SS 0xff000 55 #define RA_MASK_HT2SS 0xff00000 56 /*#define RA_MASK_MCS3SS */ 57 #define RA_MASK_HT4SS 0xff0 58 #define RA_MASK_VHT1SS 0x3ff000 59 #define RA_MASK_VHT2SS 0xffc00000 60 61 #if(DM_ODM_SUPPORT_TYPE == ODM_AP) 62 #define RA_FIRST_MACID 1 63 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 64 #define RA_FIRST_MACID 0 65 #define WIN_DEFAULT_PORT_MACID 0 66 #define WIN_BT_PORT_MACID 2 67 #else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ 68 #define RA_FIRST_MACID 0 69 #endif 70 71 #define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit 72 73 #if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) 74 #define DM_RATR_STA_INIT 0 75 #define DM_RATR_STA_HIGH 1 76 #define DM_RATR_STA_MIDDLE 2 77 #define DM_RATR_STA_LOW 3 78 #define DM_RATR_STA_ULTRA_LOW 4 79 #endif 80 81 typedef enum _phydm_arfr_num { 82 ARFR_0_RATE_ID = 0x9, 83 ARFR_1_RATE_ID = 0xa, 84 ARFR_2_RATE_ID = 0xb, 85 ARFR_3_RATE_ID = 0xc, 86 ARFR_4_RATE_ID = 0xd, 87 ARFR_5_RATE_ID = 0xe 88 } PHYDM_RA_ARFR_NUM_E; 89 90 typedef enum _Phydm_ra_dbg_para { 91 RADBG_PCR_TH_OFFSET = 0, 92 RADBG_RTY_PENALTY = 1, 93 RADBG_N_HIGH = 2, 94 RADBG_N_LOW = 3, 95 RADBG_TRATE_UP_TABLE = 4, 96 RADBG_TRATE_DOWN_TABLE = 5, 97 RADBG_TRYING_NECESSARY = 6, 98 RADBG_TDROPING_NECESSARY = 7, 99 RADBG_RATE_UP_RTY_RATIO = 8, 100 RADBG_RATE_DOWN_RTY_RATIO = 9, //u8 101 102 RADBG_DEBUG_MONITOR1 = 0xc, 103 RADBG_DEBUG_MONITOR2 = 0xd, 104 RADBG_DEBUG_MONITOR3 = 0xe, 105 RADBG_DEBUG_MONITOR4 = 0xf, 106 RADBG_DEBUG_MONITOR5 = 0x10, 107 NUM_RA_PARA 108 } PHYDM_RA_DBG_PARA_E; 109 110 typedef enum PHYDM_WIRELESS_MODE { 111 112 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, 113 PHYDM_WIRELESS_MODE_A = 0x01, 114 PHYDM_WIRELESS_MODE_B = 0x02, 115 PHYDM_WIRELESS_MODE_G = 0x04, 116 PHYDM_WIRELESS_MODE_AUTO = 0x08, 117 PHYDM_WIRELESS_MODE_N_24G = 0x10, 118 PHYDM_WIRELESS_MODE_N_5G = 0x20, 119 PHYDM_WIRELESS_MODE_AC_5G = 0x40, 120 PHYDM_WIRELESS_MODE_AC_24G = 0x80, 121 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, 122 PHYDM_WIRELESS_MODE_MAX = 0x800, 123 PHYDM_WIRELESS_MODE_ALL = 0xFFFF 124 } PHYDM_WIRELESS_MODE_E; 125 126 typedef enum PHYDM_RATEID_IDX_ { 127 128 PHYDM_BGN_40M_2SS = 0, 129 PHYDM_BGN_40M_1SS = 1, 130 PHYDM_BGN_20M_2SS = 2, 131 PHYDM_BGN_20M_1SS = 3, 132 PHYDM_GN_N2SS = 4, 133 PHYDM_GN_N1SS = 5, 134 PHYDM_BG = 6, 135 PHYDM_G = 7, 136 PHYDM_B_20M = 8, 137 PHYDM_ARFR0_AC_2SS = 9, 138 PHYDM_ARFR1_AC_1SS = 10, 139 PHYDM_ARFR2_AC_2G_1SS = 11, 140 PHYDM_ARFR3_AC_2G_2SS = 12, 141 PHYDM_ARFR4_AC_3SS = 13, 142 PHYDM_ARFR5_N_3SS = 14 143 } PHYDM_RATEID_IDX_E; 144 145 typedef enum _PHYDM_RF_TYPE_DEFINITION { 146 PHYDM_RF_1T1R = 0, 147 PHYDM_RF_1T2R, 148 PHYDM_RF_2T2R, 149 PHYDM_RF_2T2R_GREEN, 150 PHYDM_RF_2T3R, 151 PHYDM_RF_2T4R, 152 PHYDM_RF_3T3R, 153 PHYDM_RF_3T4R, 154 PHYDM_RF_4T4R, 155 PHYDM_RF_MAX_TYPE 156 } PHYDM_RF_TYPE_DEF_E; 157 158 typedef enum _PHYDM_BW { 159 PHYDM_BW_20 = 0, 160 PHYDM_BW_40, 161 PHYDM_BW_80, 162 PHYDM_BW_80_80, 163 PHYDM_BW_160, 164 PHYDM_BW_10, 165 PHYDM_BW_5 166 } PHYDM_BW_E; 167 168 169 #if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA 170 typedef struct _ODM_RA_Info_ { 171 u1Byte RateID; 172 u4Byte RateMask; 173 u4Byte RAUseRate; 174 u1Byte RateSGI; 175 u1Byte RssiStaRA; 176 u1Byte PreRssiStaRA; 177 u1Byte SGIEnable; 178 u1Byte DecisionRate; 179 u1Byte PreRate; 180 u1Byte HighestRate; 181 u1Byte LowestRate; 182 u4Byte NscUp; 183 u4Byte NscDown; 184 u2Byte RTY[5]; 185 u4Byte TOTAL; 186 u2Byte DROP; 187 u1Byte Active; 188 u2Byte RptTime; 189 u1Byte RAWaitingCounter; 190 u1Byte RAPendingCounter; 191 u1Byte RADropAfterDown; 192 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! 193 u1Byte PTActive; // on or off 194 u1Byte PTTryState; // 0 trying state, 1 for decision state 195 u1Byte PTStage; // 0~6 196 u1Byte PTStopCount; //Stop PT counter 197 u1Byte PTPreRate; // if rate change do PT 198 u1Byte PTPreRssi; // if RSSI change 5% do PT 199 u1Byte PTModeSS; // decide whitch rate should do PT 200 u1Byte RAstage; // StageRA, decide how many times RA will be done between PT 201 u1Byte PTSmoothFactor; 202 #endif 203 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) 204 u1Byte RateDownCounter; 205 u1Byte RateUpCounter; 206 u1Byte RateDirection; 207 u1Byte BoundingType; 208 u1Byte BoundingCounter; 209 u1Byte BoundingLearningTime; 210 u1Byte RateDownStartTime; 211 #endif 212 } ODM_RA_INFO_T, *PODM_RA_INFO_T; 213 #endif 214 215 216 typedef struct _Rate_Adaptive_Table_ { 217 u1Byte firstconnect; 218 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN) 219 BOOLEAN PT_collision_pre; 220 #endif 221 222 #if (defined(CONFIG_RA_DBG_CMD)) 223 BOOLEAN is_ra_dbg_init; 224 225 u1Byte RTY_P[ODM_NUM_RATE_IDX]; 226 u1Byte RTY_P_default[ODM_NUM_RATE_IDX]; 227 BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX]; 228 229 u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; 230 u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; 231 BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; 232 233 u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; 234 u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; 235 BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; 236 237 BOOLEAN RA_Para_feedback_req; 238 239 u1Byte para_idx; 240 u1Byte rate_idx; 241 u1Byte value; 242 u2Byte value_16; 243 u1Byte rate_length; 244 #endif 245 u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; 246 u1Byte highest_client_tx_order; 247 u2Byte highest_client_tx_rate_order; 248 u1Byte power_tracking_flag; 249 u1Byte RA_threshold_offset; 250 u1Byte RA_offset_direction; 251 252 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) 253 u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; 254 u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; 255 u1Byte retry_descend_num; 256 u1Byte retrylimit_low; 257 u1Byte retrylimit_high; 258 #endif 259 260 261 } RA_T, *pRA_T; 262 263 typedef struct _ODM_RATE_ADAPTIVE { 264 u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver 265 u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH 266 u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW 267 u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW 268 269 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 270 u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC 271 BOOLEAN bLowerRtsRate; 272 #endif 273 274 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) 275 u1Byte RtsThres; 276 #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) 277 BOOLEAN bUseLdpc; 278 #else 279 u1Byte UltraLowRSSIThresh; 280 u4Byte LastRATR; // RATR Register Content 281 #endif 282 283 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; 284 285 #if (defined(CONFIG_RA_DBG_CMD)) 286 287 VOID 288 odm_RA_debug( 289 IN PVOID pDM_VOID, 290 IN u4Byte *const dm_value 291 ); 292 293 VOID 294 odm_RA_ParaAdjust_init( 295 IN PVOID pDM_VOID 296 ); 297 298 #else 299 300 VOID 301 phydm_RA_debug_PCR( 302 IN PVOID pDM_VOID, 303 IN u4Byte *const dm_value, 304 IN u4Byte *_used, 305 OUT char *output, 306 IN u4Byte *_out_len 307 ); 308 309 #endif 310 311 VOID 312 ODM_C2HRaParaReportHandler( 313 IN PVOID pDM_VOID, 314 IN pu1Byte CmdBuf, 315 IN u1Byte CmdLen 316 ); 317 318 VOID 319 odm_RA_ParaAdjust( 320 IN PVOID pDM_VOID 321 ); 322 323 VOID 324 phydm_ra_dynamic_retry_count( 325 IN PVOID pDM_VOID 326 ); 327 328 VOID 329 phydm_ra_dynamic_retry_limit( 330 IN PVOID pDM_VOID 331 ); 332 333 VOID 334 phydm_ra_dynamic_rate_id_on_assoc( 335 IN PVOID pDM_VOID, 336 IN u1Byte wireless_mode, 337 IN u1Byte init_rate_id 338 ); 339 340 VOID 341 phydm_print_rate( 342 IN PVOID pDM_VOID, 343 IN u1Byte rate, 344 IN u4Byte dbg_component 345 ); 346 347 VOID 348 phydm_c2h_ra_report_handler( 349 IN PVOID pDM_VOID, 350 IN pu1Byte CmdBuf, 351 IN u1Byte CmdLen 352 ); 353 354 u1Byte 355 phydm_rate_order_compute( 356 IN PVOID pDM_VOID, 357 IN u1Byte rate_idx 358 ); 359 360 VOID 361 phydm_ra_info_watchdog( 362 IN PVOID pDM_VOID 363 ); 364 365 VOID 366 phydm_ra_info_init( 367 IN PVOID pDM_VOID 368 ); 369 370 VOID 371 odm_RSSIMonitorInit( 372 IN PVOID pDM_VOID 373 ); 374 375 VOID 376 odm_RSSIMonitorCheck( 377 IN PVOID pDM_VOID 378 ); 379 380 VOID 381 phydm_initRaInfo( 382 IN PVOID pDM_VOID 383 ); 384 385 u1Byte 386 phydm_vht_en_mapping( 387 IN PVOID pDM_VOID, 388 IN u4Byte WirelessMode 389 ); 390 391 u1Byte 392 phydm_rate_id_mapping( 393 IN PVOID pDM_VOID, 394 IN u4Byte WirelessMode, 395 IN u1Byte RfType, 396 IN u1Byte bw 397 ); 398 399 VOID 400 phydm_UpdateHalRAMask( 401 IN PVOID pDM_VOID, 402 IN u4Byte wirelessMode, 403 IN u1Byte RfType, 404 IN u1Byte BW, 405 IN u1Byte MimoPs_enable, 406 IN u1Byte disable_cck_rate, 407 IN u4Byte *ratr_bitmap_msb_in, 408 IN u4Byte *ratr_bitmap_in, 409 IN u1Byte tx_rate_level 410 ); 411 412 VOID 413 odm_RateAdaptiveMaskInit( 414 IN PVOID pDM_VOID 415 ); 416 417 VOID 418 odm_RefreshRateAdaptiveMask( 419 IN PVOID pDM_VOID 420 ); 421 422 VOID 423 odm_RefreshRateAdaptiveMaskMP( 424 IN PVOID pDM_VOID 425 ); 426 427 VOID 428 odm_RefreshRateAdaptiveMaskCE( 429 IN PVOID pDM_VOID 430 ); 431 432 VOID 433 odm_RefreshRateAdaptiveMaskAPADSL( 434 IN PVOID pDM_VOID 435 ); 436 437 u1Byte 438 phydm_RA_level_decision( 439 IN PVOID pDM_VOID, 440 IN u4Byte rssi, 441 IN u1Byte Ratr_State 442 ); 443 444 BOOLEAN 445 ODM_RAStateCheck( 446 IN PVOID pDM_VOID, 447 IN s4Byte RSSI, 448 IN BOOLEAN bForceUpdate, 449 OUT pu1Byte pRATRState 450 ); 451 452 VOID 453 odm_RefreshBasicRateMask( 454 IN PVOID pDM_VOID 455 ); 456 VOID 457 ODM_RAPostActionOnAssoc( 458 IN PVOID pDM_Odm 459 ); 460 461 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 462 463 u1Byte 464 odm_Find_RTS_Rate( 465 IN PVOID pDM_VOID, 466 IN u1Byte Tx_Rate, 467 IN BOOLEAN bErpProtect 468 ); 469 470 VOID 471 ODM_UpdateNoisyState( 472 IN PVOID pDM_VOID, 473 IN BOOLEAN bNoisyStateFromC2H 474 ); 475 476 VOID 477 phydm_update_pwr_track( 478 IN PVOID pDM_VOID, 479 IN u1Byte Rate 480 ); 481 482 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 483 484 s4Byte 485 phydm_FindMinimumRSSI( 486 IN PDM_ODM_T pDM_Odm, 487 IN PADAPTER pAdapter, 488 IN OUT BOOLEAN *pbLink_temp 489 ); 490 491 VOID 492 ODM_UpdateInitRateWorkItemCallback( 493 IN PVOID pContext 494 ); 495 496 VOID 497 odm_RSSIDumpToRegister( 498 IN PVOID pDM_VOID 499 ); 500 501 VOID 502 odm_RefreshLdpcRtsMP( 503 IN PADAPTER pAdapter, 504 IN PDM_ODM_T pDM_Odm, 505 IN u1Byte mMacId, 506 IN u1Byte IOTPeer, 507 IN s4Byte UndecoratedSmoothedPWDB 508 ); 509 510 #if 0 511 VOID 512 ODM_DynamicARFBSelect( 513 IN PVOID pDM_VOID, 514 IN u1Byte rate, 515 IN BOOLEAN Collision_State 516 ); 517 #endif 518 519 VOID 520 ODM_RateAdaptiveStateApInit( 521 IN PVOID PADAPTER_VOID, 522 IN PRT_WLAN_STA pEntry 523 ); 524 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 525 526 static void 527 FindMinimumRSSI( 528 IN PADAPTER pAdapter 529 ); 530 531 u8Byte 532 PhyDM_Get_Rate_Bitmap_Ex( 533 IN PVOID pDM_VOID, 534 IN u4Byte macid, 535 IN u8Byte ra_mask, 536 IN u1Byte rssi_level, 537 OUT u8Byte *dm_RA_Mask, 538 OUT u1Byte *dm_RteID 539 ); 540 u4Byte 541 ODM_Get_Rate_Bitmap( 542 IN PVOID pDM_VOID, 543 IN u4Byte macid, 544 IN u4Byte ra_mask, 545 IN u1Byte rssi_level 546 ); 547 548 void phydm_ra_rssi_rpt_wk(PVOID pContext); 549 #endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ 550 551 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 552 553 VOID 554 phydm_gen_ramask_h2c_AP( 555 IN PVOID pDM_VOID, 556 IN struct rtl8192cd_priv *priv, 557 IN PSTA_INFO_T *pEntry, 558 IN u1Byte rssi_level 559 ); 560 561 #endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ 562 563 #endif /*#ifndef __ODMRAINFO_H__*/ 564 565 566