1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __HALDMOUTSRC_H__ 27 #define __HALDMOUTSRC_H__ 28 29 /*@============================================================*/ 30 /*@include files*/ 31 /*@============================================================*/ 32 /*PHYDM header*/ 33 #include "phydm_pre_define.h" 34 #include "phydm_features.h" 35 #include "phydm_dig.h" 36 #ifdef CONFIG_PATH_DIVERSITY 37 #include "phydm_pathdiv.h" 38 #endif 39 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 40 #include "phydm_antdiv.h" 41 #endif 42 43 #include "phydm_soml.h" 44 45 #ifdef CONFIG_SMART_ANTENNA 46 #include "phydm_smt_ant.h" 47 #endif 48 #ifdef CONFIG_ANT_DETECTION 49 #include "phydm_antdect.h" 50 #endif 51 #include "phydm_rainfo.h" 52 #ifdef CONFIG_DYNAMIC_TX_TWR 53 #include "phydm_dynamictxpower.h" 54 #endif 55 #include "phydm_cfotracking.h" 56 #include "phydm_adaptivity.h" 57 #include "phydm_dfs.h" 58 #include "phydm_ccx.h" 59 #include "txbf/phydm_hal_txbf_api.h" 60 #if (PHYDM_LA_MODE_SUPPORT) 61 #include "phydm_adc_sampling.h" 62 #endif 63 #ifdef CONFIG_PSD_TOOL 64 #include "phydm_psd.h" 65 #endif 66 #ifdef PHYDM_PRIMARY_CCA 67 #include "phydm_primary_cca.h" 68 #endif 69 #include "phydm_cck_pd.h" 70 #include "phydm_rssi_monitor.h" 71 #ifdef PHYDM_AUTO_DEGBUG 72 #include "phydm_auto_dbg.h" 73 #endif 74 #include "phydm_math_lib.h" 75 #include "phydm_noisemonitor.h" 76 #include "phydm_api.h" 77 #ifdef PHYDM_POWER_TRAINING_SUPPORT 78 #include "phydm_pow_train.h" 79 #endif 80 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 81 #include "phydm_lna_sat.h" 82 #endif 83 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 84 #include "phydm_pmac_tx_setting.h" 85 #endif 86 #ifdef PHYDM_MP_SUPPORT 87 #include "phydm_mp.h" 88 #endif 89 90 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 91 #include "phydm_cck_rx_pathdiv.h" 92 #endif 93 94 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 95 #include "phydm_beamforming.h" 96 #endif 97 98 #ifdef CONFIG_DIRECTIONAL_BF 99 #include "phydm_direct_bf.h" 100 #endif 101 102 #include "phydm_regtable.h" 103 104 /*@HALRF header*/ 105 #include "halrf/halrf_iqk.h" 106 #include "halrf/halrf_dpk.h" 107 #include "halrf/halrf.h" 108 #include "halrf/halrf_powertracking.h" 109 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 110 #include "halrf/halphyrf_ap.h" 111 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) 112 #include "halrf/halphyrf_ce.h" 113 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 114 #include "halrf/halphyrf_win.h" 115 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 116 #include "halrf/halphyrf_iot.h" 117 #endif 118 119 extern const u16 phy_rate_table[84]; 120 121 /*@============================================================*/ 122 /*@Definition */ 123 /*@============================================================*/ 124 125 /* Traffic load decision */ 126 #define TRAFFIC_NO_TP 0 127 #define TRAFFIC_ULTRA_LOW 1 128 #define TRAFFIC_LOW 2 129 #define TRAFFIC_MID 3 130 #define TRAFFIC_HIGH 4 131 132 #define NONE 0 133 134 #if defined(DM_ODM_CE_MAC80211) 135 #define MAX_2(x, y) \ 136 __max2(typeof(x), typeof(y), \ 137 x, y) 138 #define __max2(t1, t2, x, y) ({ \ 139 t1 m80211_max1 = (x); \ 140 t2 m80211_max2 = (y); \ 141 m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) 142 143 #define MIN_2(x, y) \ 144 __min2(typeof(x), typeof(y), \ 145 x, y) 146 #define __min2(t1, t2, x, y) ({ \ 147 t1 m80211_min1 = (x); \ 148 t2 m80211_min2 = (y); \ 149 m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) 150 151 #define DIFF_2(x, y) \ 152 __diff2(typeof(x), typeof(y), \ 153 x, y) 154 #define __diff2(t1, t2, x, y) ({ \ 155 t1 __d1 = (x); \ 156 t2 __d2 = (y); \ 157 (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) 158 #else 159 #define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) 160 #define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) 161 #define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) 162 #endif 163 164 #define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) 165 #define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) 166 167 #if defined(DM_ODM_CE_MAC80211) 168 #define BYTE_DUPLICATE_2_DWORD(B0) ({ \ 169 u32 __b_dup = (B0);\ 170 (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ 171 }) 172 #else 173 #define BYTE_DUPLICATE_2_DWORD(B0) \ 174 (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) 175 #endif 176 #define BYTE_2_DWORD(B3, B2, B1, B0) \ 177 (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) 178 #define BIT_2_BYTE(B3, B2, B1, B0) \ 179 (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) 180 181 /*@For cmn sta info*/ 182 #if defined(DM_ODM_CE_MAC80211) 183 #define is_sta_active(sta) ({ \ 184 struct cmn_sta_info *__sta = (sta); \ 185 ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ 186 }) 187 188 #define IS_FUNC_EN(name) ({ \ 189 u8 *__is_func_name = (name); \ 190 (__is_func_name) && (*__is_func_name); \ 191 }) 192 #else 193 #define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) 194 195 #define IS_FUNC_EN(name) ((name) && (*name)) 196 #endif 197 198 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 199 #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ 200 #else 201 #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ 202 #endif 203 204 #define PHY_HIST_SIZE 12 205 #define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1) 206 207 #define S_TO_US 1000000 208 209 /*@============================================================*/ 210 /*structure and define*/ 211 /*@============================================================*/ 212 213 #define dm_type_by_fw 0 214 #define dm_type_by_driver 1 215 216 #define HW_IGI_TXINFO_TABLE_SIZE 64 217 218 #ifdef BB_RAM_SUPPORT 219 220 struct phydm_bb_ram_per_sta { 221 /* @Reg0x1E84 for RAM I/O*/ 222 boolean hw_igi_en; 223 boolean tx_pwr_offset0_en; 224 boolean tx_pwr_offset1_en; 225 /* @ macid from 0 to 63, above 63 => mapping to 63*/ 226 u8 macid_addr; 227 /* @hw_igi value for paths after packet Tx in a period of time*/ 228 u8 hw_igi; 229 /* @tx_pwr_offset0 offset for Tx power index*/ 230 s8 tx_pwr_offset0; 231 s8 tx_pwr_offset1; 232 233 }; 234 235 struct phydm_bb_ram_ctrl { 236 /*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/ 237 struct phydm_bb_ram_per_sta pram_sta_ctrl[HW_IGI_TXINFO_TABLE_SIZE]; 238 /*------------ For table2 do not set power offset by macid --------*/ 239 /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ 240 boolean tx_pwr_ofst_reg0_en; 241 u8 tx_pwr_ofst_reg0; 242 /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ 243 boolean tx_pwr_ofst_reg1_en; 244 u8 tx_pwr_ofst_reg1; 245 boolean hwigi_watchdog_en; 246 u64 macid_is_linked; 247 u64 hwigi_macid_is_linked; 248 }; 249 250 #endif 251 252 struct phydm_phystatus_statistic { 253 /*@[CCK]*/ 254 u32 rssi_cck_sum; 255 u32 rssi_cck_cnt; 256 u32 rssi_beacon_sum[RF_PATH_MEM_SIZE]; 257 u32 rssi_beacon_cnt; 258 #ifdef PHYSTS_3RD_TYPE_SUPPORT 259 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 260 u32 rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1]; 261 #endif 262 #endif 263 /*@[OFDM]*/ 264 u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE]; 265 u32 rssi_ofdm_cnt; 266 u32 evm_ofdm_sum; 267 u32 snr_ofdm_sum[RF_PATH_MEM_SIZE]; 268 u16 evm_ofdm_hist[PHY_HIST_SIZE]; 269 u16 snr_ofdm_hist[PHY_HIST_SIZE]; 270 /*@[1SS]*/ 271 u32 rssi_1ss_cnt; 272 u32 rssi_1ss_sum[RF_PATH_MEM_SIZE]; 273 u32 evm_1ss_sum; 274 u32 snr_1ss_sum[RF_PATH_MEM_SIZE]; 275 u16 evm_1ss_hist[PHY_HIST_SIZE]; 276 u16 snr_1ss_hist[PHY_HIST_SIZE]; 277 /*@[2SS]*/ 278 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 279 u32 rssi_2ss_cnt; 280 u32 rssi_2ss_sum[RF_PATH_MEM_SIZE]; 281 u32 evm_2ss_sum[2]; 282 u32 snr_2ss_sum[RF_PATH_MEM_SIZE]; 283 u16 evm_2ss_hist[2][PHY_HIST_SIZE]; 284 u16 snr_2ss_hist[2][PHY_HIST_SIZE]; 285 #endif 286 /*@[3SS]*/ 287 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 288 u32 rssi_3ss_cnt; 289 u32 rssi_3ss_sum[RF_PATH_MEM_SIZE]; 290 u32 evm_3ss_sum[3]; 291 u32 snr_3ss_sum[RF_PATH_MEM_SIZE]; 292 u16 evm_3ss_hist[3][PHY_HIST_SIZE]; 293 u16 snr_3ss_hist[3][PHY_HIST_SIZE]; 294 #endif 295 /*@[4SS]*/ 296 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 297 u32 rssi_4ss_cnt; 298 u32 rssi_4ss_sum[RF_PATH_MEM_SIZE]; 299 u32 evm_4ss_sum[4]; 300 u32 snr_4ss_sum[RF_PATH_MEM_SIZE]; 301 u16 evm_4ss_hist[4][PHY_HIST_SIZE]; 302 u16 snr_4ss_hist[4][PHY_HIST_SIZE]; 303 #endif 304 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 305 u16 p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/ 306 u16 cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/ 307 u16 cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE]; 308 #endif 309 }; 310 311 struct phydm_phystatus_avg { 312 /*@[CCK]*/ 313 u8 rssi_cck_avg; 314 u8 rssi_beacon_avg[RF_PATH_MEM_SIZE]; 315 #ifdef PHYSTS_3RD_TYPE_SUPPORT 316 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 317 u8 rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1]; 318 #endif 319 #endif 320 /*@[OFDM]*/ 321 u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE]; 322 u8 evm_ofdm_avg; 323 u8 snr_ofdm_avg[RF_PATH_MEM_SIZE]; 324 /*@[1SS]*/ 325 u8 rssi_1ss_avg[RF_PATH_MEM_SIZE]; 326 u8 evm_1ss_avg; 327 u8 snr_1ss_avg[RF_PATH_MEM_SIZE]; 328 /*@[2SS]*/ 329 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 330 u8 rssi_2ss_avg[RF_PATH_MEM_SIZE]; 331 u8 evm_2ss_avg[2]; 332 u8 snr_2ss_avg[RF_PATH_MEM_SIZE]; 333 #endif 334 /*@[3SS]*/ 335 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 336 u8 rssi_3ss_avg[RF_PATH_MEM_SIZE]; 337 u8 evm_3ss_avg[3]; 338 u8 snr_3ss_avg[RF_PATH_MEM_SIZE]; 339 #endif 340 /*@[4SS]*/ 341 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 342 u8 rssi_4ss_avg[RF_PATH_MEM_SIZE]; 343 u8 evm_4ss_avg[4]; 344 u8 snr_4ss_avg[RF_PATH_MEM_SIZE]; 345 #endif 346 }; 347 348 struct odm_phy_dbg_info { 349 /*@ODM Write,debug info*/ 350 u32 num_qry_phy_status_cck; 351 u32 num_qry_phy_status_ofdm; 352 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) 353 u32 num_qry_mu_pkt; 354 u32 num_qry_bf_pkt; 355 u16 num_mu_vht_pkt[VHT_RATE_NUM]; 356 boolean is_ldpc_pkt; 357 boolean is_stbc_pkt; 358 u8 num_of_ppdu[4]; 359 u8 gid_num[4]; 360 #endif 361 u32 condi_num; /*@condition number U(18,4)*/ 362 u8 condi_num_cdf[CN_CNT_MAX]; 363 u8 num_qry_beacon_pkt; 364 u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ 365 u8 beacon_phy_rate; 366 u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ 367 u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ 368 u16 show_phy_sts_cnt; 369 u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; 370 u16 num_qry_ht_pkt[HT_RATE_NUM]; 371 u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ 372 boolean ht_pkt_not_zero; 373 boolean low_bw_20_occur; 374 #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT) 375 u16 num_qry_vht_pkt[VHT_RATE_NUM]; 376 u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ 377 boolean vht_pkt_not_zero; 378 boolean low_bw_40_occur; 379 #endif 380 u16 snr_hist_th[PHY_HIST_TH_SIZE]; 381 u16 evm_hist_th[PHY_HIST_TH_SIZE]; 382 #ifdef PHYSTS_3RD_TYPE_SUPPORT 383 u16 cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/ 384 u8 condition_num_seg0; 385 u8 eigen_val[4]; 386 s16 cfo_tail[4]; /*per-path's cfo_tail */ 387 #endif 388 struct phydm_phystatus_statistic physts_statistic_info; 389 struct phydm_phystatus_avg phystatus_statistic_avg; 390 }; 391 392 enum odm_cmninfo { 393 /*@Fixed value*/ 394 /*@-----------HOOK BEFORE REG INIT-----------*/ 395 ODM_CMNINFO_PLATFORM = 0, 396 ODM_CMNINFO_ABILITY, 397 ODM_CMNINFO_INTERFACE, 398 ODM_CMNINFO_MP_TEST_CHIP, 399 ODM_CMNINFO_IC_TYPE, 400 ODM_CMNINFO_CUT_VER, 401 ODM_CMNINFO_FAB_VER, 402 ODM_CMNINFO_FW_VER, 403 ODM_CMNINFO_FW_SUB_VER, 404 ODM_CMNINFO_RF_TYPE, 405 ODM_CMNINFO_RFE_TYPE, 406 ODM_CMNINFO_DPK_EN, 407 ODM_CMNINFO_BOARD_TYPE, 408 ODM_CMNINFO_PACKAGE_TYPE, 409 ODM_CMNINFO_EXT_LNA, 410 ODM_CMNINFO_5G_EXT_LNA, 411 ODM_CMNINFO_EXT_PA, 412 ODM_CMNINFO_5G_EXT_PA, 413 ODM_CMNINFO_GPA, 414 ODM_CMNINFO_APA, 415 ODM_CMNINFO_GLNA, 416 ODM_CMNINFO_ALNA, 417 ODM_CMNINFO_TDMA, 418 ODM_CMNINFO_EXT_TRSW, 419 ODM_CMNINFO_EXT_LNA_GAIN, 420 ODM_CMNINFO_PATCH_ID, 421 ODM_CMNINFO_BINHCT_TEST, 422 ODM_CMNINFO_BWIFI_TEST, 423 ODM_CMNINFO_SMART_CONCURRENT, 424 ODM_CMNINFO_CONFIG_BB_RF, 425 ODM_CMNINFO_IQKPAOFF, 426 ODM_CMNINFO_HUBUSBMODE, 427 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 428 ODM_CMNINFO_TX_TP, 429 ODM_CMNINFO_RX_TP, 430 ODM_CMNINFO_SOUNDING_SEQ, 431 ODM_CMNINFO_REGRFKFREEENABLE, 432 ODM_CMNINFO_RFKFREEENABLE, 433 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 434 ODM_CMNINFO_VALID_PATH_SET, 435 ODM_CMNINFO_EFUSE0X3D8, 436 ODM_CMNINFO_EFUSE0X3D7, 437 ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, 438 ODM_CMNINFO_X_CAP_SETTING, 439 ODM_CMNINFO_ADVANCE_OTA, 440 ODM_CMNINFO_HP_HWID, 441 ODM_CMNINFO_HUAWEI_HWID, 442 ODM_CMNINFO_ATHEROS_HWID, 443 ODM_CMNINFO_TSSI_ENABLE, /*also for cmn_info_update*/ 444 ODM_CMNINFO_DIS_DPD, 445 ODM_CMNINFO_POWER_VOLTAGE, 446 ODM_CMNINFO_ANTDIV_GPIO, 447 ODM_CMNINFO_EN_AUTO_BW_TH, 448 ODM_CMNINFO_PEAK_DETECT_MODE, 449 ODM_CMNINFO_EN_NBI_DETECT, 450 /*@-----------HOOK BEFORE REG INIT-----------*/ 451 452 /*@Dynamic value:*/ 453 454 /*@--------- POINTER REFERENCE-----------*/ 455 ODM_CMNINFO_TX_UNI, 456 ODM_CMNINFO_RX_UNI, 457 ODM_CMNINFO_BAND, 458 ODM_CMNINFO_SEC_CHNL_OFFSET, 459 ODM_CMNINFO_SEC_MODE, 460 ODM_CMNINFO_BW, 461 ODM_CMNINFO_CHNL, 462 ODM_CMNINFO_FORCED_RATE, 463 ODM_CMNINFO_ANT_DIV, 464 ODM_CMNINFO_PATH_DIV, 465 ODM_CMNINFO_ADAPTIVE_SOML, 466 ODM_CMNINFO_ADAPTIVITY, 467 ODM_CMNINFO_SCAN, 468 ODM_CMNINFO_POWER_SAVING, 469 ODM_CMNINFO_ONE_PATH_CCA, 470 ODM_CMNINFO_DRV_STOP, 471 ODM_CMNINFO_PNP_IN, 472 ODM_CMNINFO_INIT_ON, 473 ODM_CMNINFO_ANT_TEST, 474 ODM_CMNINFO_NET_CLOSED, 475 ODM_CMNINFO_P2P_LINK, 476 ODM_CMNINFO_FCS_MODE, 477 ODM_CMNINFO_IS1ANTENNA, 478 ODM_CMNINFO_RFDEFAULTPATH, 479 ODM_CMNINFO_DFS_MASTER_ENABLE, 480 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 481 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, 482 ODM_CMNINFO_SOFT_AP_MODE, 483 ODM_CMNINFO_MP_MODE, 484 ODM_CMNINFO_INTERRUPT_MASK, 485 ODM_CMNINFO_BB_OPERATION_MODE, 486 ODM_CMNINFO_BF_ANTDIV_DECISION, 487 ODM_CMNINFO_MANUAL_SUPPORTABILITY, 488 ODM_CMNINFO_EN_DYM_BW_INDICATION, 489 ODM_ANTI_INTERFERENCE_EN, 490 /*@--------- POINTER REFERENCE-----------*/ 491 492 /*@------------CALL BY VALUE-------------*/ 493 ODM_CMNINFO_WIFI_DIRECT, 494 ODM_CMNINFO_WIFI_DISPLAY, 495 ODM_CMNINFO_LINK_IN_PROGRESS, 496 ODM_CMNINFO_LINK, 497 ODM_CMNINFO_CMW500LINK, 498 ODM_CMNINFO_STATION_STATE, 499 ODM_CMNINFO_RSSI_MIN, 500 ODM_CMNINFO_RSSI_MIN_BY_PATH, 501 ODM_CMNINFO_DBG_COMP, 502 ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ 503 ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ 504 ODM_CMNINFO_RF_ANTENNA_TYPE, 505 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 506 ODM_CMNINFO_BE_FIX_TX_ANT, 507 ODM_CMNINFO_BT_ENABLED, 508 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 509 ODM_CMNINFO_BT_HS_RSSI, 510 ODM_CMNINFO_BT_OPERATION, 511 ODM_CMNINFO_BT_LIMITED_DIG, 512 ODM_CMNINFO_AP_TOTAL_NUM, 513 ODM_CMNINFO_POWER_TRAINING, 514 ODM_CMNINFO_DFS_REGION_DOMAIN, 515 ODM_CMNINFO_BT_CONTINUOUS_TURN, 516 ODM_CMNINFO_IS_DOWNLOAD_FW, 517 ODM_CMNINFO_PHYDM_PATCH_ID, 518 ODM_CMNINFO_RRSR_VAL, 519 ODM_CMNINFO_LINKED_BF_SUPPORT, 520 ODM_CMNINFO_FLATNESS_TYPE, 521 /*@------------CALL BY VALUE-------------*/ 522 523 /*@Dynamic ptr array hook itms.*/ 524 ODM_CMNINFO_STA_STATUS, 525 ODM_CMNINFO_MAX, 526 527 }; 528 529 enum phydm_rfe_bb_source_sel { 530 PAPE_2G = 0, 531 PAPE_5G = 1, 532 LNA0N_2G = 2, 533 LNAON_5G = 3, 534 TRSW = 4, 535 TRSW_B = 5, 536 GNT_BT = 6, 537 ZERO = 7, 538 ANTSEL_0 = 8, 539 ANTSEL_1 = 9, 540 ANTSEL_2 = 0xa, 541 ANTSEL_3 = 0xb, 542 ANTSEL_4 = 0xc, 543 ANTSEL_5 = 0xd, 544 ANTSEL_6 = 0xe, 545 ANTSEL_7 = 0xf 546 }; 547 548 enum phydm_info_query { 549 PHYDM_INFO_FA_OFDM, 550 PHYDM_INFO_FA_CCK, 551 PHYDM_INFO_FA_TOTAL, 552 PHYDM_INFO_CCA_OFDM, 553 PHYDM_INFO_CCA_CCK, 554 PHYDM_INFO_CCA_ALL, 555 PHYDM_INFO_CRC32_OK_VHT, 556 PHYDM_INFO_CRC32_OK_HT, 557 PHYDM_INFO_CRC32_OK_LEGACY, 558 PHYDM_INFO_CRC32_OK_CCK, 559 PHYDM_INFO_CRC32_ERROR_VHT, 560 PHYDM_INFO_CRC32_ERROR_HT, 561 PHYDM_INFO_CRC32_ERROR_LEGACY, 562 PHYDM_INFO_CRC32_ERROR_CCK, 563 PHYDM_INFO_EDCCA_FLAG, 564 PHYDM_INFO_OFDM_ENABLE, 565 PHYDM_INFO_CCK_ENABLE, 566 PHYDM_INFO_CRC32_OK_HT_AGG, 567 PHYDM_INFO_CRC32_ERROR_HT_AGG, 568 PHYDM_INFO_DBG_PORT_0, 569 PHYDM_INFO_CURR_IGI, 570 PHYDM_INFO_RSSI_MIN, 571 PHYDM_INFO_RSSI_MAX, 572 PHYDM_INFO_CLM_RATIO, 573 PHYDM_INFO_NHM_RATIO, 574 PHYDM_INFO_NHM_NOISE_PWR, 575 PHYDM_INFO_NHM_PWR, 576 PHYDM_INFO_NHM_ENV_RATIO, 577 PHYDM_INFO_TXEN_CCK, 578 PHYDM_INFO_TXEN_OFDM, 579 PHYDM_INFO_NHM_IDLE_RATIO, 580 PHYDM_INFO_NHM_TX_RATIO, 581 }; 582 583 enum phydm_api { 584 PHYDM_API_NBI = 1, 585 PHYDM_API_CSI_MASK = 2, 586 }; 587 588 enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ 589 590 F00_DIG = 0, 591 F01_RA_MASK = 1, 592 F02_DYN_TXPWR = 2, 593 F03_FA_CNT = 3, 594 F04_RSSI_MNTR = 4, 595 F05_CCK_PD = 5, 596 F06_ANT_DIV = 6, 597 F07_SMT_ANT = 7, 598 F08_PWR_TRAIN = 8, 599 F09_RA = 9, 600 F10_PATH_DIV = 10, 601 F11_DFS = 11, 602 F12_DYN_ARFR = 12, 603 F13_ADPTVTY = 13, 604 F14_CFO_TRK = 14, 605 F15_ENV_MNTR = 15, 606 F16_PRI_CCA = 16, 607 F17_ADPTV_SOML = 17, 608 F18_LNA_SAT_CHK = 18, 609 }; 610 611 /*@=[PHYDM supportability]==========================================*/ 612 enum odm_ability { 613 ODM_BB_DIG = BIT(F00_DIG), 614 ODM_BB_RA_MASK = BIT(F01_RA_MASK), 615 ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), 616 ODM_BB_FA_CNT = BIT(F03_FA_CNT), 617 ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), 618 ODM_BB_CCK_PD = BIT(F05_CCK_PD), 619 ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), 620 ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), 621 ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), 622 ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), 623 ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), 624 ODM_BB_DFS = BIT(F11_DFS), 625 ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), 626 ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), 627 ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), 628 ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), 629 ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), 630 ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), 631 ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 632 }; 633 634 /*@=[PHYDM Debug Component]=====================================*/ 635 enum phydm_dbg_comp { 636 /*@BB Driver Functions*/ 637 DBG_DIG = BIT(F00_DIG), 638 DBG_RA_MASK = BIT(F01_RA_MASK), 639 DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), 640 DBG_FA_CNT = BIT(F03_FA_CNT), 641 DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), 642 DBG_CCKPD = BIT(F05_CCK_PD), 643 DBG_ANT_DIV = BIT(F06_ANT_DIV), 644 DBG_SMT_ANT = BIT(F07_SMT_ANT), 645 DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), 646 DBG_RA = BIT(F09_RA), 647 DBG_PATH_DIV = BIT(F10_PATH_DIV), 648 DBG_DFS = BIT(F11_DFS), 649 DBG_DYN_ARFR = BIT(F12_DYN_ARFR), 650 DBG_ADPTVTY = BIT(F13_ADPTVTY), 651 DBG_CFO_TRK = BIT(F14_CFO_TRK), 652 DBG_ENV_MNTR = BIT(F15_ENV_MNTR), 653 DBG_PRI_CCA = BIT(F16_PRI_CCA), 654 DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), 655 DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 656 /*Neet to re-arrange*/ 657 DBG_PHY_STATUS = BIT(20), 658 DBG_TMP = BIT(21), 659 DBG_FW_TRACE = BIT(22), 660 DBG_TXBF = BIT(23), 661 DBG_COMMON_FLOW = BIT(24), 662 DBG_COMP_MCC = BIT(25), 663 DBG_FW_DM = BIT(26), 664 DBG_DM_SUMMARY = BIT(27), 665 ODM_PHY_CONFIG = BIT(28), 666 ODM_COMP_INIT = BIT(29), 667 DBG_CMN = BIT(30),/*@common*/ 668 ODM_COMP_API = BIT(31) 669 }; 670 671 /*@=========================================================*/ 672 673 /*@ODM_CMNINFO_ONE_PATH_CCA*/ 674 enum odm_cca_path { 675 ODM_CCA_2R = 0, 676 ODM_CCA_1R_A = 1, 677 ODM_CCA_1R_B = 2, 678 }; 679 680 enum phy_reg_pg_type { 681 PHY_REG_PG_RELATIVE_VALUE = 0, 682 PHY_REG_PG_EXACT_VALUE = 1 683 }; 684 685 enum phydm_offload_ability { 686 PHYDM_PHY_PARAM_OFFLOAD = BIT(0), 687 PHYDM_RF_IQK_OFFLOAD = BIT(1), 688 PHYDM_RF_DPK_OFFLOAD = BIT(2), 689 }; 690 691 enum phydm_init_result { 692 PHYDM_INIT_SUCCESS = 0, 693 PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1 694 }; 695 696 struct phydm_pause_lv { 697 s8 lv_dig; 698 s8 lv_cckpd; 699 s8 lv_antdiv; 700 s8 lv_adapt; 701 s8 lv_adsl; 702 }; 703 704 struct phydm_func_poiner { 705 void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); 706 }; 707 708 struct pkt_process_info { 709 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 710 /*@send phystatus in each sampling time*/ 711 boolean physts_auto_swch_en; 712 u8 mac_ppdu_cnt; 713 u8 phy_ppdu_cnt; /*change with phy cca cnt*/ 714 u8 page_bitmap_target; 715 u8 page_bitmap_record; 716 u8 ppdu_phy_rate; 717 u8 ppdu_macid; 718 boolean is_1st_mpdu; 719 #endif 720 u8 lna_idx; 721 u8 vga_idx; 722 }; 723 724 #ifdef ODM_CONFIG_BT_COEXIST 725 struct phydm_bt_info { 726 boolean is_bt_enabled; /*@BT is enabled*/ 727 boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ 728 u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ 729 boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ 730 boolean is_bt_limited_dig; /*@BT is busy.*/ 731 }; 732 #endif 733 734 struct phydm_iot_center { 735 boolean is_linked_cmw500; 736 u8 win_patch_id; /*Customer ID*/ 737 boolean patch_id_100f0401; 738 boolean patch_id_10120200; 739 boolean patch_id_40010700; 740 boolean patch_id_021f0800; 741 boolean patch_id_011f0500; 742 u32 phydm_patch_id; /*temp for CCX IOT */ 743 }; 744 745 #if (RTL8822B_SUPPORT) 746 struct drp_rtl8822b_struct { 747 enum bb_path path_judge; 748 u16 path_a_cck_fa; 749 u16 path_b_cck_fa; 750 }; 751 #endif 752 753 #ifdef CONFIG_MCC_DM 754 #define MCC_DM_REG_NUM 32 755 struct _phydm_mcc_dm_ { 756 u8 mcc_pre_status; 757 u8 mcc_reg_id[MCC_DM_REG_NUM]; 758 u16 mcc_dm_reg[MCC_DM_REG_NUM]; 759 u8 mcc_dm_val[MCC_DM_REG_NUM][2]; 760 /*mcc DIG*/ 761 u8 mcc_rssi[2]; 762 /*u8 mcc_igi[2];*/ 763 764 /* need to be config by driver*/ 765 u8 mcc_status; 766 u8 sta_macid[2][NUM_STA]; 767 u16 mcc_rf_ch[2]; 768 769 }; 770 #endif 771 772 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 773 struct phydm_physts { 774 u8 cck_gi_u_bnd; 775 u8 cck_gi_l_bnd; 776 }; 777 #endif 778 779 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 780 #if (RT_PLATFORM != PLATFORM_LINUX) 781 typedef 782 #endif 783 784 struct dm_struct { 785 #else/*for AP, CE Team*/ 786 struct dm_struct { 787 #endif 788 /*@Add for different team use temporarily*/ 789 void *adapter; /*@For CE/NIC team*/ 790 struct rtl8192cd_priv *priv; /*@For AP team*/ 791 boolean odm_ready; 792 enum phy_reg_pg_type phy_reg_pg_value_type; 793 u8 phy_reg_pg_version; 794 u64 support_ability; /*@PHYDM function Supportability*/ 795 u64 pause_ability; /*@PHYDM function pause Supportability*/ 796 u64 debug_components; 797 u8 cmn_dbg_msg_period; 798 u8 cmn_dbg_msg_cnt; 799 u32 fw_debug_components; 800 u32 num_qry_phy_status_all; /*@CCK + OFDM*/ 801 u32 last_num_qry_phy_status_all; 802 u32 rx_pwdb_ave; 803 boolean is_init_hw_info_by_rfe; 804 boolean is_R2R_CCA_MASKT_TIME_SHORT; 805 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 806 u32 rts_drop_cnt; 807 u32 low_rate_tx_fail_cnt; 808 u32 low_rate_tx_ok_cnt; 809 #endif 810 811 //TSSI 812 u8 en_tssi_mode; 813 #if (RTL8723F_SUPPORT) 814 //ZWDFS for 80M 815 u8 en_zwdfs_bw80; 816 #endif 817 818 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 819 boolean is_cck_high_power; 820 u8 rf_path_rx_enable; 821 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 822 823 /* @COMMON INFORMATION */ 824 825 /*@Init value*/ 826 /*@-----------HOOK BEFORE REG INIT-----------*/ 827 828 u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ 829 u8 normal_rx_path; 830 u8 valid_path_set; /*@use for single rx path only*/ 831 boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ 832 u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ 833 u32 support_ic_type; /*@PHYDM supported IC*/ 834 enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/ 835 u8 ic_ip_series; /*N/AC/JGR3*/ 836 enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/ 837 u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ 838 u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ 839 u8 fw_version; 840 u8 fw_sub_version; 841 u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ 842 u8 rfe_type; 843 u8 board_type; 844 u8 package_type; 845 u16 type_glna; 846 u16 type_gpa; 847 u16 type_alna; 848 u16 type_apa; 849 u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ 850 u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ 851 u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ 852 u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ 853 u8 efuse0x3d7; /*@with Efuse number*/ 854 u8 efuse0x3d8; 855 u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ 856 u8 ext_lna_gain; /*@gain of external lna*/ 857 boolean is_in_hct_test; 858 u8 wifi_test; 859 boolean is_dual_mac_smart_concurrent; 860 u32 bk_support_ability; /*SD4 only*/ 861 u8 with_extenal_ant_switch; 862 /*@cck agc relative*/ 863 boolean cck_new_agc; 864 s8 cck_lna_gain_table[8]; 865 u8 cck_sat_cnt_th_init; 866 /*@-------------------------------------*/ 867 u32 phydm_sys_up_time; 868 u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ 869 u32 soft_ap_special_setting; 870 boolean boolean_dummy; 871 s8 s8_dummy; 872 u8 u8_dummy; 873 u16 u16_dummy; 874 u32 u32_dummy; 875 u8 rfe_hwsetting_band; 876 u8 p_advance_ota; 877 boolean hp_hw_id; 878 boolean BOOLEAN_temp; 879 boolean is_dfs_band; 880 u8 is_rx_blocking_en; 881 u16 fw_offload_ability; 882 boolean is_download_fw; 883 boolean en_dis_dpd; 884 u16 dis_dpd_rate; 885 u8 en_auto_bw_th; 886 boolean is_pause_dig; 887 boolean en_nbi_detect; 888 #if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT) 889 u8 txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX]; 890 u32 bp_0x9b0; 891 #elif (RTL8723F_SUPPORT) 892 u8 txagc_buff[2][PHY_NUM_RATE_IDX]; 893 u32 bp_0x9b0; 894 #endif 895 #if (RTL8822C_SUPPORT || RTL8723F_SUPPORT) 896 u8 ofdm_rxagc_l_bnd[16]; 897 boolean l_bnd_detect[16]; 898 u16 agc_rf_gain_ori[16][64];/*[table][mp_gain_idx]*/ 899 u16 agc_rf_gain[16][64];/*[table][mp_gain_idx]*/ 900 u8 agc_table_cnt; 901 boolean is_agc_tab_pos_shift; 902 u8 agc_table_shift; 903 #endif 904 /*@-----------HOOK BEFORE REG INIT-----------*/ 905 /*@===========================================================*/ 906 /*@====[ CALL BY Reference ]=========================================*/ 907 /*@===========================================================*/ 908 909 u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ 910 u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ 911 u8 *band_type; /*@2.4G/5G = 0/1*/ 912 u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ 913 u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ 914 u8 *band_width; /*@20M/40M/80M = 0/1/2*/ 915 u8 *channel; /*@central CH number*/ 916 boolean *is_scan_in_process; 917 boolean *is_power_saving; 918 boolean *is_tdma; 919 u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ 920 u8 *antenna_test; 921 boolean *is_net_closed; 922 boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/ 923 /*@--------- For 8723B IQK-------------------------------------*/ 924 boolean *is_1_antenna; 925 u8 *rf_default_path; /* @0:S1, 1:S0 */ 926 /*@-----------------------------------------------------------*/ 927 928 u16 *forced_data_rate; 929 u8 *enable_antdiv; 930 u8 *enable_pathdiv; 931 u8 *en_adap_soml; 932 u8 *edcca_mode; 933 u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ 934 boolean *is_fw_dw_rsvd_page_in_progress; 935 u32 *current_tx_tp; 936 u32 *current_rx_tp; 937 u8 *sounding_seq; 938 u32 *soft_ap_mode; 939 u8 *mp_mode; 940 u32 *interrupt_mask; 941 u8 *bb_op_mode; 942 u32 *manual_supportability; 943 u8 *dis_dym_bw_indication; 944 u8 *anti_interference_en; 945 /*@===========================================================*/ 946 /*@====[ CALL BY VALUE ]===========================================*/ 947 /*@===========================================================*/ 948 949 u8 disable_phydm_watchdog; 950 boolean is_link_in_process; 951 boolean is_wifi_direct; 952 boolean is_wifi_display; 953 boolean is_linked; 954 boolean pre_is_linked; 955 boolean first_connect; 956 boolean first_disconnect; 957 boolean bsta_state; 958 u8 rssi_min; 959 u8 rssi_min_macid; 960 u8 pre_rssi_min; 961 u8 rssi_max; 962 u8 rssi_max_macid; 963 u8 rssi_min_by_path; 964 boolean is_mp_chip; 965 boolean is_one_entry_only; 966 u32 one_entry_macid; 967 u32 one_entry_tp; 968 u32 pre_one_entry_tp; 969 u8 pre_number_linked_client; 970 u8 number_linked_client; 971 u8 pre_number_active_client; 972 u8 number_active_client; 973 boolean is_disable_phy_api; 974 u8 rssi_a; 975 u8 rssi_b; 976 u8 rssi_c; 977 u8 rssi_d; 978 s8 rxsc_80; 979 s8 rxsc_40; 980 s8 rxsc_20; 981 s8 rxsc_l; 982 u64 rssi_trsw; 983 u64 rssi_trsw_h; 984 u64 rssi_trsw_l; 985 u64 rssi_trsw_iso; 986 u8 tx_ant_status; /*TX path enable*/ 987 u8 rx_ant_status; /*RX path enable*/ 988 #ifdef PHYDM_COMPILE_ABOVE_4SS 989 enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/ 990 #endif 991 #ifdef PHYDM_COMPILE_ABOVE_3SS 992 enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/ 993 #endif 994 #ifdef PHYDM_COMPILE_ABOVE_2SS 995 enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/ 996 #endif 997 enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/ 998 u8 cck_lna_idx; 999 u8 cck_vga_idx; 1000 u8 curr_station_id; 1001 u8 ofdm_agc_idx[4]; 1002 u8 rx_rate; 1003 u8 rate_ss; 1004 u8 tx_rate; 1005 u8 linked_interval; 1006 u8 pre_channel; 1007 u32 txagc_offset_value_a; 1008 boolean is_txagc_offset_positive_a; 1009 u32 txagc_offset_value_b; 1010 boolean is_txagc_offset_positive_b; 1011 u8 ap_total_num; 1012 boolean flatness_type; 1013 /*@[traffic]*/ 1014 u8 traffic_load; 1015 u8 pre_traffic_load; 1016 u32 tx_tp; /*@Mbps*/ 1017 u32 rx_tp; /*@Mbps*/ 1018 u32 total_tp; /*@Mbps*/ 1019 u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ 1020 u64 cur_tx_ok_cnt; 1021 u64 cur_rx_ok_cnt; 1022 u64 last_tx_ok_cnt; 1023 u64 last_rx_ok_cnt; 1024 u16 consecutive_idlel_time; /*@unit: second*/ 1025 /*@---------------------------*/ 1026 boolean is_bb_swing_offset_positive_a; 1027 boolean is_bb_swing_offset_positive_b; 1028 1029 /*@[DIG]*/ 1030 boolean MPDIG_2G; /*off MPDIG*/ 1031 u8 times_2g; /*@for MP DIG*/ 1032 u8 force_igi; /*@for debug*/ 1033 boolean is_dig_low_bond; 1034 1035 /*@[TDMA-DIG]*/ 1036 u8 tdma_dig_timer_ms; 1037 u8 tdma_dig_state_number; 1038 u8 tdma_dig_low_upper_bond; 1039 u8 force_tdma_low_igi; 1040 u8 force_tdma_high_igi; 1041 u8 fix_expire_to_zero; 1042 boolean original_dig_restore; 1043 /*@---------------------------*/ 1044 1045 /*@[AntDiv]*/ 1046 u8 ant_div_type; 1047 u8 antdiv_rssi; 1048 u8 fat_comb_a; 1049 u8 fat_comb_b; 1050 u8 antdiv_intvl; 1051 u8 antdiv_delay; 1052 u8 ant_type; 1053 u8 ant_type2; 1054 u8 pre_ant_type; 1055 u8 pre_ant_type2; 1056 u8 antdiv_period; 1057 u8 evm_antdiv_period; 1058 u8 antdiv_select; 1059 u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ 1060 u8 stop_antdiv_rssi_th; 1061 u16 stop_antdiv_tp_diff_th; 1062 u16 stop_antdiv_tp_th; 1063 u8 antdiv_tp_period; 1064 u16 tp_active_th; 1065 u8 tp_active_occur; 1066 u8 path_select; 1067 u8 antdiv_evm_en; 1068 u8 bdc_holdstate; 1069 u8 antdiv_counter; 1070 /*@---------------------------*/ 1071 1072 u8 ndpa_period; 1073 boolean h2c_rarpt_connect; 1074 boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ 1075 u8 print_agc; 1076 u8 la_mode; 1077 /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ 1078 u8 current_rf_set_8821c; 1079 u8 default_rf_set_8821c; 1080 u8 current_ant_num_8821c; 1081 u8 default_ant_num_8821c; 1082 u8 rfe_type_expand; 1083 /*@-----------------------------------------------------------*/ 1084 /*@---For Adaptivtiy---------------------------------------------*/ 1085 s8 TH_L2H_default; 1086 s8 th_edcca_hl_diff_default; 1087 s8 th_l2h_ini; 1088 s8 th_edcca_hl_diff; 1089 boolean carrier_sense_enable; 1090 /*@-----------------------------------------------------------*/ 1091 u8 pre_dbg_priority; 1092 u8 nbi_set_result; 1093 u8 c2h_cmd_start; 1094 u8 fw_debug_trace[60]; 1095 u8 pre_c2h_seq; 1096 boolean fw_buff_is_enpty; 1097 u32 data_frame_num; 1098 /*@--- for spur detection ---------------------------------------*/ 1099 boolean en_reg_mntr_bb; 1100 boolean en_reg_mntr_rf; 1101 boolean en_reg_mntr_mac; 1102 boolean en_reg_mntr_byte; 1103 /*@--------------------------------------------------------------*/ 1104 #if (RTL8814B_SUPPORT || RTL8812F_SUPPORT || RTL8198F_SUPPORT) 1105 u8 dsde_sel; 1106 u8 nbi_path_sel; 1107 u8 csi_wgt; 1108 #endif 1109 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT) 1110 u8 csi_wgt_th_db[5]; /*@wgt 4,3,2,1,0 */ 1111 /* ^ ^ ^ ^ ^ */ 1112 #endif 1113 /*@------------------------------------------*/ 1114 1115 /*@--- for noise detection ---------------------------------------*/ 1116 boolean is_noisy_state; 1117 boolean noisy_decision; /*@b_noisy*/ 1118 boolean pre_b_noisy; 1119 u32 noisy_decision_smooth; 1120 /*@-----------------------------------------------------------*/ 1121 1122 /*@--- for MCC ant weighting ------------------------------------*/ 1123 boolean is_stop_dym_ant_weighting; 1124 /*@-----------------------------------------------------------*/ 1125 1126 boolean is_disable_dym_ecs; 1127 boolean is_disable_dym_ant_weighting; 1128 struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; 1129 u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ 1130 1131 #if (RATE_ADAPTIVE_SUPPORT) 1132 u16 currmin_rpt_time; 1133 struct _phydm_txstatistic_ hw_stats; 1134 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; 1135 /*Use mac_id as array index. STA mac_id=0*/ 1136 /*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ 1137 #endif 1138 /*@2012/02/14 MH Add to share 88E ra with other SW team*/ 1139 /*We need to colelct all support abilit to a proper area.*/ 1140 boolean ra_support88e; 1141 boolean *is_driver_stopped; 1142 boolean *is_driver_is_going_to_pnp_set_power_sleep; 1143 boolean *pinit_adpt_in_progress; 1144 boolean is_user_assign_level; 1145 u8 RSSI_BT; /*@come from BT*/ 1146 1147 /*@---PSD Relative ---------------------------------------------*/ 1148 boolean is_psd_in_process; 1149 boolean is_psd_active; 1150 /*@-----------------------------------------------------------*/ 1151 1152 boolean bsomlenabled; /* @D-SoML control */ 1153 u8 no_ndp_cnts; 1154 u16 ndp_cnt_pre; 1155 boolean is_beamformed; 1156 u8 linked_bf_support; 1157 boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ 1158 u32 n_iqk_cnt; 1159 u32 n_iqk_ok_cnt; 1160 u32 n_iqk_fail_cnt; 1161 1162 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 1163 boolean config_bbrf; 1164 #endif 1165 boolean is_disable_power_training; 1166 boolean is_bt_continuous_turn; 1167 u8 enhance_pwr_th[3]; 1168 u8 set_pwr_th[3]; 1169 /*@----------Dyn Tx Pwr ---------------------------------------*/ 1170 #ifdef BB_RAM_SUPPORT 1171 struct phydm_bb_ram_ctrl p_bb_ram_ctrl; 1172 #endif 1173 u8 dynamic_tx_high_power_lvl; 1174 void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); 1175 u8 last_dtp_lvl; 1176 u8 min_power_index; 1177 u32 tx_agc_ofdm_18_6; 1178 /*-------------------------------------------------------------*/ 1179 u8 rx_pkt_type; 1180 1181 #ifdef CONFIG_PHYDM_DFS_MASTER 1182 u8 dfs_region_domain; 1183 u8 *dfs_master_enabled; 1184 /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ 1185 u8 radar_detect_dbg_parm_en; 1186 u32 radar_detect_reg_918; 1187 u32 radar_detect_reg_91c; 1188 u32 radar_detect_reg_920; 1189 u32 radar_detect_reg_924; 1190 1191 u32 radar_detect_reg_a40; 1192 u32 radar_detect_reg_a44; 1193 u32 radar_detect_reg_a48; 1194 u32 radar_detect_reg_a4c; 1195 u32 radar_detect_reg_a50; 1196 u32 radar_detect_reg_a54; 1197 1198 u32 radar_detect_reg_f54; 1199 u32 radar_detect_reg_f58; 1200 u32 radar_detect_reg_f5c; 1201 u32 radar_detect_reg_f70; 1202 u32 radar_detect_reg_f74; 1203 /*@---For zero-wait DFS---------------------------------------*/ 1204 boolean seg1_dfs_flag; 1205 /*@---For ETSI 302 ---------------------------------------*/ 1206 /*@-----------------------------------------------------------*/ 1207 #endif 1208 1209 /*@=== RTL8721D ===*/ 1210 #if (RTL8721D_SUPPORT) 1211 boolean cbw20_adc80; 1212 boolean invalid_mode; 1213 u8 power_voltage; 1214 u8 cca_cbw20_lev; 1215 u8 cca_cbw40_lev; 1216 u8 antdiv_gpio; 1217 u8 peak_detect_mode; 1218 #endif 1219 1220 /*@=== PHYDM Timer ========================================== (start)*/ 1221 1222 struct phydm_timer_list mpt_dig_timer; 1223 struct phydm_timer_list fast_ant_training_timer; 1224 #ifdef ODM_EVM_ENHANCE_ANTDIV 1225 struct phydm_timer_list evm_fast_ant_training_timer; 1226 #endif 1227 #ifdef PHYDM_TDMA_DIG_SUPPORT 1228 struct phydm_timer_list tdma_dig_timer; 1229 #endif 1230 struct phydm_timer_list sbdcnt_timer; 1231 1232 /*@=== PHYDM Workitem ======================================= (start)*/ 1233 1234 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1235 #if USE_WORKITEM 1236 RT_WORK_ITEM fast_ant_training_workitem; 1237 RT_WORK_ITEM ra_rpt_workitem; 1238 RT_WORK_ITEM sbdcnt_workitem; 1239 RT_WORK_ITEM phydm_evm_antdiv_workitem; 1240 #ifdef PHYDM_TDMA_DIG_SUPPORT 1241 RT_WORK_ITEM phydm_tdma_dig_workitem; 1242 #endif 1243 #endif 1244 #endif 1245 1246 /*@=== PHYDM Structure ======================================== (start)*/ 1247 struct phydm_func_poiner phydm_func_handler; 1248 struct phydm_iot_center iot_table; 1249 1250 #ifdef ODM_CONFIG_BT_COEXIST 1251 struct phydm_bt_info bt_info_table; 1252 #endif 1253 1254 struct pkt_process_info pkt_proc_struct; 1255 struct phydm_adaptivity_struct adaptivity; 1256 #ifdef CONFIG_PHYDM_DFS_MASTER 1257 struct _DFS_STATISTICS dfs; 1258 #endif 1259 struct odm_noise_monitor noise_level; 1260 struct odm_phy_dbg_info phy_dbg_info; 1261 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1262 struct odm_phy_dbg_info phy_dbg_info_win_bkp; 1263 #endif 1264 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 1265 struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3; 1266 #endif 1267 1268 #ifdef CONFIG_ADAPTIVE_SOML 1269 struct adaptive_soml dm_soml_table; 1270 #endif 1271 1272 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 1273 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 1274 struct _BF_DIV_COEX_ dm_bdc_table; 1275 #endif 1276 1277 #if (defined(CONFIG_HL_SMART_ANTENNA)) 1278 struct smt_ant_honbo dm_sat_table; 1279 #endif 1280 #endif 1281 1282 #if (defined(CONFIG_SMART_ANTENNA)) 1283 struct smt_ant smtant_table; 1284 #endif 1285 1286 struct _hal_rf_ rf_table; /*@for HALRF function*/ 1287 struct dm_rf_calibration_struct rf_calibrate_info; 1288 struct dm_iqk_info IQK_info; 1289 struct dm_dpk_info dpk_info; 1290 struct dm_dack_info dack_info; 1291 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 1292 struct phydm_fat_struct dm_fat_table; 1293 struct sw_antenna_switch dm_swat_table; 1294 #endif 1295 struct phydm_dig_struct dm_dig_table; 1296 1297 #ifdef PHYDM_SUPPORT_CCKPD 1298 struct phydm_cckpd_struct dm_cckpd_table; 1299 1300 #ifdef PHYDM_DCC_ENHANCE 1301 struct phydm_dcc_struct dm_dcc_info; /*dig cckpd coex*/ 1302 #endif 1303 #endif 1304 1305 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 1306 struct phydm_lna_sat_t dm_lna_sat_info; 1307 #endif 1308 1309 #ifdef CONFIG_MCC_DM 1310 struct _phydm_mcc_dm_ mcc_dm; 1311 #endif 1312 1313 #ifdef PHYDM_PRIMARY_CCA 1314 struct phydm_pricca_struct dm_pri_cca; 1315 #endif 1316 1317 struct ra_table dm_ra_table; 1318 struct phydm_fa_struct false_alm_cnt; 1319 #ifdef PHYDM_TDMA_DIG_SUPPORT 1320 struct phydm_fa_acc_struct false_alm_cnt_acc; 1321 #ifdef IS_USE_NEW_TDMA 1322 struct phydm_fa_acc_struct false_alm_cnt_acc_low; 1323 #endif 1324 #endif 1325 struct phydm_cfo_track_struct dm_cfo_track; 1326 struct ccx_info dm_ccx_info; 1327 1328 struct odm_power_trim_data power_trim_data; 1329 #if (RTL8822B_SUPPORT) 1330 struct drp_rtl8822b_struct phydm_rtl8822b; 1331 #endif 1332 1333 #ifdef CONFIG_PSD_TOOL 1334 struct psd_info dm_psd_table; 1335 #endif 1336 1337 #if (PHYDM_LA_MODE_SUPPORT) 1338 struct rt_adcsmp adcsmp; 1339 #endif 1340 1341 #if (defined(CONFIG_PATH_DIVERSITY)) 1342 struct _ODM_PATH_DIVERSITY_ dm_path_div; 1343 #endif 1344 1345 #if (defined(CONFIG_ANT_DETECTION)) 1346 struct _ANT_DETECTED_INFO ant_detected_info; 1347 #endif 1348 1349 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1350 #ifdef PHYDM_BEAMFORMING_SUPPORT 1351 struct _RT_BEAMFORMING_INFO beamforming_info; 1352 #endif 1353 #endif 1354 #ifdef PHYDM_AUTO_DEGBUG 1355 struct phydm_auto_dbg_struct auto_dbg_table; 1356 #endif 1357 1358 struct phydm_pause_lv pause_lv_table; 1359 struct phydm_api_stuc api_table; 1360 #ifdef PHYDM_POWER_TRAINING_SUPPORT 1361 struct phydm_pow_train_stuc pow_train_table; 1362 #endif 1363 1364 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 1365 struct phydm_pmac_tx dm_pmac_tx_table; 1366 #endif 1367 1368 #ifdef PHYDM_MP_SUPPORT 1369 struct phydm_mp dm_mp_table; 1370 #endif 1371 1372 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 1373 struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table; 1374 #endif 1375 /*@==========================================================*/ 1376 1377 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 1378 /*@-------------------phydm_phystatus report --------------------*/ 1379 struct phydm_physts dm_physts_table; 1380 #endif 1381 1382 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1383 1384 #if (RT_PLATFORM != PLATFORM_LINUX) 1385 } dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ 1386 #else 1387 }; 1388 #endif 1389 1390 #else /*@for AP,CE Team*/ 1391 }; 1392 #endif 1393 1394 enum phydm_adv_ota { 1395 PHYDM_PATHB_1RCCA = BIT(0), 1396 PHYDM_HP_OTA_SETTING_A = BIT(1), 1397 PHYDM_HP_OTA_SETTING_B = BIT(2), 1398 PHYDM_ASUS_OTA_SETTING = BIT(3), 1399 PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), 1400 PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), 1401 PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), 1402 1403 }; 1404 1405 enum phydm_bb_op_mode { 1406 PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ 1407 PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ 1408 }; 1409 1410 enum phydm_structure_type { 1411 PHYDM_FALSEALMCNT, 1412 PHYDM_CFOTRACK, 1413 PHYDM_ADAPTIVITY, 1414 PHYDM_DFS, 1415 PHYDM_ROMINFO, 1416 1417 }; 1418 1419 enum odm_bb_config_type { 1420 CONFIG_BB_PHY_REG, 1421 CONFIG_BB_AGC_TAB, 1422 CONFIG_BB_AGC_TAB_2G, 1423 CONFIG_BB_AGC_TAB_5G, 1424 CONFIG_BB_PHY_REG_PG, 1425 CONFIG_BB_PHY_REG_MP, 1426 CONFIG_BB_AGC_TAB_DIFF, 1427 CONFIG_BB_RF_CAL_INIT, 1428 }; 1429 1430 enum odm_rf_config_type { 1431 CONFIG_RF_RADIO, 1432 CONFIG_RF_TXPWR_LMT, 1433 CONFIG_RF_SYN_RADIO, 1434 }; 1435 1436 enum odm_fw_config_type { 1437 CONFIG_FW_NIC, 1438 CONFIG_FW_NIC_2, 1439 CONFIG_FW_AP, 1440 CONFIG_FW_AP_2, 1441 CONFIG_FW_MP, 1442 CONFIG_FW_WOWLAN, 1443 CONFIG_FW_WOWLAN_2, 1444 CONFIG_FW_AP_WOWLAN, 1445 CONFIG_FW_BT, 1446 }; 1447 1448 /*status code*/ 1449 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1450 enum rt_status { 1451 RT_STATUS_SUCCESS, 1452 RT_STATUS_FAILURE, 1453 RT_STATUS_PENDING, 1454 RT_STATUS_RESOURCE, 1455 RT_STATUS_INVALID_CONTEXT, 1456 RT_STATUS_INVALID_PARAMETER, 1457 RT_STATUS_NOT_SUPPORT, 1458 RT_STATUS_OS_API_FAILED, 1459 }; 1460 #endif /*@end of enum rt_status definition*/ 1461 1462 void 1463 phydm_watchdog_lps(struct dm_struct *dm); 1464 1465 void 1466 phydm_watchdog_lps_32k(struct dm_struct *dm); 1467 1468 void 1469 phydm_txcurrentcalibration(struct dm_struct *dm); 1470 1471 void 1472 phydm_dm_early_init(struct dm_struct *dm); 1473 1474 enum phydm_init_result 1475 odm_dm_init(struct dm_struct *dm); 1476 1477 void 1478 odm_dm_reset(struct dm_struct *dm); 1479 1480 void 1481 phydm_fwoffload_ability_init(struct dm_struct *dm, 1482 enum phydm_offload_ability offload_ability); 1483 1484 void 1485 phydm_fwoffload_ability_clear(struct dm_struct *dm, 1486 enum phydm_offload_ability offload_ability); 1487 1488 void 1489 phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, 1490 char *output, u32 *_out_len); 1491 1492 void 1493 phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); 1494 1495 void 1496 phydm_watchdog(struct dm_struct *dm); 1497 1498 void 1499 phydm_watchdog_mp(struct dm_struct *dm); 1500 1501 void 1502 phydm_pause_func_init(void *dm_void); 1503 1504 u8 1505 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, 1506 enum phydm_pause_type pause_type, 1507 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); 1508 1509 void 1510 phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, 1511 char *output, u32 *_out_len); 1512 1513 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm, 1514 enum phydm_pause_type pause_type, u8 rssi); 1515 1516 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx, 1517 boolean enable); 1518 1519 void 1520 odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); 1521 1522 void 1523 odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); 1524 1525 void 1526 odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); 1527 1528 u32 1529 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); 1530 1531 void 1532 odm_init_all_timers(struct dm_struct *dm); 1533 1534 void 1535 odm_cancel_all_timers(struct dm_struct *dm); 1536 1537 void 1538 odm_release_all_timers(struct dm_struct *dm); 1539 1540 void * 1541 phydm_get_structure(struct dm_struct *dm, u8 structure_type); 1542 1543 void 1544 phydm_dc_cancellation(struct dm_struct *dm); 1545 1546 void 1547 phydm_receiver_blocking(void *dm_void); 1548 1549 void 1550 phydm_dyn_bw_indication(void *dm_void); 1551 1552 void 1553 phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en); 1554 1555 1556 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH 1557 void 1558 phydm_tx_collsion_th_init(void *dm_void); 1559 1560 void 1561 phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r); 1562 #endif 1563 1564 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1565 void 1566 odm_init_all_work_items( 1567 struct dm_struct *dm 1568 ); 1569 void 1570 odm_free_all_work_items( 1571 struct dm_struct *dm 1572 ); 1573 #endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ 1574 1575 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1576 void 1577 odm_dtc(struct dm_struct *dm); 1578 #endif 1579 1580 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 1581 void 1582 odm_init_all_threads( 1583 struct dm_struct *dm 1584 ); 1585 1586 void 1587 odm_stop_all_threads( 1588 struct dm_struct *dm 1589 ); 1590 #endif 1591 1592 #endif 1593