1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __PLAT_DEF_H__ 7 #define __PLAT_DEF_H__ 8 9 #define SIZE_K(n) ((n) * 1024) 10 #define SIZE_M(n) ((n) * 1024 * 1024) 11 12 #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) 13 #define BITS_WMSK(msk, shift) ((msk) << ((shift) + REG_MSK_SHIFT)) 14 15 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 16 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 17 18 #define RK3576_DEV_RNG0_BASE 0x00000000 19 #define RK3576_DEV_RNG0_SIZE 0x40000000 20 21 #define RK_DRAM_BASE 0x40000000 22 23 /* All slave base address declare below */ 24 #define MCU_TCM_BASE 0x23800000 25 #define MCU_CACHE_BASE 0x23810000 26 #define MCU_RAM_TEST_BASE 0x23820000 27 #define MCU_BOOT_BASE 0x00000000 28 #define MCU_MAIN_BASE 0x00010000 29 #define PMU0SGRF_BASE 0x26000000 30 #define PMU1SGRF_BASE 0x26002000 31 #define PMU1SGRF_FW_BASE 0x26003000 32 #define SYS_SGRF_BASE 0x26004000 33 #define SYS_SGRF_FW_BASE 0x26005000 34 #define SYS_GRF_BASE 0x2600a000 35 #define BIGCORE_GRF_BASE 0x2600c000 36 #define LITCORE_GRF_BASE 0x2600e000 37 #define CCI_GRF_BASE 0x26010000 38 #define DDR_GRF_BASE 0x26012000 39 #define CENTER_GRF_BASE 0x26014000 40 #define GPUGRF_BASE 0x26016000 41 #define NPUGRF_BASE 0x26018000 42 #define VO_GRF_BASE 0x2601a000 43 #define VI_GRF_BASE 0x2601c000 44 #define USB_GRF_BASE 0x2601e000 45 #define PHP_GRF_BASE 0x26020000 46 #define VOP_GRF_BASE 0x26022000 47 #define PMU0_GRF_BASE 0x26024000 48 #define PMU1_GRF_BASE 0x26026000 49 #define USBDPPHY_GRF_BASE 0x2602c000 50 #define USB2PHY0_GRF_BASE 0x2602e000 51 #define USB2PHY1_GRF_BASE 0x26030000 52 #define PMU0_IOC_BASE 0x26040000 53 #define PMU1_IOC_BASE 0x26042000 54 #define TOP_IOC_BASE 0x26044000 55 #define VCCIO_IOC_BASE 0x26046000 56 #define VCCIO6_IOC_BASE 0x2604a000 57 #define VCCIO7_IOC_BASE 0x2604b000 58 #define CRU_BASE 0x27200000 59 #define PHP_CRU_BASE 0x27208000 60 #define SECURE_CRU_BASE 0x27210000 61 #define PMU1_CRU_BASE 0x27220000 62 #define DDRPHY0_CRU_BASE 0x27228000 63 #define DDRPHY1_CRU_BASE 0x27230000 64 #define BIGCORE_CRU_BASE 0x27238000 65 #define LITTLE_CRU_BASE 0x27240000 66 #define CCI_CRU_BASE 0x27248000 67 #define PVTPLL_CCI_BASE 0x27250000 68 #define PVTPLL_BIGCORE_BASE 0x27258000 69 #define PVTPLL_LITCORE_BASE 0x27260000 70 #define PVTPLL_GPU_BASE 0x27268000 71 #define PVTPLL_NPU_BASE 0x27270000 72 #define PVTPLL_CRU_BASE 0x27278000 73 #define I2C0_BASE 0x27300000 74 #define UART1_BASE 0x27310000 75 #define GPIO0_BASE 0x27320000 76 #define PWM0_BASE 0x27330000 77 #define WDT_PMU_BASE 0x27340000 78 #define TIMER_PMU_BASE 0x27350000 79 #define PMU_BASE 0x27360000 80 #define PMU0_BASE 0x27360000 81 #define PMU1_BASE 0x27370000 82 #define PMU2_BASE 0x27380000 83 #define PVTM_PMU_BASE 0x273f0000 84 #define HPTIMER_BASE 0x27400000 85 #define CCI_BASE 0x27500000 86 #define VOP_BASE 0x27d00000 87 #define INTERCONNECT_BASE 0x27f00000 88 #define FW_CCI2DDR_BASE 0x27f80000 89 #define FW_CENTER2DDR_BASE 0x27f90000 90 #define FW_SYSMEM_BASE 0x27fa0000 91 #define FW_VOP2DDR_BASE 0x27fb0000 92 #define FW_CBUF_BASE 0x27fc0000 93 #define FIREWALL_DDR_BASE 0x27f80000 94 #define DDRCTL0_BASE 0x28000000 95 #define DDRCTL1_BASE 0x29000000 96 #define DDR_MONITOR0_BASE 0x2a000000 97 #define DDR_MONITOR1_BASE 0x2a010000 98 #define DDRPHY0_BASE 0x2a020000 99 #define DDRPHY1_BASE 0x2a030000 100 #define HWLP0_BASE 0x2a060000 101 #define HWLP1_BASE 0x2a070000 102 #define KEYLADDER_BASE 0x2a420000 103 #define CRYPTO_S_BASE 0x2a430000 104 #define OTP_S_BASE 0x2a480000 105 #define DCF_BASE 0x2a490000 106 #define STIMER0_BASE 0x2a4a0000 107 #define STIMER1_BASE 0x2a4b0000 108 #define WDT_S_BASE 0x2a4c0000 109 #define OTP_MASK_BASE 0x2a4d0000 110 #define OTP_NS_BASE 0x2a580000 111 #define GIC400_BASE 0x2a700000 112 #define I2C1_BASE 0x2ac40000 113 #define NSTIMER0_BASE 0x2acc0000 114 #define NSTIMER1_BASE 0x2acd0000 115 #define WDT_NS_BASE 0x2ace0000 116 #define UART0_BASE 0x2ad40000 117 #define UART2_BASE 0x2ad50000 118 #define UART3_BASE 0x2ad60000 119 #define UART4_BASE 0x2ad70000 120 #define UART5_BASE 0x2ad80000 121 #define UART6_BASE 0x2ad90000 122 #define UART7_BASE 0x2ada0000 123 #define UART8_BASE 0x2adb0000 124 #define UART9_BASE 0x2adc0000 125 #define PWM1_BASE 0x2add0000 126 #define PWM2_BASE 0x2ade0000 127 #define PWM3_BASE 0x2adf0000 128 #define GPIO1_BASE 0x2ae10000 129 #define GPIO2_BASE 0x2ae20000 130 #define GPIO3_BASE 0x2ae30000 131 #define GPIO4_BASE 0x2ae40000 132 #define TSADC_BASE 0x2ae70000 133 134 #define PMUSRAM_BASE 0x3fe70000 135 #define PMUSRAM_RSIZE SIZE_K(32) 136 137 #define CBUF_BASE 0x3fe80000 138 #define SRAM_BASE 0x3ff80000 139 140 #define STIMER0_CHN_BASE(i) (STIMER0_BASE + 0x1000 * (i)) 141 #define STIMER1_CHN_BASE(i) (STIMER1_BASE + 0x1000 * (i)) 142 143 #define NSTIMER0_CHN_BASE(i) (NSTIMER0_BASE + 0x1000 * (i)) 144 #define NSTIMER1_CHN_BASE(i) (NSTIMER1_BASE + 0x1000 * (i)) 145 146 #define DDRPHY_BASE_CH(n) (DDRPHY0_BASE + ((n) * 0x10000)) 147 #define DDRPHY_CRU_BASE_CH(n) (DDRPHY0_CRU_BASE + ((n) * 0x8000)) 148 #define UMCTL_BASE_CH(n) (DDRCTL0_BASE + ((n) * 0x1000000)) 149 #define HWLP_BASE_CH(n) (HWLP0_BASE + ((n) * 0x10000)) 150 #define MAILBOX1_BASE (0x2ae50000 + 0xb000) 151 152 #define CRYPTO_S_BY_KEYLAD_BASE CRYPTO_S_BASE 153 154 #define DDR_SHARE_MEM (RK_DRAM_BASE + SIZE_K(1024)) 155 #define DDR_SHARE_SIZE SIZE_K(64) 156 157 #define SHARE_MEM_BASE DDR_SHARE_MEM 158 #define SHARE_MEM_PAGE_NUM 15 159 #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 160 161 #define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE) 162 #define SCMI_SHARE_MEM_SIZE SIZE_K(4) 163 164 #define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE 165 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 166 167 #define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(8) 168 169 /****************************************************************************** 170 * sgi, ppi 171 ******************************************************************************/ 172 #define RK_IRQ_SEC_PHY_TIMER 29 173 174 #define RK_IRQ_SEC_SGI_0 8 175 #define RK_IRQ_SEC_SGI_1 9 176 #define RK_IRQ_SEC_SGI_2 10 177 #define RK_IRQ_SEC_SGI_3 11 178 #define RK_IRQ_SEC_SGI_4 12 179 #define RK_IRQ_SEC_SGI_5 13 180 #define RK_IRQ_SEC_SGI_6 14 181 #define RK_IRQ_SEC_SGI_7 15 182 183 /* 184 * Define a list of Group 0 interrupts. 185 */ 186 #define PLAT_RK_GICV2_G0_IRQS \ 187 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 188 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ 189 INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 190 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) 191 192 /* UART related constants */ 193 #define RK_DBG_UART_BASE UART0_BASE 194 #define RK_DBG_UART_BAUDRATE 1500000 195 #define RK_DBG_UART_CLOCK 24000000 196 197 /* Base rk_platform compatible GIC memory map */ 198 #define PLAT_GICD_BASE (GIC400_BASE + 0x1000) 199 #define PLAT_GICC_BASE (GIC400_BASE + 0x2000) 200 #define PLAT_GICR_BASE 0 201 202 /* CCI */ 203 #define PLAT_RK_CCI_BASE CCI_BASE 204 #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 1 205 #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 2 206 207 #endif /* __PLAT_DEF_H__ */ 208