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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef MHAL_XC_CONFIG_H 95 #define MHAL_XC_CONFIG_H 96 97 //------------------------------------------------------------------------------------------------- 98 // Monaco 99 //------------------------------------------------------------------------------------------------- 100 //------------------------------------------------------------------------------------------------- 101 // Chip Configuration 102 //------------------------------------------------------------------------------------------------- 103 #define MAX_XC_DEVICE_NUM (2) 104 #define MAX_XC_DEVICE0_OFFSET (0) 105 #define MAX_XC_DEVICE1_OFFSET (128) 106 107 #define MAX_WINDOW_NUM (2) 108 #define MAX_FRAME_NUM_IN_MEM (4) // Progressive 109 #define MAX_FIELD_NUM_IN_MEM (16) // Interlace 110 #define NUM_OF_DIGITAL_DDCRAM (1) 111 112 #define SCALER_LINE_BUFFER_MAX (4096UL) 113 #define MST_LINE_BFF_MAX MAX(4096, SCALER_LINE_BUFFER_MAX) 114 115 #define SUB_MAIN_LINEOFFSET_GUARD_BAND 0 116 #define SUB_SCALER_LINE_BUFFER_MAX 2048UL - SUB_MAIN_LINEOFFSET_GUARD_BAND 117 #define SUB_MST_LINE_BFF_MAX SUB_SCALER_LINE_BUFFER_MAX 118 119 #define MS_3D_LINE_BFF_MAX (2048UL) 120 #define PHASE_OFFSET_LIMIT (0x900UL) 121 #define PHASE_OFFSET_LIMIT_HDMITX (0x500UL) 122 #define PHASE_OFFSET_LIMIT_FREQ_ONLY (0x1200UL) //0x03DFUL // 0x8000UL 123 #define LPLL_LIMIT_OFFSET (0x1600UL) 124 125 // MIU Word (Bytes) 126 #define BYTE_PER_WORD (32) // MIU 128: 16Byte/W, MIU 256: 32Byte/W 127 #define OFFSET_PIXEL_ALIGNMENT (64) 128 #define LPLL_LOOPGAIN (32) //due to bound cale. 129 #define LVDS_MPLL_CLOCK_MHZ (432) 130 #define FRC_OFFSET_PIXEL_ALIGNMENT (128) 131 132 #define FRC_BYTE_PER_WORD 32 133 #define MCDI_BYTE_PER_WORD 32 134 135 #define FRC_LINE_BUFFER_MAX (3840UL) 136 137 //value for pipe vcnt and hcnt delay 138 #define FRC_PIPE_DELAY_VCNT_FRC 0x10 // need to wait for FRC set to adjust this 139 #define FRC_PIPE_DELAY_HCNT_FRC 0x140 // need to wait for FRC set to adjust this 140 #define FRC_PIPE_DELAY_VCNT_FRC_FHD_OUT 0x06 // need to wait for FHD set to adjust this 141 #define FRC_PIPE_DELAY_HCNT_FRC_FHD_OUT 0x140 // need to wait for FHD set to adjust this 142 #define FRC_PIPE_DELAY_VCNT_FSC_FHD 0x10 143 #define FRC_PIPE_DELAY_VCNT_FSC_4K 0x06 144 #define FRC_PIPE_DELAY_HCNT_FSC_FHD 0x140 145 #define FRC_PIPE_DELAY_HCNT_FSC_4K 0x140 146 #define FRC_PIPE_DELAY_VCNT_FSC_4K_120Hz 0x0A // Maxim no 120Hz case, don't case this 147 #define FRC_PIPE_DELAY_HCNT_FSC_4K_120Hz 0x140 // Maxim no 120Hz case, don't case this 148 149 150 #define DEFAULT_STEP_P 4 //conservative step value 151 #define DEFAULT_STEP_I ((DEFAULT_STEP_P*DEFAULT_STEP_P)/2) 152 #define STEP_P 2 //recommended step value -> more faster fpll(T3) 153 #define STEP_I ((STEP_P*STEP_P)/2) 154 #define IPGAIN_REFACTOR 5 155 156 #define F2_WRITE_LIMIT_EN BIT(31) //BK12_1b[15] 157 #define F2_WRITE_LIMIT_MIN BIT(30) //BK12_1b[14] 158 159 #define F1_WRITE_LIMIT_EN BIT(31) //BK12_5b[15] 160 #define F1_WRITE_LIMIT_MIN BIT(30) //BK12_5b[14] 161 162 #define F2_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_1b[15] 163 #define F1_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_5b[15] 164 165 #define F2_V_WRITE_LIMIT_EN BIT(15) //BK12_18[12] 166 #define F1_V_WRITE_LIMIT_EN BIT(15) //BK12_58[12] 167 168 #define F2_OPW_WRITE_LIMIT_EN BIT(31) //for UC 169 #define F2_OPW_WRITE_LIMIT_MIN BIT(30) //for UC 170 171 #define ADC_MAX_CLK (3500) 172 173 #define SUPPORTED_XC_INT ((1UL << SC_INT_DIPW) | \ 174 (1UL << SC_INT_VSINT) | \ 175 (1UL << SC_INT_F2_VTT_CHG) | \ 176 (1UL << SC_INT_F1_VTT_CHG) | \ 177 (1UL << SC_INT_F2_VS_LOSE) | \ 178 (1UL << SC_INT_F1_VS_LOSE) | \ 179 (1UL << SC_INT_F2_JITTER) | \ 180 (1UL << SC_INT_F1_JITTER) | \ 181 (1UL << SC_INT_F2_IPVS_SB) | \ 182 (1UL << SC_INT_F1_IPVS_SB) | \ 183 (1UL << SC_INT_F2_IPHCS_DET) | \ 184 (1UL << SC_INT_F1_IPHCS_DET) | \ 185 (1UL << SC_INT_F2_HTT_CHG) | \ 186 (1UL << SC_INT_F1_HTT_CHG) | \ 187 (1UL << SC_INT_F2_HS_LOSE) | \ 188 (1UL << SC_INT_F1_HS_LOSE) | \ 189 (1UL << SC_INT_F2_CSOG) | \ 190 (1UL << SC_INT_F1_CSOG) | \ 191 (1UL << SC_INT_F2_ATP_READY) | \ 192 (1UL << SC_INT_F1_ATP_READY)) 193 194 #define SUPPORTED_KERNEL_INT ((1UL << SC_INT_VSINT)|(1UL << SC_INT_PWM_RP_R_INT)|(1UL << SC_INT_PWM_FP_R_INT)) 195 196 //These table definition is from SC_BK0 spec. 197 //Because some chip development is different, it need to check and remap when INT function is used 198 #define IRQ_CLEAN_INKERNEL 1 199 200 #define IRQ_INT_DIPW 0 201 #define IRQ_INT_START 3 202 #define IRQ_INT_RESERVED1 IRQ_INT_START 203 204 #define IRQ_INT_VSINT 4 205 #define IRQ_INT_F2_VTT_CHG 5 206 #define IRQ_INT_F1_VTT_CHG 6 207 #define IRQ_INT_F2_VS_LOSE 7 208 #define IRQ_INT_F1_VS_LOSE 8 209 #define IRQ_INT_F2_JITTER 9 210 #define IRQ_INT_F1_JITTER 10 211 #define IRQ_INT_F2_IPVS_SB 11 212 #define IRQ_INT_F1_IPVS_SB 12 213 #define IRQ_INT_F2_IPHCS_DET 13 214 #define IRQ_INT_F1_IPHCS_DET 14 215 216 #define IRQ_INT_PWM_RP_L_INT 15 217 #define IRQ_INT_PWM_FP_L_INT 16 218 #define IRQ_INT_F2_HTT_CHG 17 219 #define IRQ_INT_F1_HTT_CHG 18 220 #define IRQ_INT_F2_HS_LOSE 19 221 #define IRQ_INT_F1_HS_LOSE 20 222 #define IRQ_INT_PWM_RP_R_INT 21 223 #define IRQ_INT_PWM_FP_R_INT 22 224 #define IRQ_INT_F2_CSOG 23 225 #define IRQ_INT_F1_CSOG 24 226 #define IRQ_INT_F2_RESERVED2 25 227 #define IRQ_INT_F1_RESERVED2 26 228 #define IRQ_INT_F2_ATP_READY 27 229 #define IRQ_INT_F1_ATP_READY 28 230 #define IRQ_INT_F2_RESERVED3 29 231 #define IRQ_INT_F1_RESERVED3 30 232 233 //------------------------------------------------------------------------------------------------- 234 // Chip Feature 235 //------------------------------------------------------------------------------------------------- 236 /* 12 frame mode for progessive */ 237 #define _12FRAME_BUFFER_PMODE_SUPPORTED 1 238 /* 8 frame mode for progessive */ 239 #define _8FRAME_BUFFER_PMODE_SUPPORTED 1 240 /* 6 frame mode for progessive */ 241 #define _6FRAME_BUFFER_PMODE_SUPPORTED 1 242 /* 4 frame mode for progessive */ 243 #define _4FRAME_BUFFER_PMODE_SUPPORTED 1 244 /* 3 frame mode for progessive */ 245 #define _3FRAME_BUFFER_PMODE_SUPPORTED 1 246 247 // Maxim fix this HW bug, so remove SW patch 248 /* change Vtt BK68 replace BK10 */ 249 //#define PATCH_HW_VTT_LIMITATION 1 250 /* Vtt BK10 not be replaced, CHIP number after U3 */ 251 //#define HW_VTT_LIMITATION_CHIPREV 2 252 253 /* 254 Field-packing ( Customized name ) 255 This is a feature in M10. M10 only needs one IPM buffer address. (Other chips need two or three 256 IPM buffer address). We show one of memory format for example at below. 257 258 Block : Y0 C0 L M Y1 C1 259 Each block contain 4 fields (F0 ~ F3) and each fields in one block is 64 bits 260 Y0 has 64 * 4 bits ( 8 pixel for each field ). 261 Y1 has 64 * 4 bits ( 8 pixel for each field ). 262 So, in this memory format, pixel alignment is 16 pixels (OFFSET_PIXEL_ALIGNMENT = 16). 263 For cropping, OPM address offset have to multiple 4. 264 */ 265 #define _FIELD_PACKING_MODE_SUPPORTED 1 266 267 #if (_FIELD_PACKING_MODE_SUPPORTED) 268 269 /* Linear mode */ 270 #define _LINEAR_ADDRESS_MODE_SUPPORTED 0 271 272 #else 273 /* Linear mode */ 274 #define _LINEAR_ADDRESS_MODE_SUPPORTED 1 275 276 #endif 277 278 #define SUPPORT_2_FRAME_MIRROR 0 279 280 /* Because fix loop_div, lpll initial set is different between singal port and dual port */ 281 #define _FIX_LOOP_DIV_SUPPORTED 1 282 283 // You can only enable ENABLE_8_FIELD_SUPPORTED or ENABLE_16_FIELD_SUPPORTED. (one of them) 284 // 16 field mode include 8 field configurion in it. ENABLE_8_FIELD_SUPPORTED is specital case in T7 285 #define ENABLE_8_FIELD_SUPPORTED 0 286 #define ENABLE_16_FIELD_SUPPORTED 1 287 #define ENABLE_OPM_WRITE_SUPPORTED 1 288 #define ENABLE_YPBPR_PRESCALING_TO_ORIGINAL 0 289 #define ENABLE_VD_PRESCALING_TO_DOT75 0 290 #define ENABLE_NONSTD_INPUT_MCNR 0 291 #define ENABLE_REGISTER_SPREAD 1 292 293 #define ENABLE_REQUEST_FBL 1 294 #define DELAY_LINE_SC_UP 7 295 #define DELAY_LINE_SC_DOWN 8 296 297 #define CHANGE_VTT_STEPS 1 298 #define CHANGE_VTT_DELAY 1 299 300 #define SUPPORT_IMMESWITCH 1 301 #define SUPPORT_DVI_AUTO_EQ 1 302 #define SUPPORT_MHL 0 303 #define SUPPORT_HDMI_RX_NEW_FEATURE 1 304 #define SUPPORT_DEVICE1 0 305 #define SUPPORT_SEAMLESS_ZAPPING 0 306 #define SUPPORT_OP2_TEST_PATTERN 1 307 #define SUPPORT_FRCM_MODE 0 308 #define SUPPORT_4K2K_PIP 1 309 #define SUPPORT_KERNEL_MLOAD 1 310 #define SUPPORT_KERNEL_DS 1 311 312 // Special frame lock means that the frame rates of input and output are the same in HW design spec. 313 #define SUPPORT_SPECIAL_FRAMELOCK FALSE 314 315 #define LD_ENABLE 0 // 1 316 #define FRC_INSIDE TRUE //FALSE 317 #define FRC_IP_NUM_Passive 17 //FRC__NUM_FRC_Mapping_mode 318 #define ENABLE_SPREADMODE 319 #define SUPPORT_FHD_MEMC 320 //#define HW_SUPPORT_FRC_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE 321 322 // 480p and 576p have FPLL problem in HV mode. 323 // So only allow HV mode for 720P 324 #define ONLY_ALLOW_HV_MODE_FOR_720P 0 325 326 //For Manhattan U01 GOP HW bug //U02 Fix 327 #define MANHATTAN_GOP_HW_BUG_PATCH 0 328 329 #define MAXIM_ATV_LOCK_PHASE_PATCH 330 331 #define _ENABLE_SW_DS 0 332 #define DS_BUFFER_NUM_EX 6 333 #define DS_MAX_INDEX 6 334 335 #define ENABLE_64BITS_COMMAND 1 336 #define ENABLE_64BITS_SPREAD_MODE 1 //need enable ENABLE_64BITS_COMMAND first 337 //------------------------------------------------------------------------------------------------- 338 /// enable ENABLE_MLOAD_SAME_REG_COMBINE you can do: 339 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(N), BIT(N)); 340 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(M), BIT(M)); 341 /// MApi_XC_MLoad_Fire(); 342 //------------------------------------------------------------------------------------------------- 343 #define ENABLE_MLOAD_SAME_REG_COMBINE 1 344 //#define SRAMPD_XC_CLOSE_TEMP 1 345 346 #define IS_SUPPORT_64BITS_COMMAND(bEnable64bitsCmd, u32DeviceID) ((bEnable64bitsCmd == 1) && (u32DeviceID == 0)) 347 #define ENABLE_DS_4_BASEADDR_MODE 1 // need enable both ENABLE_64BITS_COMMAND and ENABLE_64BITS_SPREAD_MODE first 348 #define DS_CMD_LEN_64BITS 8 349 350 #define IS_SUPPORT_DS_SR(fps) 0//((fps >= 230) && (fps <= 600)) 351 // T12, T13 cannot use IP_HDMI for HV mode 352 // We must use IP_HDMI for HV mode, otherwise 480i 576i will have color space proble,m 353 //Note: if use IP_HDMI, MApi_XC_GetDEWindow() cannot get value correctly 354 // and IP_HDMI is set in MApi_XC_SetInputSource(), so cannot change dynamically 355 // Thus, chip could use this flag to determine whether could do HV mode or not. 356 #define SUPPORT_IP_HDMI_FOR_HV_MODE 0 357 358 // version1: edison: 4k2k@mm :mvop->dip->gop->ursa; 4k2k@hdmi:hdmi->ursa 359 // version2: nike: 360 // version3: napoli: frc: double frc and width 361 // version4: monaco: frcm and 2p 362 // version5: clippers: 4k2k@60 MVOP directly output to HVSP 363 // version6: Monet/Maya/Manhattan: 364 // for Manhattan pip:1.SC1(1P) Htt = SC0(2P) Htt/2 365 // 2.if xc mute SC1 main, please mute SC0 sub. The same to mute color. 366 // 3.SC1 DE(bank 0x90) HStart = SC0 DE HStart/2, SC1 DE(bank 0x90) Width = SC0 DE Width/2 367 // 4.temp solution:SC0 DE VStart/Vend should add 6, so is SC1 DE Vstart/Vend 368 #define HW_DESIGN_4K2K_VER (6) 369 370 // version0: Not support TV chip as HDMITx 371 // version1: Maserati + Raptor 372 // version2: Maxim + inside HDMITx 373 #define HW_DESIGN_HDMITX_VER (2) 374 375 #define HDMITX_COLORDEPTH_DEFAULT_FACTOR (100) 376 #define HDMITX_COLORDEPTH_8BIT_FACTOR (100) 377 #define HDMITX_COLORDEPTH_10BIT_FACTOR (125) 378 #define HDMITX_COLORDEPTH_12BIT_FACTOR (150) 379 #define HDMITX_COLORDEPTH_16BIT_FACTOR (200) 380 381 #define HW_DESIGN_3D_VER (3) 382 #define HW_2DTO3D_SUPPORT TRUE 383 #define HW_2DTO3D_VER (4) 384 #define HW_2DTO3D_BYTE_PER_WORD (32) 385 #define HW_2DTO3D_PATCH FALSE //a1 u01:2d to 3d hw bug 386 #define HW_2DTO3D_BLOCK_DR_BUF_SIZE (0x2200) 387 #define HW_2DTO3D_DD_BUF_SIZE (0xFF00) 388 //HW support check board and pixel alternative 389 #define HW_SUPPORT_3D_CB_AND_PA TRUE 390 #define ENABLE_GOP_T3DPATCH 391 #define VALUE_AUTO_TUNE_AREA_TRIG_4K540P (0x0A) //4k0.5k 3D 392 #define VALUE_DISP_AREA_TRIG_4K540P (0x0D) //4k0.5k 3D 393 // maserati use 4 tap scaling in 3D mode. PQ is 6 tap mode. Line buffer is not enough because 12 line mode is disabled in 3D mode. 394 #define HW_6TAP_MODE_SUPPORT FALSE 395 396 //hw support fbl 3d or not. if support,can do SBS to LBL and SBS to SBS 397 #define HW_3D_SUPPORT_FBL TRUE 398 //M10, A2, J2 ,A5,A6,A3,Agate HW will automatic use IPM fetch's reg setting to alignment IPM fetch, so skip sw alignment 399 //and for mirror cbcr swap, need check IPM fetch to decide if need swap 400 #define HW_IPM_FETCH_ALIGNMENT TRUE 401 //hw support 2 line mode deinterlace for interlace or not 402 #define HW_2LINEMODE_DEINTERLACE_SUPPORT FALSE 403 #define HW_CLK_CTRL TRUE 404 #define SUPPORT_OSD_HSLVDS_PATH 1 405 #define MLG_1024 406 407 #define OSD_LAYER_NUM (5) 408 #define VIDEO_OSD_SWITCH_VER (2) 409 410 //#define FA_1920X540_OUTPUT 411 #define XC_SUPPORT_4K2K 1 412 413 // if H/W support 2p mode to achieve 600M HZ 414 #define XC_SUPPORT_2P_MODE TRUE 415 416 //device 1 is interlace out 417 #define XC_DEVICE1_IS_INTERLACE_OUT 0 418 419 //if H/W support force post-Vscalin-down in DS mode 420 #define HW_SUPPORT_FORCE_VSP_IN_DS_MODE TRUE 421 422 //if H/W support LPLL lock freqence not lock phase mode 423 #define HW_SUPPORT_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE TRUE 424 425 // if H/W support interlace output timing 426 #define HW_SUPPORT_INTERLACE_OUTPUT TRUE 427 428 // if H/W support 4k2k_60p output timing 429 #define HW_SUPPORT_4K2K_60P_OUTPUT TRUE 430 431 #define SUPPORT_MOD_ADBANK_SEPARATE 432 433 #define SUPPORT_FPLL_REFER_24MXTAL // Maxim is 2P mode 434 435 //#define SUPPORT_FPLL_REFER_24MXTAL_4P /// 24MXTAL_4P>>24MXTAL 436 437 // for 4K 0.5K 240Hz case, if input only 25fps, ivs:ovs = 5:48 case 438 #define SUPPORT_FPLL_DOUBLE_OVS 439 440 #define SUPPORT_HDMI20 1 441 442 #define LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE 1 443 444 /// for Chip bringup 445 #define ENABLE_CHIP_BRINGUP 446 #define PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB 1 // support pip&pop by multi sc ,such as sc1 support pip&pop 447 448 #define HW_4K2K_VIP_PEAKING_LIMITATION 0 449 #define HW_SCALING_LIMITATION 0 //NO LIMITATION 450 451 // support 3D DS 452 #define SUPPORT_3D_DS 0 453 454 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0) 455 //#define ENABLE_TV_SC2_PQ 456 #endif 457 //#define MONACO_SC2_PATCH 458 459 //#define PATCH_TCON_BRING_UP 460 461 #define XC_SUPPORT_CMA TRUE 462 463 #define XC_CMA_8MB 0x0800000 464 #define XC_CMA_10MB 0x0A00000 465 #define XC_CMA_12MB 0x0C00000 466 #define XC_CMA_15MB 0x0F00000 467 #define XC_CMA_16MB 0x1000000 468 #define XC_CMA_18MB 0x1200000 469 #define XC_CMA_19MB 0x1300000 470 #define XC_CMA_20MB 0x1400000 471 #define XC_CMA_22MB 0x1600000 472 #define XC_CMA_24MB 0x1800000 473 #define XC_CMA_32MB 0x2000000 474 #define XC_CMA_36MB 0x2400000 475 #define XC_CMA_30MB 0x1E00000 476 #define XC_CMA_40MB 0x2800000 477 #define XC_CMA_48MB 0x3000000 478 #define XC_CMA_64MB 0x4000000 479 #define XC_CMA_72MB 0x4800000 480 #define XC_CMA_96MB 0x6000000 481 482 #define XC_4K2K_WIDTH_MAX 4500 483 #define XC_4K2K_WIDTH_MIN 3000 484 #define XC_4K2K_HIGH_MAX 2500 485 #define XC_4K2K_HIGH_MIN 1900 486 487 #define XC_4K1K_WIDTH_MAX 4500 488 #define XC_4K1K_WIDTH_MIN 3000 489 #define XC_4K1K_HIGH_MAX 1300 490 #define XC_4K1K_HIGH_MIN 900 491 492 #define XC_4K_HALFK_WIDTH_MAX 4500 // 4K 0.5K 493 #define XC_4K_HALFK_WIDTH_MIN 3000 // 4K 0.5K 494 #define XC_4K_HALFK_HIGH_MAX 600 // 4K 0.5K 495 #define XC_4K_HALFK_HIGH_MIN 500 // 4K 0.5K 496 497 #define XC_2K2K_WIDTH_MAX 2300 498 #define XC_2K2K_WIDTH_MIN 1500 499 #define XC_2K2K_HIGH_MAX 2500 500 #define XC_2K2K_HIGH_MIN 1900 501 502 #define XC_FHD_WIDTH_MAX 2300 503 #define XC_FHD_WIDTH_MIN 1500 504 #define XC_FHD_HIGH_MAX 1300 505 #define XC_FHD_HIGH_MIN 900 506 507 #define XC_FP1080P_H_SIZE 1920 508 #define XC_FP1080P_V_SIZE 2205 509 510 #define FRC_MEMORY_PROTECT 511 512 #define XC_FRC_IPM_L 0x3F48000 // 4096x2160x1.5x10/2 513 #define XC_FRC_IPM_R 0x3F48000 // 4096x2160x1.5x10/2 514 #define XC_FRC_MEDS_L 0x0BDD800 // 2048x1080x1.125x10/2 515 #define XC_FRC_MEDS_R 0x0BDD800 // 2048x1080x1.125x10/2 516 #define XC_FRC_ME1_X1_READ 0x0002800 // ME1_X1 pre-fetch size 517 #define XC_FRC_ME1_X1 0x0061C00 // 8x136x32x11.5 518 #define XC_FRC_ME1_S1 0x0030E00 // 2x136x32x23 519 #define XC_FRC_ME2_X2 0x02DD200 // 30x272x32x11.5 520 #define XC_FRC_ME2_Y2 0x00C3800 // 8x272x32x11.5 521 #define XC_FRC_ME2_F2 0x01B7E00 // 18x272x32x11.5 522 #define XC_FRC_ME2_LOGO 0x00C3800 // 8x272x32x11.5 523 #define XC_FRC_ME2_S2 0x00C3800 // 8x272x32x11.5 524 #define XC_FRC_HR 0x03FC000 // 40x272x32x12 525 #define XC_FRC_HR_BUF23 0x02FD000 // 30x272x32x12 526 527 528 529 //------------------------------------------------------------------------------------------------- 530 // Register base 531 //------------------------------------------------------------------------------------------------- 532 533 // PM 534 #define REG_DDC_BASE 0x000400UL 535 #define REG_PM_SLP_BASE 0x000E00UL 536 #define REG_PM_GPIO_BASE 0x000F00UL 537 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung 538 #define REG_PAD_SAR_BASE 0x001400UL 539 #define REG_SCDC0_BASE 0x010200UL 540 #define REG_SCDC1_BASE 0x010300UL 541 #define REG_SCDC2_BASE 0x010400UL 542 #define REG_SCDC3_BASE 0x010500UL 543 #define REG_PM_TOP_BASE 0x001E00UL 544 #define REG_MHL_CBUS_BANK 0x001F00UL 545 #define REG_EFUSE_BASE 0x002000UL 546 #define REG_PM_MHL_CBUS_BANK 0x002F00UL 547 548 // NONPM 549 #define REG_MIU0_BASE 0x101200UL 550 #define REG_MIU0_EX_BASE 0x161500UL 551 #define REG_MIU0_ARBB_BASE 0x152000UL 552 #define REG_MIU1_BASE 0x100600UL 553 #define REG_MIU1_EX_BASE 0x162200UL 554 #define REG_MIU1_ARBB_BASE 0x152100UL 555 #define REG_MIU2_BASE 0x162000UL 556 #define REG_MIU2_EX_BASE 0x162300UL 557 #define REG_MIU2_ARBB_BASE 0x152200UL 558 559 #define REG_CLKGEN2_BASE 0x100A00UL 560 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF 561 #define REG_CHIP_BASE 0x101E00UL 562 #define REG_UHC0_BASE 0x102400UL 563 #define REG_UHC1_BASE 0x100D00UL 564 #define REG_ADC_ATOP_BASE 0x102500UL // 0x2500 - 0x25FF 565 #define REG_ADC_DTOP_BASE 0x102600UL // 0x2600 - 0x26EF 566 #define REG_ADC_CHIPTOP_BASE 0x101E00UL // 0x1E00 - 0x1EFF 567 #define REG_HDMI_BASE 0x102700UL // 0x2700 - 0x27FF 568 #define REG_CHIP_GPIO_BASE 0x102B00UL 569 #define REG_ADC_ATOPB_BASE 0x103D00UL // 0x3D00 - 0x3DFF 570 571 #define REG_HDMI2_BASE 0x101A00UL 572 #define REG_IPMUX_BASE 0x102E00UL 573 #define REG_MVOP_BASE 0x101400UL 574 #define REG_SUBMVOP_BASE 0x101300UL 575 576 #if ENABLE_REGISTER_SPREAD 577 #define REG_SCALER_BASE 0x130000UL 578 #else 579 #define REG_SCALER_BASE 0x102F00UL 580 #endif 581 #define REG_LPLL_BASE 0x103100UL 582 #define REG_MOD_BASE 0x103200UL 583 #define REG_PWM_BASE 0x13F400UL 584 #define REG_MOD_A_BASE 0x111E00UL 585 #define REG_AFEC_BASE 0x103500UL 586 #define REG_COMB_BASE 0x103600UL 587 588 #define REG_HDCPKEY_BASE 0x173800UL 589 #define REG_DVI_ATOP_BASE 0x110900UL 590 #define REG_DVI_DTOP_BASE 0x110A00UL 591 #define REG_DVI_EQ_BASE 0x110A80UL // EQ started from 0x80 592 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 593 #define REG_ADC_DTOPB_BASE 0x111200UL // ADC DTOPB 594 #define REG_DVI_ATOP1_BASE 0x113200UL 595 #define REG_DVI_DTOP1_BASE 0x113300UL 596 #define REG_DVI_EQ1_BASE 0x113380UL // EQ started from 0x80 597 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 598 #define REG_DVI_ATOP2_BASE 0x113400UL 599 #define REG_DVI_ATOP3_BASE 0x162F00UL 600 #define REG_DVI_DTOP2_BASE 0x113500UL 601 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 602 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 603 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving 604 #define REG_DVI_PS1_BASE 0x113640UL // DVI power saving1 605 #define REG_DVI_PS2_BASE 0x113680UL // DVI power saving2 606 #define REG_DVI_PS3_BASE 0x1136C0UL // DVI power saving3 607 #define REG_DVI_DTOP3_BASE 0x113700UL 608 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 609 #define REG_HDCP3_BASE 0x1137C0UL // HDCP started from 0xC0 610 611 #define REG_CHIP_ID_MAJOR 0x1ECC 612 #define REG_CHIP_ID_MINOR 0x1ECD 613 #define REG_CHIP_VERSION 0x1ECE 614 #define REG_CHIP_REVISION 0x1ECFUL 615 #define REG_CHIP_GPIO1_BASE 0x110300UL 616 617 #define REG_COMBO_PHY0_P0_BASE 0x170200UL 618 #define REG_COMBO_PHY1_P0_BASE 0x170300UL 619 #define REG_COMBO_PHY0_P1_BASE 0x170400UL 620 #define REG_COMBO_PHY1_P1_BASE 0x170500UL 621 #define REG_COMBO_PHY0_P2_BASE 0x170600UL 622 #define REG_COMBO_PHY1_P2_BASE 0x170700UL 623 #define REG_COMBO_PHY0_P3_BASE 0x170800UL 624 #define REG_COMBO_PHY1_P3_BASE 0x170900UL 625 626 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL 627 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL 628 #define REG_HDCP_DUAL_P0_BASE 0x171200UL 629 #define REG_DVI_DTOP_DUAL_P1_BASE 0x171300UL 630 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL 631 #define REG_HDCP_DUAL_P1_BASE 0x171500UL 632 #define REG_DVI_DTOP_DUAL_P2_BASE 0x171600UL 633 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL 634 #define REG_HDCP_DUAL_P2_BASE 0x171800UL 635 #define REG_DVI_DTOP_DUAL_P3_BASE 0x171900UL 636 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL 637 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL 638 639 #define REG_HDMI_DUAL_0_BASE 0x173000UL 640 #define REG_HDMI2_DUAL_0_BASE 0x173100UL 641 #define REG_HDMI3_DUAL_0_BASE 0x173400UL 642 #define REG_HDMI_DUAL_1_BASE 0x173200UL 643 #define REG_HDMI2_DUAL_1_BASE 0x173300UL 644 #define REG_HDMI3_DUAL_1_BASE 0x173600UL 645 646 #define REG_COMBO_GP_TOP_BASE 0x173900UL 647 #define REG_SECURE_TZPC_BASE 0x173A00UL 648 649 ////////////////////////// FRC using //////////////////////////////// 650 #define REG_CLKGEN0_BASE 0x100B00UL 651 #define REG_CLKGEN1_BASE 0x103300UL 652 653 ///FRC Area 654 #define REG_FSC_BANK_BASE 0x140000UL // FSC 0x102C bank, direct bank is 0x1400 655 #define REG_FRC_BANK_BASE 0x400000UL 656 657 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 658 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 659 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 660 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 661 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x) 662 #define H_CLKGEN2(x) BK_REG_H(REG_CLKGEN2_BASE, x) 663 664 /////////////////////////////////////////////////////////////////// 665 666 // store bank 667 #define LPLL_BK_STORE \ 668 MS_U8 u8Bank; \ 669 u8Bank = MDrv_ReadByte(REG_LPLL_BASE) 670 671 // restore bank 672 #define LPLL_BK_RESTORE MDrv_WriteByte(REG_LPLL_BASE, u8Bank) 673 674 // switch bank 675 #define LPLL_BK_SWITCH(_x_) MDrv_WriteByte(REG_LPLL_BASE, _x_) 676 677 678 //------------------------------------------------------------------------------ 679 // Register configure 680 //------------------------------------------------------------------------------ 681 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out 682 #define CKG_DACA2_GATED BIT(0) 683 #define CKG_DACA2_INVERT BIT(1) 684 #define CKG_DACA2_MASK BMASK(3:2) 685 #define CKG_DACA2_VIF_CLK (0 << 2) 686 #define CKG_DACA2_VD_CLK (1 << 2) 687 #define CKG_DACA2_EXT_TEST_CLK (2 << 2) 688 #define CKG_DACA2_XTAL (3 << 2) 689 690 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out 691 #define CKG_DACB2_GATED BIT(0) 692 #define CKG_DACB2_INVERT BIT(1) 693 #define CKG_DACB2_MASK BMASK(3:2) 694 #define CKG_DACB2_VIF_CLK (0 << 2) 695 #define CKG_DACB2_VD_CLK (1 << 2) 696 #define CKG_DACB2_EXT_TEST_CLK (2 << 2) 697 #define CKG_DACB2_XTAL (3 << 2) 698 699 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L 700 #define CKG_EDCLK_F1_GATED BIT(0) 701 #define CKG_EDCLK_F1_INVERT BIT(1) 702 #define CKG_EDCLK_F1_MASK BMASK(4:2) 703 #define CKG_EDCLK_F1_ADC (0 << 2) 704 #define CKG_EDCLK_F1_DVI (1 << 2) 705 #define CKG_EDCLK_F1_345MHZ (2 << 2) 706 #define CKG_EDCLK_F1_216MHZ (3 << 2) 707 #define CKG_EDCLK_F1_192MHZ (4 << 2) 708 #define CKG_EDCLK_F1_240MHZ (5 << 2) 709 #define CKG_EDCLK_F1_320MHZ (6 << 2) 710 #define CKG_EDCLK_F1_XTAL (7 << 2) 711 712 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L 713 #define CKG_EDCLK_F2_GATED BIT(0) 714 #define CKG_EDCLK_F2_INVERT BIT(1) 715 #define CKG_EDCLK_F2_MASK BMASK(4:2) 716 #define CKG_EDCLK_F2_ADC (0 << 2) 717 #define CKG_EDCLK_F2_DVI (1 << 2) 718 #define CKG_EDCLK_F2_345MHZ (2 << 2) 719 #define CKG_EDCLK_F2_216MHZ (3 << 2) 720 #define CKG_EDCLK_F2_192MHZ (4 << 2) 721 #define CKG_EDCLK_F2_240MHZ (5 << 2) 722 #define CKG_EDCLK_F2_320MHZ (6 << 2) 723 #define CKG_EDCLK_F2_XTAL (7 << 2) 724 725 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) 726 #define CKG_FMCLK_GATED BIT(0) 727 #define CKG_FMCLK_INVERT BIT(1) 728 #define CKG_FMCLK_MASK BMASK(3:2) 729 #define CKG_FMCLK_FCLK (0 << 2) 730 #define CKG_FMCLK_MIU_256 (1 << 2) 731 #define CKG_FMCLK_MIU_128 (2 << 2) 732 733 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) 734 #define CKG_SC_ROT_GATED BIT(0) 735 #define CKG_SC_ROT_INVERT BIT(1) 736 #define CKG_SC_ROT_MASK BMASK(3:2) 737 #define CKG_SC_ROT_MIU_256 (0 << 2) 738 #define CKG_SC_ROT_MIU_128 (1 << 2) 739 740 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 741 #define CKG_FICLK_F1_GATED BIT(0) 742 #define CKG_FICLK_F1_INVERT BIT(1) 743 #define CKG_FICLK_F1_MASK BMASK(3:2) 744 #define CKG_FICLK_F1_IDCLK1 (0 << 2) 745 #define CKG_FICLK_F1_FLK (1 << 2) 746 //#define CKG_FICLK_F1_XTAL (3 << 2) 747 748 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using, not for FLCIK, and should set 0x00 for VE 749 #define CKG_FICLK_F2_GATED BIT(0) 750 #define CKG_FICLK_F2_INVERT BIT(1) 751 #define CKG_FICLK_F2_MASK BMASK(3:2) 752 #define CKG_FICLK_F2_IDCLK2 (0 << 2) 753 #define CKG_FICLK_F2_FLK (0 << 2) 754 //#define CKG_FICLK_F2_XTAL (3 << 2) 755 756 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 757 #define CKG_FICLK2_F2_GATED BIT(4) 758 #define CKG_FICLK2_F2_INVERT BIT(5) 759 #define CKG_FICLK2_F2_MASK BMASK(7:6) 760 #define CKG_FICLK2_F2_IDCLK2 (0 << 6) 761 #define CKG_FICLK2_F2_FCLK (1 << 6) 762 763 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk 764 #define CKG_FCLK_GATED BIT(0) 765 #define CKG_FCLK_INVERT BIT(1) 766 #define CKG_FCLK_MASK BMASK(4:2) 767 #define CKG_FCLK_170MHZ (0 << 2) 768 #define CKG_FCLK_CLK_MIU (1 << 2) 769 #define CKG_FCLK_345MHZ (2 << 2) 770 #define CKG_FCLK_216MHZ (3 << 2) 771 #define CKG_FCLK_192MHZ (4 << 2) 772 #define CKG_FCLK_240MHZ (5 << 2) 773 #define CKG_FCLK_320MHZ (6 << 2) 774 #define CKG_FCLK_XTAL (7 << 2) 775 #define CKG_FCLK_XTAL_ CKG_FCLK_XTAL//(8 << 2) for A5 no XTAL 776 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ 777 778 #define REG_CKG_ODCLK (REG_CLKGEN0_BASE + 0xA6 ) // output dot clock, usually select LPLL, select XTAL when debug 779 #define CKG_ODCLK_GATED BIT(0) 780 #define CKG_ODCLK_INVERT BIT(1) 781 #define CKG_ODCLK_MASK BMASK(5:2) 782 #define CKG_ODCLK_SC_PLL (0 << 2) 783 #define CKG_ODCLK_LPLL_DIV2 (1 << 2) 784 #define CKG_ODCLK_27M (2 << 2) 785 #define CKG_ODCLK_CLK_LPLL (3 << 2) 786 //#define CKG_ODCLK_XTAL (8 << 2) 787 788 #define REG_CKG_IDCLK0 (REG_CLKGEN0_BASE + 0xA8 ) // off-line detect idclk 789 #define CKG_IDCLK0_GATED BIT(0) 790 #define CKG_IDCLK0_INVERT BIT(1) 791 #define CKG_IDCLK0_MASK BMASK(5:2) 792 #define CKG_IDCLK0_CLK_ADC (0 << 2) 793 #define CKG_IDCLK0_CLK_DVI (1 << 2) 794 #define CKG_IDCLK0_CLK_VD (2 << 2) 795 #define CKG_IDCLK0_CLK_DC0 (3 << 2) 796 #define CKG_IDCLK0_ODCLK (4 << 2) 797 #define CKG_IDCLK0_0 (5 << 2) 798 #define CKG_IDCLK0_CLK_VD_ADC (6 << 2) 799 #define CKG_IDCLK0_00 (7 << 2) // same as 5 --> also is 0 800 #define CKG_IDCLK0_XTAL CKG_IDCLK0_ODCLK//(8 << 2) for A5 no XTAL, select as OD 801 802 #define REG_CKG_IDCLK1 (REG_CLKGEN0_BASE + 0xA9 ) // sub main window idclk 803 #define CKG_IDCLK1_GATED BIT(0) 804 #define CKG_IDCLK1_INVERT BIT(1) 805 #define CKG_IDCLK1_MASK BMASK(5:2) 806 #define CKG_IDCLK1_CLK_ADC (0 << 2) 807 #define CKG_IDCLK1_CLK_DVI (1 << 2) 808 #define CKG_IDCLK1_CLK_VD (2 << 2) 809 #define CKG_IDCLK1_CLK_DC0 (3 << 2) 810 #define CKG_IDCLK1_ODCLK (4 << 2) 811 #define CKG_IDCLK1_0 (5 << 2) 812 #define CKG_IDCLK1_CLK_VD_ADC (6 << 2) 813 #define CKG_IDCLK1_00 (7 << 2) // same as 5 --> also is 0 814 #define CKG_IDCLK1_XTAL CKG_IDCLK1_ODCLK//(8 << 2) for A5 no XTAL,select as OD 815 816 #define REG_CKG_PRE_IDCLK1 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 817 #define CKG_PRE_IDCLK1_MASK BMASK(5:3) 818 #define CKG_PRE_IDCLK1_CLK_ADC (0 << 3) 819 #define CKG_PRE_IDCLK1_CLK_DVI (1 << 3) 820 #define CKG_PRE_IDCLK1_CLK_MHL (2 << 3) 821 822 #define REG_CKG_IDCLK2 (REG_CLKGEN0_BASE + 0xAA ) // main window idclk 823 #define CKG_IDCLK2_GATED BIT(0) 824 #define CKG_IDCLK2_INVERT BIT(1) 825 #define CKG_IDCLK2_MASK BMASK(5:2) 826 #define CKG_IDCLK2_CLK_ADC (0 << 2) 827 #define CKG_IDCLK2_CLK_DVI (1 << 2) 828 #define CKG_IDCLK2_CLK_VD (2 << 2) 829 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 830 #define CKG_IDCLK2_CLK_ADC2 (4 << 2) 831 #define CKG_IDCLK2_0 (5 << 2) 832 #define CKG_IDCLK2_00 (6 << 2) 833 #define CKG_IDCLK2_ODCLK (7 << 2) // same as 5 --> also is 0 834 #define CKG_IDCLK2_CLK_SUB_DC0 (8 << 2) 835 #define CKG_IDCLK2_CLK_ADC3 (9 << 2) 836 #define CKG_IDCLK2_ODCLK2 (10 << 2) 837 #define CKG_IDCLK2_CLKMHL (11 << 2) 838 #define CKG_IDCLK2_XTAL CKG_IDCLK2_ODCLK//(8 << 2)no XTAL select as OD 839 840 #define REG_CKG_PRE_IDCLK2 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 841 #define CKG_PRE_IDCLK2_MASK BMASK(8:6) 842 #define CKG_PRE_IDCLK2_CLK_ADC (0 << 6) 843 #define CKG_PRE_IDCLK2_CLK_DVI (1 << 6) 844 #define CKG_PRE_IDCLK2_CLK_MHL (2 << 6) 845 846 #define REG_CKG_IDCLK3 (REG_CLKGEN0_BASE + 0xB2 ) 847 #define CKG_IDCLK3_GATED BIT(0) 848 #define CKG_IDCLK3_INVERT BIT(1) 849 #define CKG_IDCLK3_MASK BMASK(5:2) 850 #define CKG_IDCLK3_CLK_ADC (0 << 2) 851 #define CKG_IDCLK3_CLK_DVI (1 << 2) 852 #define CKG_IDCLK3_CLK_VD (2 << 2) 853 #define CKG_IDCLK3_CLK_DC0 (3 << 2) 854 #define CKG_IDCLK3_ODCLK (4 << 2) 855 #define CKG_IDCLK3_0 (5 << 2) 856 #define CKG_IDCLK3_CLK_VD_ADC (6 << 2) 857 #define CKG_IDCLK3_00 (7 << 2) // same as 5 --> also is 0 858 #define CKG_IDCLK3_XTAL (8 << 2) 859 860 #define REG_CKG_IDCLK_USR_ENA (REG_CLKGEN0_BASE + 0xB4 ) // idclk user enable 861 #define CKG_IDCLK3_USR_ENA BIT(3) 862 863 #define REG_CKG_PRE_IDCLK3 (REG_CLKGEN0_BASE + 0xBC ) 864 #define CKG_PRE_IDCLK3_MASK BMASK(11:9) 865 #define CKG_PRE_IDCLK3_CLK_ADC (0 << 9) 866 #define CKG_PRE_IDCLK3_CLK_DVI (1 << 9) 867 #define CKG_PRE_IDCLK3_CLK_MHL (2 << 9) 868 869 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) 870 #define CKG_PDW0_GATED BIT(0) 871 #define CKG_PDW0_INVERT BIT(1) 872 #define CKG_PDW0_MASK BMASK(4:2) 873 #define CKG_PDW0_CLK_ADC (0 << 2) 874 #define CKG_PDW0_CLK_DVI (1 << 2) 875 #define CKG_PDW0_CLK_VD (2 << 2) 876 #define CKG_PDW0_CLK_DC0 (3 << 2) 877 #define CKG_PDW0_ODCLK (4 << 2) 878 #define CKG_PDW0_0 (5 << 2) 879 #define CKG_PDW0_CLK_VD_ADC (6 << 2) 880 #define CKG_PDW0_00 (7 << 2) // same as 5 --> also is 0 881 #define CKG_PDW0_XTAL (8 << 2) 882 883 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) 884 #define CKG_PDW1_GATED BIT(0) 885 #define CKG_PDW1_INVERT BIT(1) 886 #define CKG_PDW1_MASK BMASK(4:2) 887 #define CKG_PDW1_CLK_ADC (0 << 2) 888 #define CKG_PDW1_CLK_DVI (1 << 2) 889 #define CKG_PDW1_CLK_VD (2 << 2) 890 #define CKG_PDW1_CLK_DC0 (3 << 2) 891 #define CKG_PDW1_ODCLK (4 << 2) 892 #define CKG_PDW1_0 (5 << 2) 893 #define CKG_PDW1_CLK_VD_ADC (6 << 2) 894 #define CKG_PDW1_00 (7 << 2) // same as 5 --> also is 0 895 #define CKG_PDW1_XTAL (8 << 2) 896 897 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) 898 #define CKG_OSDC_GATED BIT(0) 899 #define CKG_OSDC_INVERT BIT(1) 900 #define CKG_OSDC_MASK BMASK(3:2) 901 #define CKG_OSDC_CLK_LPLL_OSD (0 << 2) 902 903 #define REG_DE_ONLY_F3 (REG_CLKGEN0_BASE + 0xA0 ) 904 #define DE_ONLY_F3_MASK BIT(3) 905 906 #define REG_DE_ONLY_F2 (REG_CLKGEN0_BASE + 0xA0 ) 907 #define DE_ONLY_F2_MASK BIT(2) 908 909 #define REG_DE_ONLY_F1 (REG_CLKGEN0_BASE + 0xA0 ) 910 #define DE_ONLY_F1_MASK BIT(1) 911 912 #define REG_DE_ONLY_F0 (REG_CLKGEN0_BASE + 0xA0 ) 913 #define DE_ONLY_F0_MASK BIT(0) 914 915 916 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96) 917 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42) 918 919 #define REG_CLKGEN0_50_L (REG_CLKGEN0_BASE + 0xA0) 920 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) 921 #define REG_CLKGEN0_57_L (REG_CLKGEN0_BASE + 0xAE) 922 923 //MVOP 8bit address 924 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76) 925 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80) 926 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82) 927 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84) 928 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86) 929 #define REG_SUBMVOP_MIRROR (REG_SUBMVOP_BASE + 0x76) 930 #define REG_SUBMVOP_CROP_H_START (REG_SUBMVOP_BASE + 0x80) 931 #define REG_SUBMVOP_CROP_V_START (REG_SUBMVOP_BASE + 0x82) 932 #define REG_SUBMVOP_CROP_H_SIZE (REG_SUBMVOP_BASE + 0x84) 933 #define REG_SUBMVOP_CROP_V_SIZE (REG_SUBMVOP_BASE + 0x86) 934 935 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 ) 936 #define CKG_S2_MECLK_GATED BIT(0) 937 #define CKG_S2_MECLK_INVERT BIT(1) 938 #define CKG_S2_MECLK_MASK BMASK(5:2) 939 940 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 ) 941 #define CKG_S2_MGCLK_GATED BIT(0) 942 #define CKG_S2_MGCLK_INVERT BIT(1) 943 #define CKG_S2_MGCLK_MASK BMASK(5:2) 944 945 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) 946 #define CKG_S2_GOP_HDR_GATED BIT(0) 947 #define CKG_S2_GOP_HDR_INVERT BIT(1) 948 #define CKG_S2_GOP_HDR_MASK BMASK(5:2) 949 #define CKG_S2_GOP_HDR_ODCLK (0 << 2) 950 #define CKG_S2_GOP_HDR_EDCLK (1 << 2) 951 952 //// for SC2, at REG_CLKGEN2_BASE 953 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 ) 954 #define CKG_S2_FICLK_F1_GATED BIT(0) 955 #define CKG_S2_FICLK_F1_INVERT BIT(1) 956 #define CKG_S2_FICLK_F1_MASK BMASK(3:2) 957 #define CKG_S2_FICLK_F1_IDCLK1 (0 << 2) 958 #define CKG_S2_FICLK_F1_FLK (1 << 2) 959 960 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 ) 961 #define CKG_S2_FICLK_F2_GATED BIT(0) 962 #define CKG_S2_FICLK_F2_INVERT BIT(1) 963 #define CKG_S2_FICLK_F2_MASK BMASK(3:2) 964 #define CKG_S2_FICLK_F2_IDCLK2 (0 << 2) 965 #define CKG_S2_FICLK_F2_FLK (1 << 2) 966 967 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) 968 #define CKG_S2_FICLK2_F2_GATED BIT(0) 969 #define CKG_S2_FICLK2_F2_INVERT BIT(1) 970 #define CKG_S2_FICLK2_F2_MASK BMASK(3:2) 971 #define CKG_S2_FICLK2_F2_IDCLK2 (0 << 2) // v prescaling 972 #define CKG_S2_FICLK2_F2_FCLK (1 << 2) // normal 973 #define CKG_S2_FICLK2_F2_MIUCLK (2 << 2) // DIP case 974 975 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk 976 #define CKG_S2_FCLK_GATED BIT(0) 977 #define CKG_S2_FCLK_INVERT BIT(1) 978 #define CKG_S2_FCLK_MASK BMASK(4:2) 979 #define CKG_S2_FCLK_172MHZ (0 << 2) 980 #define CKG_S2_FCLK_CLK_MIU (1 << 2) 981 #define CKG_S2_FCLK_345MHZ (2 << 2) 982 #define CKG_S2_FCLK_216MHZ (3 << 2) 983 #define CKG_S2_FCLK_192MHZ (4 << 2) 984 #define CKG_S2_FCLK_240MHZ (5 << 2) 985 #define CKG_S2_FCLK_320MHZ (6 << 2) 986 #define CKG_S2_FCLK_XTAL (7 << 2) 987 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ 988 989 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 ) 990 #define CKG_S2_FODCLK_GATED BIT(0) 991 #define CKG_S2_FODCLK_INVERT BIT(1) 992 #define CKG_S2_FODCLK_CLK_ODCLK (0 << 2) 993 #define CKG_S2_FODCLK_CLK_MIU (1 << 2) 994 995 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 ) 996 #define CKG_S2_ODCLK_GATED BIT(0) 997 #define CKG_S2_ODCLK_INVERT BIT(1) 998 #define CKG_S2_ODCLK_MASK BMASK(3:2) 999 #define CKG_S2_ODCLK_SYN_CLK (0 << 2) 1000 #define CKG_S2_ODCLK_LPLL_DIV2 (1 << 2) 1001 #define CKG_S2_ODCLK_27M (2 << 2) 1002 #define CKG_S2_ODCLK_CLK_LPLL (3 << 2) 1003 1004 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk 1005 #define CKG_S2_IDCLK0_GATED BIT(0) 1006 #define CKG_S2_IDCLK0_INVERT BIT(1) 1007 #define CKG_S2_IDCLK0_MASK BMASK(5:2) 1008 #define CKG_S2_IDCLK0_CLK_ADC (0 << 2) 1009 #define CKG_S2_IDCLK0_CLK_DVI (1 << 2) 1010 #define CKG_S2_IDCLK0_CLK_VD (2 << 2) 1011 #define CKG_S2_IDCLK0_CLK_DC0 (3 << 2) 1012 #define CKG_S2_IDCLK0_CLK_ADC2 (4 << 2) 1013 #define CKG_S2_IDCLK0_0 (5 << 2) 1014 #define CKG_S2_IDCLK0_00 (6 << 2) 1015 #define CKG_S2_IDCLK0_ODCLK (7 << 2) 1016 #define CKG_S2_IDCLK0_CLK_SUB_DC0 (8 << 2) 1017 #define CKG_S2_IDCLK0_CLK_ADC3 (9 << 2) 1018 #define CKG_S2_IDCLK0_ODCLK2 (10<< 2) 1019 #define CKG_S2_IDCLK0_MHL (13<< 2) 1020 #define CKG_S2_IDCLK0_XTAL CKG_S2_IDCLK0_ODCLK 1021 1022 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk 1023 #define CKG_S2_IDCLK1_GATED BIT(0) 1024 #define CKG_S2_IDCLK1_INVERT BIT(1) 1025 #define CKG_S2_IDCLK1_MASK BMASK(5:2) 1026 #define CKG_S2_IDCLK1_CLK_ADC (0 << 2) 1027 #define CKG_S2_IDCLK1_CLK_DVI (1 << 2) 1028 #define CKG_S2_IDCLK1_CLK_VD (2 << 2) 1029 #define CKG_S2_IDCLK1_CLK_DC0 (3 << 2) 1030 #define CKG_S2_IDCLK1_CLK_ADC2 (4 << 2) 1031 #define CKG_S2_IDCLK1_0 (5 << 2) 1032 #define CKG_S2_IDCLK1_00 (6 << 2) 1033 #define CKG_S2_IDCLK1_ODCLK (7 << 2) 1034 #define CKG_S2_IDCLK1_CLK_SUB_DC0 (8 << 2) 1035 #define CKG_S2_IDCLK1_CLK_ADC3 (9 << 2) 1036 #define CKG_S2_IDCLK1_ODCLK2 (10<< 2) 1037 #define CKG_S2_IDCLK1_MHL (13<< 2) 1038 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK 1039 1040 #define REG_CKG_S2_IDCLK2 (REG_CLKGEN2_BASE + 0xCA ) // off-line detect idclk 1041 #define CKG_S2_IDCLK2_GATED BIT(0) 1042 #define CKG_S2_IDCLK2_INVERT BIT(1) 1043 #define CKG_S2_IDCLK2_MASK BMASK(5:2) 1044 #define CKG_S2_IDCLK2_CLK_ADC (0 << 2) 1045 #define CKG_S2_IDCLK2_CLK_DVI (1 << 2) 1046 #define CKG_S2_IDCLK2_CLK_VD (2 << 2) 1047 #define CKG_S2_IDCLK2_CLK_DC0 (3 << 2) 1048 #define CKG_S2_IDCLK2_CLK_ADC2 (4 << 2) 1049 #define CKG_S2_IDCLK2_0 (5 << 2) 1050 #define CKG_S2_IDCLK2_00 (6 << 2) 1051 #define CKG_S2_IDCLK2_ODCLK (7 << 2) 1052 #define CKG_S2_IDCLK2_CLK_SUB_DC0 (8 << 2) 1053 #define CKG_S2_IDCLK2_CLK_ADC3 (9 << 2) 1054 #define CKG_S2_IDCLK2_ODCLK2 (10<< 2) 1055 #define CKG_S2_IDCLK2_MHL (13<< 2) 1056 #define CKG_S2_IDCLK2_XTAL CKG_S2_IDCLK2_ODCLK 1057 1058 #define REG_CKG_S2_IDCLK3 (REG_CLKGEN2_BASE + 0xD2 ) // off-line detect idclk 1059 #define CKG_S2_IDCLK3_ATED BIT(0) 1060 #define CKG_S2_IDCLK3_INVERT BIT(1) 1061 #define CKG_S2_IDCLK3_MASK BMASK(5:2) 1062 #define CKG_S2_IDCLK3_CLK_ADC (0 << 2) 1063 #define CKG_S2_IDCLK3_CLK_DVI (1 << 2) 1064 #define CKG_S2_IDCLK3_CLK_VD (2 << 2) 1065 #define CKG_S2_IDCLK3_CLK_DC0 (3 << 2) 1066 #define CKG_S2_IDCLK3_CLK_ADC2 (4 << 2) 1067 #define CKG_S2_IDCLK3_0 (5 << 2) 1068 #define CKG_S2_IDCLK3_00 (6 << 2) 1069 #define CKG_S2_IDCLK3_ODCLK (7 << 2) 1070 #define CKG_S2_IDCLK3_CLK_SUB_DC0 (8 << 2) 1071 #define CKG_S2_IDCLK3_CLK_ADC3 (9 << 2) 1072 #define CKG_S2_IDCLK3_ODCLK2 (10<< 2) 1073 #define CKG_S2_IDCLK3_MHL (13<< 2) 1074 #define CKG_S2_IDCLK3_XTAL CKG_S2_IDCLK3_ODCLK 1075 1076 1077 #define REG_S2_DE_ONLY_F3 (REG_CLKGEN2_BASE + 0xC0 ) 1078 #define S2_DE_ONLY_F3_MASK BIT(3) 1079 1080 #define REG_S2_DE_ONLY_F2 (REG_CLKGEN2_BASE + 0xC0 ) 1081 #define S2_DE_ONLY_F2_MASK BIT(2) 1082 1083 #define REG_S2_DE_ONLY_F1 (REG_CLKGEN2_BASE + 0xC0 ) 1084 #define S2_DE_ONLY_F1_MASK BIT(1) 1085 1086 #define REG_S2_DE_ONLY_F0 (REG_CLKGEN2_BASE + 0xC0 ) 1087 #define S2_DE_ONLY_F0_MASK BIT(0) 1088 1089 //// 1090 #define CLK_SRC_IDCLK2 0 1091 #define CLK_SRC_FCLK 1 1092 #define CLK_SRC_XTAL 3 1093 1094 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46) 1095 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66) 1096 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86) 1097 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6) 1098 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06) 1099 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26) 1100 #define MIU0_G6_REQUEST_MASK (REG_MIU0_ARBB_BASE + 0x06) 1101 1102 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46) 1103 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66) 1104 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86) 1105 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6) 1106 #define MIU1_G4_REQUEST_MASK (REG_MIU1_EX_BASE + 0x06) 1107 #define MIU1_G5_REQUEST_MASK (REG_MIU1_EX_BASE + 0x26) 1108 #define MIU1_G6_REQUEST_MASK (REG_MIU1_ARBB_BASE + 0x06) 1109 1110 #define MIU_SC_G0REQUEST_MASK (0x0000) 1111 #define MIU_SC_G1REQUEST_MASK (0x0000) 1112 #define MIU_SC_G2REQUEST_MASK (0x0000) 1113 #define MIU_SC_G3REQUEST_MASK (0x0000) 1114 #define MIU_SC_G4REQUEST_MASK (0x0000) 1115 #define MIU_SC_G5REQUEST_MASK (0x0000) 1116 #define MIU_SC_G6REQUEST_MASK (0xF603) 1117 1118 ////////////////////////// FRC using //////////////////////////////// 1119 1120 #define MIU_FRC_G0REQUEST_MASK (0x0000) 1121 #define MIU_FRC_G1REQUEST_MASK (0x0000) 1122 #define MIU_FRC_G2REQUEST_MASK (0x0000) 1123 #define MIU_FRC_G3REQUEST_MASK (0x0000) 1124 #define MIU_FRC_G4REQUEST_MASK (0x0000) 1125 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) 1126 #define MIU_FRC_G6REQUEST_MASK (0x0000) 1127 1128 1129 1130 /////////////////////////////////////////////////////////////////// 1131 1132 #define IP_DE_HSTART_MASK (0x1FFF) //BK_01_13 BK_03_13 1133 #define IP_DE_HEND_MASK (0x1FFF) //BK_01_15 BK_03_15 1134 #define IP_DE_VSTART_MASK (0x1FFF) //BK_01_12 BK_03_12 1135 #define IP_DE_VEND_MASK (0x1FFF) //BK_01_14 BK_03_14 1136 1137 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 1138 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 1139 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 1140 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 1141 1142 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 1143 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 1144 1145 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 1146 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 1147 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 1148 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 1149 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 1150 1151 1152 #define HW_DESIGN_LD_VER (2) 1153 1154 #define FPLL_THRESH_MODE_SUPPORT 0 1155 1156 #define ADC_EFUSE_IN_MBOOT 1157 1158 #define ADC_CENTER_GAIN 0x1000 1159 #define ADC_CENTER_OFFSET 0x0800 1160 #define ADC_GAIN_BIT_CNT 14 1161 #define ADC_OFFSET_BIT_CNT 13 1162 1163 #define ADC_VGA_DEFAULT_GAIN_R 0x1000 1164 #define ADC_VGA_DEFAULT_GAIN_G 0x1000 1165 #define ADC_VGA_DEFAULT_GAIN_B 0x1000 1166 #define ADC_VGA_DEFAULT_OFFSET_R 0x0000 1167 #define ADC_VGA_DEFAULT_OFFSET_G 0x0000 1168 #define ADC_VGA_DEFAULT_OFFSET_B 0x0000 1169 #define ADC_YPBPR_DEFAULT_GAIN_R 0x1212 1170 #define ADC_YPBPR_DEFAULT_GAIN_G 0x11AA 1171 #define ADC_YPBPR_DEFAULT_GAIN_B 0x1212 1172 #define ADC_YPBPR_DEFAULT_OFFSET_R 0x0800 1173 #define ADC_YPBPR_DEFAULT_OFFSET_G 0x0100 1174 #define ADC_YPBPR_DEFAULT_OFFSET_B 0x0800 1175 #define ADC_SCART_DEFAULT_GAIN_R 0x1000 1176 #define ADC_SCART_DEFAULT_GAIN_G 0x1000 1177 #define ADC_SCART_DEFAULT_GAIN_B 0x1000 1178 #define ADC_SCART_DEFAULT_OFFSET_R 0x0100 1179 #define ADC_SCART_DEFAULT_OFFSET_G 0x0100 1180 #define ADC_SCART_DEFAULT_OFFSET_B 0x0100 1181 1182 /////////////////////////////////////////////// 1183 // Enable Hardware auto gain/offset 1184 #define ADC_HARDWARE_AUTOOFFSET_RGB ENABLE 1185 #define ADC_HARDWARE_AUTOOFFSET_YPBPR ENABLE 1186 #define ADC_HARDWARE_AUTOOFFSET_SCARTRGB ENABLE 1187 #define ADC_HARDWARE_AUTOGAIN_SUPPORTED ENABLE 1188 #define ADC_VGA_FIXED_GAIN_R 0x1796 1189 #define ADC_VGA_FIXED_GAIN_G 0x1796 1190 #define ADC_VGA_FIXED_GAIN_B 0x1796 1191 #define ADC_VGA_FIXED_OFFSET_R 0x0000 1192 #define ADC_VGA_FIXED_OFFSET_G 0x0000 1193 #define ADC_VGA_FIXED_OFFSET_B 0x0000 1194 #define ADC_YPBPR_FIXED_GAIN_R 0x14B7 1195 #define ADC_YPBPR_FIXED_GAIN_G 0x1441 1196 #define ADC_YPBPR_FIXED_GAIN_B 0x14B7 1197 #define ADC_YPBPR_FIXED_OFFSET_R 0x0800 1198 #define ADC_YPBPR_FIXED_OFFSET_G 0x0100 1199 #define ADC_YPBPR_FIXED_OFFSET_B 0x0800 1200 #define ADC_SCART_FIXED_GAIN_R 0x1796 1201 #define ADC_SCART_FIXED_GAIN_G 0x1796 1202 #define ADC_SCART_FIXED_GAIN_B 0x1796 1203 #define ADC_SCART_FIXED_OFFSET_R 0x0000 1204 #define ADC_SCART_FIXED_OFFSET_G 0x0000 1205 #define ADC_SCART_FIXED_OFFSET_B 0x0000 1206 1207 // patch for china player 1208 // there are some undefined signal between sync and DE in YPbPr fullHD 1209 // so we ignore this signal with coast window 1210 //#define ADC_BYPASS_YPBPR_MACRO_VISION_PATCH 1211 1212 #define SUPPORT_SC0_SUB_WIN FALSE 1213 #define SUPPORT_DUAL_MIU_MIRROR_SWAP_IPM TRUE 1214 1215 1216 // GOP need this define, MI system would call MDrv_SC_SetOSDBlendingFormula before XC init 1217 // determinated dual op by panel type would be failed. 1218 #define GOP_SUPPORT_DUALRATE 1219 1220 1221 // IP Authorization number for dolby 1222 #define IPAUTH_DOLBY_HDR_PIN 118 1223 1224 #endif /* MHAL_XC_CONFIG_H */ 1225 1226