1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef HALMAC_POWER_SEQUENCE_CMD 3 #define HALMAC_POWER_SEQUENCE_CMD 4 5 #include "halmac_2_platform.h" 6 #include "halmac_type.h" 7 8 #define HALMAC_POLLING_READY_TIMEOUT_COUNT 10000 9 10 /* 11 * The value of cmd : 4 bits 12 */ 13 14 /* 15 * offset : the read register offset 16 * msk : the mask of the read value 17 * value : N/A, left by 0 18 * Note : dirver shall implement this function by read & msk 19 */ 20 #define HALMAC_PWR_CMD_READ 0x00 21 /* 22 * offset: the read register offset 23 * msk: the mask of the write bits 24 * value: write value 25 * Note: driver shall implement this cmd by read & msk after write 26 */ 27 #define HALMAC_PWR_CMD_WRITE 0x01 28 /* 29 * offset: the read register offset 30 * msk: the mask of the polled value 31 * value: the value to be polled, masked by the msd field. 32 * Note: driver shall implement this cmd by 33 * do{ 34 * if( (Read(offset) & msk) == (value & msk) ) 35 * break; 36 * } while(not timeout); 37 */ 38 #define HALMAC_PWR_CMD_POLLING 0x02 39 /* 40 * offset: the value to delay 41 * msk: N/A 42 * value: the unit of delay, 0: us, 1: ms 43 */ 44 #define HALMAC_PWR_CMD_DELAY 0x03 45 /* 46 * offset: N/A 47 * msk: N/A 48 * value: N/A 49 */ 50 #define HALMAC_PWR_CMD_END 0x04 51 52 /* 53 * The value of base : 4 bits 54 */ 55 56 /* define the base address of each block */ 57 #define HALMAC_PWR_BASEADDR_MAC 0x00 58 #define HALMAC_PWR_BASEADDR_USB 0x01 59 #define HALMAC_PWR_BASEADDR_PCIE 0x02 60 #define HALMAC_PWR_BASEADDR_SDIO 0x03 61 62 /* 63 * The value of interface_msk : 4 bits 64 */ 65 #define HALMAC_PWR_INTF_SDIO_MSK BIT(0) 66 #define HALMAC_PWR_INTF_USB_MSK BIT(1) 67 #define HALMAC_PWR_INTF_PCI_MSK BIT(2) 68 #define HALMAC_PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 69 70 /* 71 * The value of fab_msk : 4 bits 72 */ 73 #define HALMAC_PWR_FAB_TSMC_MSK BIT(0) 74 #define HALMAC_PWR_FAB_UMC_MSK BIT(1) 75 #define HALMAC_PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 76 77 /* 78 * The value of cut_msk : 8 bits 79 */ 80 #define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0) 81 #define HALMAC_PWR_CUT_A_MSK BIT(1) 82 #define HALMAC_PWR_CUT_B_MSK BIT(2) 83 #define HALMAC_PWR_CUT_C_MSK BIT(3) 84 #define HALMAC_PWR_CUT_D_MSK BIT(4) 85 #define HALMAC_PWR_CUT_E_MSK BIT(5) 86 #define HALMAC_PWR_CUT_F_MSK BIT(6) 87 #define HALMAC_PWR_CUT_G_MSK BIT(7) 88 #define HALMAC_PWR_CUT_ALL_MSK 0xFF 89 90 typedef enum _HALMAC_PWRSEQ_CMD_DELAY_UNIT_ { 91 HALMAC_PWRSEQ_DELAY_US, 92 HALMAC_PWRSEQ_DELAY_MS, 93 } HALMAC_PWRSEQ_DELAY_UNIT; 94 95 /* Don't care endian issue, because element of pwer seq vector is fixed address */ 96 typedef struct _HALMAC_WL_PWR_CFG_ { 97 u16 offset; 98 u8 cut_msk; 99 u8 fab_msk:4; 100 u8 interface_msk:4; 101 u8 base:4; 102 u8 cmd:4; 103 u8 msk; 104 u8 value; 105 } HALMAC_WLAN_PWR_CFG, *PHALMAC_WLAN_PWR_CFG; 106 107 #endif 108