1 /*
2 * SPDX-License-Identifier: GPL-2.0+
3 *
4 * (C) Copyright 2024 Rockchip Electronics Co., Ltd
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <dwc3-uboot.h>
10 #include <usb.h>
11
12 DECLARE_GLOBAL_DATA_PTR;
13
14 #define PERI_CRU_BASE 0x20000000
15 #define PERICRU_PERISOFTRST_CON06 0x0a18
16 #define GRF_SYS_BASE 0x20150000
17 #define GRF_SYS_USBPHY_CON0 0x0050
18 #define GRF_SYS_USBPHY_CON2 0x0058
19
20 #ifdef CONFIG_USB_DWC3
21 static struct dwc3_device dwc3_device_data = {
22 .maximum_speed = USB_SPEED_HIGH,
23 .base = 0x20b00000,
24 .dr_mode = USB_DR_MODE_PERIPHERAL,
25 .index = 0,
26 .dis_u2_susphy_quirk = 1,
27 .usb2_phyif_utmi_width = 16,
28 };
29
usb_gadget_handle_interrupts(void)30 int usb_gadget_handle_interrupts(void)
31 {
32 dwc3_uboot_handle_interrupt(0);
33 return 0;
34 }
35
usb_reset_otg_controller(void)36 static void usb_reset_otg_controller(void)
37 {
38 writel(0x02000200, PERI_CRU_BASE + PERICRU_PERISOFTRST_CON06);
39 mdelay(1);
40 writel(0x02000000, PERI_CRU_BASE + PERICRU_PERISOFTRST_CON06);
41 mdelay(1);
42 }
43
board_usb_init(int index,enum usb_init_type init)44 int board_usb_init(int index, enum usb_init_type init)
45 {
46 usb_reset_otg_controller();
47
48 /* Resume usb2 phy to normal mode */
49 writel(0x01ff0000, GRF_SYS_BASE + GRF_SYS_USBPHY_CON0);
50
51 /* Select usb utmi bvalid from grf and set bvalid high */
52 writel(0xc000c000, GRF_SYS_BASE + GRF_SYS_USBPHY_CON2);
53
54 return dwc3_uboot_init(&dwc3_device_data);
55 }
56 #endif
57