1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H 9 10 /* pll clocks */ 11 #define PLL_GPLL 1 12 #define PLL_CPLL 2 13 #define PLL_AUPLL 3 14 #define ARMCLK 4 15 #define SCLK_DDR 5 16 17 /* clk (clocks) */ 18 #define CLK_CPLL_DIV20 8 19 #define CLK_CPLL_DIV10 9 20 #define CLK_CPLL_DIV8 10 21 #define CLK_GPLL_DIV8 11 22 #define CLK_GPLL_DIV6 12 23 #define CLK_GPLL_DIV4 13 24 #define CLK_CPLL_DIV3 14 25 #define CLK_GPLL_DIV3 15 26 #define CLK_CPLL_DIV2 16 27 #define CLK_GPLL_DIV2 17 28 #define CLK_CM_FRAC0 18 29 #define CLK_CM_FRAC1 19 30 #define CLK_CM_FRAC2 20 31 #define CLK_UART_FRAC0 21 32 #define CLK_UART_FRAC1 22 33 #define CLK_AUDIO_FRAC0 23 34 #define CLK_AUDIO_FRAC1 24 35 #define CLK_AUDIO_INT0 25 36 #define CLK_AUDIO_INT1 26 37 #define SCLK_UART0_SRC 27 38 #define SCLK_UART1 28 39 #define SCLK_UART2 29 40 #define SCLK_UART3 30 41 #define SCLK_UART4 31 42 #define SCLK_UART5 32 43 #define SCLK_UART6 33 44 #define SCLK_UART7 34 45 #define MCLK_SAI0 35 46 #define MCLK_SAI1 36 47 #define MCLK_SAI2 37 48 #define MCLK_PDM 38 49 #define CLKOUT_PDM 39 50 #define MCLK_ASRC0 40 51 #define MCLK_ASRC1 41 52 #define MCLK_ASRC2 42 53 #define MCLK_ASRC3 43 54 #define CLK_ASRC0 44 55 #define CLK_ASRC1 45 56 #define CLK_CORE_PLL 46 57 #define CLK_NPU_PLL 47 58 #define CLK_VEPU_PLL 48 59 #define CLK_ISP_PLL 49 60 #define CLK_AISP_PLL 50 61 #define CLK_SARADC0_SRC 51 62 #define CLK_SARADC1_SRC 52 63 #define CLK_SARADC2_SRC 53 64 #define HCLK_NPU_ROOT 54 65 #define PCLK_NPU_ROOT 55 66 #define ACLK_VEPU_ROOT 56 67 #define HCLK_VEPU_ROOT 57 68 #define PCLK_VEPU_ROOT 58 69 #define CLK_CORE_RGA_SRC 59 70 #define ACLK_GMAC_ROOT 60 71 #define ACLK_VI_ROOT 61 72 #define HCLK_VI_ROOT 62 73 #define PCLK_VI_ROOT 63 74 #define DCLK_VICAP_ROOT 64 75 #define CLK_SYS_DSMC_ROOT 65 76 #define ACLK_VDO_ROOT 66 77 #define ACLK_RKVDEC_ROOT 67 78 #define HCLK_VDO_ROOT 68 79 #define PCLK_VDO_ROOT 69 80 #define DCLK_OOC_SRC 70 81 #define DCLK_VOP 71 82 #define DCLK_DECOM_SRC 72 83 #define PCLK_DDR_ROOT 73 84 #define ACLK_SYSMEM_SRC 74 85 #define ACLK_TOP_ROOT 75 86 #define ACLK_BUS_ROOT 76 87 #define HCLK_BUS_ROOT 77 88 #define PCLK_BUS_ROOT 78 89 #define CCLK_SDMMC0 79 90 #define CCLK_SDMMC1 80 91 #define CCLK_EMMC 81 92 #define SCLK_2X_FSPI0 82 93 #define CLK_GMAC_PTP_REF_SRC 83 94 #define CLK_GMAC_125M 84 95 #define CLK_TIMER_ROOT 85 96 #define TCLK_WDT_NS_SRC 86 97 #define TCLK_WDT_S_SRC 87 98 #define TCLK_WDT_HPMCU 88 99 #define CLK_CAN0 89 100 #define CLK_CAN1 90 101 #define PCLK_PERI_ROOT 91 102 #define ACLK_PERI_ROOT 92 103 #define CLK_I2C_BUS_SRC 93 104 #define CLK_SPI0 94 105 #define CLK_SPI1 95 106 #define BUSCLK_PMU_SRC 96 107 #define CLK_PWM0 97 108 #define CLK_PWM2 98 109 #define CLK_PWM3 99 110 #define CLK_PKA_RKCE_SRC 100 111 #define ACLK_RKCE_SRC 101 112 #define ACLK_VCP_ROOT 102 113 #define HCLK_VCP_ROOT 103 114 #define PCLK_VCP_ROOT 104 115 #define CLK_CORE_FEC_SRC 105 116 #define CLK_CORE_AVSP_SRC 106 117 #define CLK_50M_GMAC_IOBUF_VI 107 118 #define PCLK_TOP_ROOT 108 119 #define CLK_MIPI0_OUT2IO 109 120 #define CLK_MIPI1_OUT2IO 110 121 #define CLK_MIPI2_OUT2IO 111 122 #define CLK_MIPI3_OUT2IO 112 123 #define CLK_CIF_OUT2IO 113 124 #define CLK_MAC_OUT2IO 114 125 #define MCLK_SAI0_OUT2IO 115 126 #define MCLK_SAI1_OUT2IO 116 127 #define MCLK_SAI2_OUT2IO 117 128 #define CLK_CM_FRAC0_SRC 118 129 #define CLK_CM_FRAC1_SRC 119 130 #define CLK_CM_FRAC2_SRC 120 131 #define CLK_UART_FRAC0_SRC 121 132 #define CLK_UART_FRAC1_SRC 122 133 #define CLK_AUDIO_FRAC0_SRC 123 134 #define CLK_AUDIO_FRAC1_SRC 124 135 #define ACLK_NPU_ROOT 125 136 #define HCLK_RKNN 126 137 #define ACLK_RKNN 127 138 #define PCLK_GPIO3 128 139 #define DBCLK_GPIO3 129 140 #define PCLK_IOC_VCCIO3 130 141 #define PCLK_SARADC0 131 142 #define CLK_SARADC0 132 143 #define HCLK_SDMMC1 133 144 #define HCLK_VEPU 134 145 #define ACLK_VEPU 135 146 #define CLK_CORE_VEPU 136 147 #define HCLK_FEC 137 148 #define ACLK_FEC 138 149 #define CLK_CORE_FEC 139 150 #define HCLK_AVSP 140 151 #define ACLK_AVSP 141 152 #define BUSCLK_PMU1_ROOT 142 153 #define HCLK_AISP 143 154 #define ACLK_AISP 144 155 #define CLK_CORE_AISP 145 156 #define CLK_CORE_ISP_ROOT 146 157 #define PCLK_DSMC 147 158 #define ACLK_DSMC 148 159 #define HCLK_CAN0 149 160 #define HCLK_CAN1 150 161 #define PCLK_GPIO2 151 162 #define DBCLK_GPIO2 152 163 #define PCLK_GPIO4 153 164 #define DBCLK_GPIO4 154 165 #define PCLK_GPIO5 155 166 #define DBCLK_GPIO5 156 167 #define PCLK_GPIO6 157 168 #define DBCLK_GPIO6 158 169 #define PCLK_GPIO7 159 170 #define DBCLK_GPIO7 160 171 #define PCLK_IOC_VCCIO2 161 172 #define PCLK_IOC_VCCIO4 162 173 #define PCLK_IOC_VCCIO5 163 174 #define PCLK_IOC_VCCIO6 164 175 #define PCLK_IOC_VCCIO7 165 176 #define HCLK_ISP 166 177 #define ACLK_ISP 167 178 #define CLK_CORE_ISP 168 179 #define HCLK_VICAP 169 180 #define ACLK_VICAP 170 181 #define DCLK_VICAP 171 182 #define ISP0CLK_VICAP 172 183 #define HCLK_VPSS 173 184 #define ACLK_VPSS 174 185 #define CLK_CORE_VPSS 175 186 #define PCLK_CSI2HOST0 176 187 #define DCLK_CSI2HOST0 177 188 #define PCLK_CSI2HOST1 178 189 #define DCLK_CSI2HOST1 179 190 #define PCLK_CSI2HOST2 180 191 #define DCLK_CSI2HOST2 181 192 #define PCLK_CSI2HOST3 182 193 #define DCLK_CSI2HOST3 183 194 #define HCLK_SDMMC0 184 195 #define ACLK_GMAC 185 196 #define PCLK_GMAC 186 197 #define CLK_GMAC_PTP_REF 187 198 #define PCLK_CSIPHY0 188 199 #define PCLK_CSIPHY1 189 200 #define PCLK_MACPHY 190 201 #define PCLK_SARADC1 191 202 #define CLK_SARADC1 192 203 #define PCLK_SARADC2 193 204 #define CLK_SARADC2 194 205 #define ACLK_RKVDEC 195 206 #define HCLK_RKVDEC 196 207 #define CLK_HEVC_CA_RKVDEC 197 208 #define ACLK_VOP 198 209 #define HCLK_VOP 199 210 #define HCLK_RKJPEG 200 211 #define ACLK_RKJPEG 201 212 #define ACLK_RKMMU_DECOM 202 213 #define HCLK_RKMMU_DECOM 203 214 #define DCLK_DECOM 204 215 #define ACLK_DECOM 205 216 #define PCLK_DECOM 206 217 #define PCLK_MIPI_DSI 207 218 #define PCLK_DSIPHY 208 219 #define ACLK_OOC 209 220 #define ACLK_SYSMEM 210 221 #define PCLK_DDRC 211 222 #define PCLK_DDRMON 212 223 #define CLK_TIMER_DDRMON 213 224 #define PCLK_DFICTRL 214 225 #define PCLK_DDRPHY 215 226 #define PCLK_DMA2DDR 216 227 #define CLK_RCOSC_SRC 217 228 #define BUSCLK_PMU_MUX 218 229 #define BUSCLK_PMU_ROOT 219 230 #define PCLK_PMU 220 231 #define CLK_XIN_RC_DIV 221 232 #define CLK_32K 222 233 #define PCLK_PMU_GPIO0 223 234 #define DBCLK_PMU_GPIO0 224 235 #define PCLK_PMU_HP_TIMER 225 236 #define CLK_PMU_HP_TIMER 226 237 #define CLK_PMU_32K_HP_TIMER 227 238 #define PCLK_PWM1 228 239 #define CLK_PWM1 229 240 #define CLK_OSC_PWM1 230 241 #define CLK_RC_PWM1 231 242 #define CLK_FREQ_PWM1 232 243 #define CLK_COUNTER_PWM1 233 244 #define PCLK_I2C2 234 245 #define CLK_I2C2 235 246 #define PCLK_UART0 236 247 #define SCLK_UART0 237 248 #define PCLK_RCOSC_CTRL 238 249 #define CLK_OSC_RCOSC_CTRL 239 250 #define CLK_REF_RCOSC_CTRL 240 251 #define PCLK_IOC_PMUIO0 241 252 #define CLK_REFOUT 242 253 #define CLK_PREROLL 243 254 #define CLK_PREROLL_32K 244 255 #define HCLK_PMU_SRAM 245 256 #define PCLK_WDT_LPMCU 246 257 #define TCLK_WDT_LPMCU 247 258 #define CLK_LPMCU 248 259 #define CLK_LPMCU_RTC 249 260 #define PCLK_LPMCU_MAILBOX 250 261 #define HCLK_OOC 251 262 #define PCLK_SPI2AHB 252 263 #define HCLK_SPI2AHB 253 264 #define HCLK_FSPI1 254 265 #define HCLK_XIP_FSPI1 255 266 #define SCLK_1X_FSPI1 256 267 #define PCLK_IOC_PMUIO1 257 268 #define PCLK_AUDIO_ADC_PMU 258 269 #define MCLK_AUDIO_ADC_PMU 259 270 #define MCLK_AUDIO_ADC_DIV4_PMU 260 271 #define MCLK_LPSAI 261 272 #define ACLK_GIC400 262 273 #define PCLK_WDT_NS 263 274 #define TCLK_WDT_NS 264 275 #define PCLK_WDT_HPMCU 265 276 #define HCLK_CACHE 266 277 #define PCLK_HPMCU_MAILBOX 267 278 #define PCLK_HPMCU_INTMUX 268 279 #define CLK_HPMCU 269 280 #define CLK_HPMCU_RTC 270 281 #define PCLK_RKDMA 271 282 #define ACLK_RKDMA 272 283 #define PCLK_DCF 273 284 #define ACLK_DCF 274 285 #define HCLK_RGA 275 286 #define ACLK_RGA 276 287 #define CLK_CORE_RGA 277 288 #define PCLK_TIMER 278 289 #define CLK_TIMER0 279 290 #define CLK_TIMER1 280 291 #define CLK_TIMER2 281 292 #define CLK_TIMER3 282 293 #define CLK_TIMER4 283 294 #define CLK_TIMER5 284 295 #define PCLK_I2C0 285 296 #define CLK_I2C0 286 297 #define PCLK_I2C1 287 298 #define CLK_I2C1 288 299 #define PCLK_I2C3 289 300 #define CLK_I2C3 290 301 #define PCLK_I2C4 291 302 #define CLK_I2C4 292 303 #define PCLK_I2C5 293 304 #define CLK_I2C5 294 305 #define PCLK_SPI0 295 306 #define PCLK_SPI1 296 307 #define PCLK_PWM0 297 308 #define CLK_OSC_PWM0 298 309 #define CLK_RC_PWM0 299 310 #define PCLK_PWM2 300 311 #define CLK_OSC_PWM2 301 312 #define CLK_RC_PWM2 302 313 #define PCLK_PWM3 303 314 #define CLK_OSC_PWM3 304 315 #define CLK_RC_PWM3 305 316 #define PCLK_UART1 306 317 #define PCLK_UART2 307 318 #define PCLK_UART3 308 319 #define PCLK_UART4 309 320 #define PCLK_UART5 310 321 #define PCLK_UART6 311 322 #define PCLK_UART7 312 323 #define PCLK_TSADC 313 324 #define CLK_TSADC 314 325 #define HCLK_SAI0 315 326 #define HCLK_SAI1 316 327 #define HCLK_SAI2 317 328 #define HCLK_RKDSM 318 329 #define MCLK_RKDSM 319 330 #define HCLK_PDM 320 331 #define HCLK_ASRC0 321 332 #define HCLK_ASRC1 322 333 #define PCLK_AUDIO_ADC_BUS 323 334 #define MCLK_AUDIO_ADC_BUS 324 335 #define MCLK_AUDIO_ADC_DIV4_BUS 325 336 #define PCLK_RKCE 326 337 #define HCLK_NS_RKCE 327 338 #define PCLK_OTPC_NS 328 339 #define CLK_SBPI_OTPC_NS 329 340 #define CLK_USER_OTPC_NS 330 341 #define CLK_OTPC_ARB 331 342 #define PCLK_OTP_MASK 332 343 #define CLK_TSADC_PHYCTRL 333 344 #define LRCK_SRC_ASRC0 334 345 #define LRCK_DST_ASRC0 335 346 #define LRCK_SRC_ASRC1 336 347 #define LRCK_DST_ASRC1 337 348 #define PCLK_KEY_READER 338 349 #define ACLK_NSRKCE 339 350 #define CLK_PKA_NSRKCE 340 351 #define PCLK_RTC_ROOT 341 352 #define PCLK_GPIO1 342 353 #define DBCLK_GPIO1 343 354 #define PCLK_IOC_VCCIO1 344 355 #define ACLK_USB3OTG 345 356 #define CLK_REF_USB3OTG 346 357 #define CLK_SUSPEND_USB3OTG 347 358 #define HCLK_USB2HOST 348 359 #define HCLK_ARB_USB2HOST 349 360 #define PCLK_RTC_TEST 350 361 #define HCLK_EMMC 351 362 #define HCLK_FSPI0 352 363 #define HCLK_XIP_FSPI0 353 364 #define PCLK_PIPEPHY 354 365 #define PCLK_USB2PHY 355 366 #define CLK_REF_PIPEPHY_CPLL_SRC 356 367 #define CLK_REF_PIPEPHY 357 368 #define HCLK_VPSL 358 369 #define ACLK_VPSL 359 370 #define CLK_CORE_VPSL 360 371 #define CLK_MACPHY 361 372 #define HCLK_RKRNG_NS 362 373 #define HCLK_RKRNG_S_NS 362 374 375 /* secure clks */ 376 #define CLK_USER_OTPC_S 400 377 #define CLK_SBPI_OTPC_S 401 378 #define PCLK_OTPC_S 402 379 #define PCLK_KEY_READER_S 403 380 #define HCLK_KL_RKCE_S 404 381 #define HCLK_RKCE_S 405 382 #define PCLK_WDT_S 406 383 #define TCLK_WDT_S 407 384 #define CLK_STIMER0 408 385 #define CLK_STIMER1 409 386 #define PLK_STIMER 410 387 #define HCLK_RKRNG_S 411 388 #define CLK_PKA_RKCE_S 412 389 #define ACLK_RKCE_S 413 390 391 #define CLK_NR_CLKS (ACLK_RKCE_S + 1) 392 393 // ======================= TOPCRU module definition bank=0 ======================== 394 // TOPCRU_SOFTRST_CON15(Offset:0xA3C) 395 #define SRST_PRESETN_CRU 0x000000F1 396 #define SRST_PRESETN_CRU_BIU 0x000000F2 397 398 // ======================= BUSCRU module definition bank=1 ======================== 399 // BUSCRU_SOFTRST_CON00(Offset:0xA00) 400 #define SRST_ARESETN_TOP_BIU 0x00040000 401 #define SRST_ARESETN_RKCE_BIU 0x00040001 402 #define SRST_ARESETN_BUS_BIU 0x00040002 403 #define SRST_HRESETN_BUS_BIU 0x00040003 404 #define SRST_PRESETN_BUS_BIU 0x00040004 405 #define SRST_PRESETN_CRU_BUS 0x00040005 406 #define SRST_PRESETN_SYS_GRF 0x00040006 407 #define SRST_HRESETN_BOOTROM 0x00040007 408 #define SRST_ARESETN_GIC400 0x00040008 409 #define SRST_ARESETN_SPINLOCK 0x00040009 410 #define SRST_PRESETN_WDT_NS 0x0004000A 411 #define SRST_TRESETN_WDT_NS 0x0004000B 412 413 // BUSCRU_SOFTRST_CON01(Offset:0xA04) 414 #define SRST_PRESETN_WDT_HPMCU 0x00040010 415 #define SRST_TRESETN_WDT_HPMCU 0x00040011 416 #define SRST_HRESETN_CACHE 0x00040012 417 #define SRST_PRESETN_HPMCU_MAILBOX 0x00040013 418 #define SRST_PRESETN_HPMCU_INTMUX 0x00040014 419 #define SRST_RESETN_HPMCU_FULL_CLUSTER 0x00040015 420 #define SRST_RESETN_HPMCU_PWUP 0x00040016 421 #define SRST_RESETN_HPMCU_ONLY_CORE 0x00040017 422 #define SRST_TRESETN_HPMCU_JTAG 0x00040018 423 #define SRST_PRESETN_RKDMA 0x0004001B 424 #define SRST_ARESETN_RKDMA 0x0004001C 425 426 // BUSCRU_SOFTRST_CON02(Offset:0xA08) 427 #define SRST_PRESETN_DCF 0x00040020 428 #define SRST_ARESETN_DCF 0x00040021 429 #define SRST_HRESETN_RGA 0x00040022 430 #define SRST_ARESETN_RGA 0x00040023 431 #define SRST_RESETN_CORE_RGA 0x00040024 432 #define SRST_PRESETN_TIMER 0x00040025 433 #define SRST_RESETN_TIMER0 0x00040026 434 #define SRST_RESETN_TIMER1 0x00040027 435 #define SRST_RESETN_TIMER2 0x00040028 436 #define SRST_RESETN_TIMER3 0x00040029 437 #define SRST_RESETN_TIMER4 0x0004002A 438 #define SRST_RESETN_TIMER5 0x0004002B 439 #define SRST_ARESETN_RKCE 0x0004002C 440 #define SRST_RESETN_PKA_RKCE 0x0004002D 441 #define SRST_HRESETN_RKRNG_S 0x0004002E 442 #define SRST_HRESETN_RKRNG_NS 0x0004002F 443 444 // BUSCRU_SOFTRST_CON03(Offset:0xA0C) 445 #define SRST_PRESETN_I2C0 0x00040030 446 #define SRST_RESETN_I2C0 0x00040031 447 #define SRST_PRESETN_I2C1 0x00040032 448 #define SRST_RESETN_I2C1 0x00040033 449 #define SRST_PRESETN_I2C3 0x00040034 450 #define SRST_RESETN_I2C3 0x00040035 451 #define SRST_PRESETN_I2C4 0x00040036 452 #define SRST_RESETN_I2C4 0x00040037 453 #define SRST_PRESETN_I2C5 0x00040038 454 #define SRST_RESETN_I2C5 0x00040039 455 #define SRST_PRESETN_SPI0 0x0004003A 456 #define SRST_RESETN_SPI0 0x0004003B 457 #define SRST_PRESETN_SPI1 0x0004003C 458 #define SRST_RESETN_SPI1 0x0004003D 459 460 // BUSCRU_SOFTRST_CON04(Offset:0xA10) 461 #define SRST_PRESETN_PWM0 0x00040040 462 #define SRST_RESETN_PWM0 0x00040041 463 #define SRST_PRESETN_PWM2 0x00040044 464 #define SRST_RESETN_PWM2 0x00040045 465 #define SRST_PRESETN_PWM3 0x00040048 466 #define SRST_RESETN_PWM3 0x00040049 467 468 // BUSCRU_SOFTRST_CON05(Offset:0xA14) 469 #define SRST_PRESETN_UART1 0x00040050 470 #define SRST_SRESETN_UART1 0x00040051 471 #define SRST_PRESETN_UART2 0x00040052 472 #define SRST_SRESETN_UART2 0x00040053 473 #define SRST_PRESETN_UART3 0x00040054 474 #define SRST_SRESETN_UART3 0x00040055 475 #define SRST_PRESETN_UART4 0x00040056 476 #define SRST_SRESETN_UART4 0x00040057 477 #define SRST_PRESETN_UART5 0x00040058 478 #define SRST_SRESETN_UART5 0x00040059 479 #define SRST_PRESETN_UART6 0x0004005A 480 #define SRST_SRESETN_UART6 0x0004005B 481 #define SRST_PRESETN_UART7 0x0004005C 482 #define SRST_SRESETN_UART7 0x0004005D 483 484 // BUSCRU_SOFTRST_CON06(Offset:0xA18) 485 #define SRST_PRESETN_TSADC 0x00040060 486 #define SRST_RESETN_TSADC 0x00040061 487 #define SRST_HRESETN_SAI0 0x00040062 488 #define SRST_MRESETN_SAI0 0x00040063 489 #define SRST_HRESETN_SAI1 0x00040064 490 #define SRST_MRESETN_SAI1 0x00040065 491 #define SRST_HRESETN_SAI2 0x00040066 492 #define SRST_MRESETN_SAI2 0x00040067 493 #define SRST_HRESETN_RKDSM 0x00040068 494 #define SRST_MRESETN_RKDSM 0x00040069 495 #define SRST_HRESETN_PDM 0x0004006A 496 #define SRST_MRESETN_PDM 0x0004006B 497 #define SRST_RESETN_PDM 0x0004006C 498 499 // BUSCRU_SOFTRST_CON07(Offset:0xA1C) 500 #define SRST_HRESETN_ASRC0 0x00040070 501 #define SRST_RESETN_ASRC0 0x00040071 502 #define SRST_HRESETN_ASRC1 0x00040072 503 #define SRST_RESETN_ASRC1 0x00040073 504 #define SRST_PRESETN_AUDIO_ADC_BUS 0x00040074 505 #define SRST_MRESETN_AUDIO_ADC_BUS 0x00040075 506 #define SRST_PRESETN_RKCE 0x00040076 507 #define SRST_HRESETN_NS_RKCE 0x00040077 508 #define SRST_PRESETN_OTPC_NS 0x00040078 509 #define SRST_RESETN_SBPI_OTPC_NS 0x00040079 510 #define SRST_RESETN_USER_OTPC_NS 0x0004007A 511 #define SRST_RESETN_OTPC_ARB 0x0004007B 512 #define SRST_PRESETN_OTP_MASK 0x0004007C 513 #define SRST_RESETN_TSADC_PHYCTRL 0x0004007E 514 515 // ======================= PERICRU module definition bank=2 ======================= 516 // PERICRU_SOFTRST_CON00(Offset:0xA00) 517 #define SRST_ARESETN_PERI_BIU 0x00080000 518 #define SRST_PRESETN_PERI_BIU 0x00080001 519 #define SRST_PRESETN_RTC_BIU 0x00080002 520 #define SRST_PRESETN_CRU_PERI 0x00080003 521 #define SRST_PRESETN_PERI_GRF 0x00080004 522 #define SRST_PRESETN_GPIO1 0x00080005 523 #define SRST_DBRESETN_GPIO1 0x00080006 524 #define SRST_PRESETN_IOC_VCCIO1 0x00080007 525 #define SRST_ARESETN_USB3OTG 0x00080008 526 #define SRST_HRESETN_USB2HOST 0x0008000B 527 #define SRST_HRESETN_ARB_USB2HOST 0x0008000C 528 #define SRST_PRESETN_RTC_TEST 0x0008000D 529 530 // PERICRU_SOFTRST_CON01(Offset:0xA04) 531 #define SRST_HRESETN_EMMC 0x00080010 532 #define SRST_HRESETN_FSPI0 0x00080011 533 #define SRST_HRESETN_XIP_FSPI0 0x00080012 534 #define SRST_SRESETN_2X_FSPI0 0x00080013 535 #define SRST_RESETN_UTMI_USB2HOST 0x00080015 536 #define SRST_RESETN_REF_PIPEPHY 0x00080017 537 #define SRST_PRESETN_PIPEPHY 0x00080018 538 #define SRST_PRESETN_PIPEPHY_GRF 0x00080019 539 #define SRST_PRESETN_USB2PHY 0x0008001A 540 #define SRST_RESETN_POR_USB2PHY 0x0008001B 541 #define SRST_RESETN_OTG_USB2PHY 0x0008001C 542 #define SRST_RESETN_HOST_USB2PHY 0x0008001D 543 544 // ======================= CORECRU module definition bank=3 ======================= 545 // CORECRU_SOFTRST_CON00(Offset:0xA00) 546 #define SRST_RESETN_REF_PVTPLL_CORE 0x000C0000 547 #define SRST_NCOREPORESET0 0x000C0001 548 #define SRST_NCORESET0 0x000C0002 549 #define SRST_NCOREPORESET1 0x000C0003 550 #define SRST_NCORESET1 0x000C0004 551 #define SRST_NCOREPORESET2 0x000c0005 552 #define SRST_NCORESET2 0x000C0006 553 #define SRST_NCOREPORESET3 0x000C0007 554 #define SRST_NCORESET3 0x000C0008 555 #define SRST_NDBGRESET 0x000C0009 556 #define SRST_NL2RESET 0x000C000A 557 558 // CORECRU_SOFTRST_CON01(Offset:0xA04) 559 #define SRST_ARESETN_CORE_BIU 0x000C0010 560 #define SRST_PRESETN_CORE_BIU 0x000C0011 561 #define SRST_HRESETN_CORE_BIU 0x000C0012 562 #define SRST_PRESETN_DBG 0x000C0013 563 #define SRST_POTRESETN_DBG 0x000C0014 564 #define SRST_NTRESETN_DBG 0x000C0015 565 #define SRST_PRESETN_CORE_PVTPLL 0x000C0016 566 #define SRST_PRESETN_CRU_CORE 0x000C0017 567 #define SRST_PRESETN_CORE_GRF 0x000C0018 568 #define SRST_PRESETN_DFT2APB 0x000C001A 569 570 // ======================= PMUCRU module definition bank=4 ======================== 571 // PMUCRU_SOFTRST_CON00(Offset:0xA00) 572 #define SRST_HRESETN_PMU_BIU 0x00100000 573 #define SRST_PRESETN_PMU_GPIO0 0x00100007 574 #define SRST_DBRESETN_PMU_GPIO0 0x00100008 575 #define SRST_PRESETN_PMU_HP_TIMER 0x0010000A 576 #define SRST_RESETN_PMU_HP_TIMER 0x0010000B 577 #define SRST_RESETN_PMU_32K_HP_TIMER 0x0010000C 578 579 // PMUCRU_SOFTRST_CON01(Offset:0xA04) 580 #define SRST_PRESETN_PWM1 0x00100010 581 #define SRST_RESETN_PWM1 0x00100011 582 #define SRST_PRESETN_I2C2 0x00100012 583 #define SRST_RESETN_I2C2 0x00100013 584 #define SRST_PRESETN_UART0 0x00100014 585 #define SRST_SRESETN_UART0 0x00100015 586 587 // PMUCRU_SOFTRST_CON02(Offset:0xA08) 588 #define SRST_PRESETN_RCOSC_CTRL 0x00100020 589 #define SRST_RESETN_REF_RCOSC_CTRL 0x00100022 590 #define SRST_PRESETN_IOC_PMUIO0 0x00100023 591 #define SRST_PRESETN_CRU_PMU 0x00100024 592 #define SRST_PRESETN_PMU_GRF 0x00100025 593 #define SRST_RESETN_PREROLL 0x00100027 594 #define SRST_RESETN_PREROLL_32K 0x00100028 595 #define SRST_HRESETN_PMU_SRAM 0x00100029 596 597 // PMUCRU_SOFTRST_CON03(Offset:0xA0C) 598 #define SRST_PRESETN_WDT_LPMCU 0x00100030 599 #define SRST_TRESETN_WDT_LPMCU 0x00100031 600 #define SRST_RESETN_LPMCU_FULL_CLUSTER 0x00100032 601 #define SRST_RESETN_LPMCU_PWUP 0x00100033 602 #define SRST_RESETN_LPMCU_ONLY_CORE 0x00100034 603 #define SRST_TRESETN_LPMCU_JTAG 0x00100035 604 #define SRST_PRESETN_LPMCU_MAILBOX 0x00100036 605 606 // ======================= PMU1CRU module definition bank=5 ======================= 607 // PMU1CRU_SOFTRST_CON00(Offset:0xA00) 608 #define SRST_PRESETN_SPI2AHB 0x00140000 609 #define SRST_HRESETN_SPI2AHB 0x00140001 610 #define SRST_HRESETN_FSPI1 0x00140002 611 #define SRST_HRESETN_XIP_FSPI1 0x00140003 612 #define SRST_SRESETN_1X_FSPI1 0x00140004 613 #define SRST_PRESETN_IOC_PMUIO1 0x00140005 614 #define SRST_PRESETN_CRU_PMU1 0x00140006 615 #define SRST_PRESETN_AUDIO_ADC_PMU 0x00140007 616 #define SRST_MRESETN_AUDIO_ADC_PMU 0x00140008 617 #define SRST_HRESETN_PMU1_BIU 0x00140009 618 619 // PMU1CRU_SOFTRST_CON01(Offset:0xA04) 620 #define SRST_PRESETN_LPDMA 0x00140010 621 #define SRST_ARESETN_LPDMA 0x00140011 622 #define SRST_HRESETN_LPSAI 0x00140012 623 #define SRST_MRESETN_LPSAI 0x00140013 624 #define SRST_PRESETN_AOA_TDD 0x00140014 625 #define SRST_PRESETN_AOA_FE 0x00140015 626 #define SRST_PRESETN_AOA_AAD 0x00140016 627 #define SRST_PRESETN_AOA_APB 0x00140017 628 #define SRST_PRESETN_AOA_SRAM 0x00140018 629 630 // ======================= DDRCRU module definition bank=6 ======================== 631 // DDRCRU_SOFTRST_CON00(Offset:0xA00) 632 #define SRST_PRESETN_DDR_BIU 0x00180001 633 #define SRST_PRESETN_DDRC 0x00180002 634 #define SRST_PRESETN_DDRMON 0x00180003 635 #define SRST_RESETN_TIMER_DDRMON 0x00180004 636 #define SRST_PRESETN_DFICTRL 0x00180005 637 #define SRST_PRESETN_DDR_GRF 0x00180006 638 #define SRST_PRESETN_CRU_DDR 0x00180007 639 #define SRST_PRESETN_DDRPHY 0x00180008 640 #define SRST_PRESETN_DMA2DDR 0x00180009 641 642 // ====================== SUBDDRCRU module definition bank=7 ====================== 643 // SUBDDRCRU_SOFTRST_CON00(Offset:0xA00) 644 #define SRST_ARESETN_SYSMEM_BIU 0x001A0000 645 #define SRST_ARESETN_SYSMEM 0x001A0001 646 #define SRST_ARESETN_DDR_BIU 0x001A0002 647 #define SRST_ARESETN_DDRSCH0_CPU 0x001A0003 648 #define SRST_ARESETN_DDRSCH1_NPU 0x001A0004 649 #define SRST_ARESETN_DDRSCH2_POE 0x001A0005 650 #define SRST_ARESETN_DDRSCH3_VI 0x001A0006 651 #define SRST_RESETN_CORE_DDRC 0x001A0007 652 #define SRST_RESETN_DDRMON 0x001A0008 653 #define SRST_RESETN_DFICTRL 0x001A0009 654 #define SRST_RESETN_RS 0x001A000B 655 #define SRST_ARESETN_DMA2DDR 0x001A000C 656 #define SRST_RESETN_DDRPHY 0x001A000D 657 658 // ======================== VICRU module definition bank=8 ======================== 659 // VICRU_SOFTRST_CON00(Offset:0xA00) 660 #define SRST_RESETN_REF_PVTPLL_ISP 0x001C0000 661 #define SRST_ARESETN_GMAC_BIU 0x001C0001 662 #define SRST_ARESETN_VI_BIU 0x001C0002 663 #define SRST_HRESETN_VI_BIU 0x001C0003 664 #define SRST_PRESETN_VI_BIU 0x001C0004 665 #define SRST_PRESETN_CRU_VI 0x001C0005 666 #define SRST_PRESETN_VI_GRF 0x001C0006 667 #define SRST_PRESETN_VI_PVTPLL 0x001C0007 668 #define SRST_PRESETN_DSMC 0x001C0008 669 #define SRST_ARESETN_DSMC 0x001C0009 670 #define SRST_HRESETN_CAN0 0x001C000A 671 #define SRST_RESETN_CAN0 0x001C000B 672 #define SRST_HRESETN_CAN1 0x001C000C 673 #define SRST_RESETN_CAN1 0x001C000D 674 675 // VICRU_SOFTRST_CON01(Offset:0xA04) 676 #define SRST_PRESETN_GPIO2 0x001C0010 677 #define SRST_DBRESETN_GPIO2 0x001C0011 678 #define SRST_PRESETN_GPIO4 0x001C0012 679 #define SRST_DBRESETN_GPIO4 0x001C0013 680 #define SRST_PRESETN_GPIO5 0x001C0014 681 #define SRST_DBRESETN_GPIO5 0x001C0015 682 #define SRST_PRESETN_GPIO6 0x001C0016 683 #define SRST_DBRESETN_GPIO6 0x001C0017 684 #define SRST_PRESETN_GPIO7 0x001C0018 685 #define SRST_DBRESETN_GPIO7 0x001C0019 686 #define SRST_PRESETN_IOC_VCCIO2 0x001C001A 687 #define SRST_PRESETN_IOC_VCCIO4 0x001C001B 688 #define SRST_PRESETN_IOC_VCCIO5 0x001C001C 689 #define SRST_PRESETN_IOC_VCCIO6 0x001C001D 690 #define SRST_PRESETN_IOC_VCCIO7 0x001C001E 691 692 // VICRU_SOFTRST_CON02(Offset:0xA08) 693 #define SRST_RESETN_CORE_ISP 0x001C0020 694 #define SRST_HRESETN_VICAP 0x001C0021 695 #define SRST_ARESETN_VICAP 0x001C0022 696 #define SRST_DRESETN_VICAP 0x001C0023 697 #define SRST_ISP0RESETN_VICAP 0x001C0024 698 #define SRST_RESETN_CORE_VPSS 0x001C0025 699 #define SRST_RESETN_CORE_VPSL 0x001C0026 700 #define SRST_PRESETN_CSI2HOST0 0x001C0027 701 #define SRST_PRESETN_CSI2HOST1 0x001C0028 702 #define SRST_PRESETN_CSI2HOST2 0x001C0029 703 #define SRST_PRESETN_CSI2HOST3 0x001C002A 704 #define SRST_HRESETN_SDMMC0 0x001C002B 705 #define SRST_ARESETN_GMAC 0x001C002C 706 #define SRST_PRESETN_CSIPHY0 0x001C002D 707 #define SRST_PRESETN_CSIPHY1 0x001C002E 708 709 // VICRU_SOFTRST_CON03(Offset:0xA0C) 710 #define SRST_PRESETN_MACPHY 0x001C0030 711 #define SRST_RESETN_MACPHY 0x001C0031 712 #define SRST_PRESETN_SARADC1 0x001C0032 713 #define SRST_RESETN_SARADC1 0x001C0033 714 #define SRST_RESETN_SARADC1_PHY 0x001C0034 715 #define SRST_PRESETN_SARADC2 0x001C0035 716 #define SRST_RESETN_SARADC2 0x001C0036 717 #define SRST_RESETN_SARADC2_PHY 0x001C0037 718 719 // ======================= VEPUCRU module definition bank=9 ======================= 720 // VEPUCRU_SOFTRST_CON00(Offset:0xA00) 721 #define SRST_RESETN_REF_PVTPLL_VEPU 0x00200000 722 #define SRST_ARESETN_VEPU_BIU 0x00200001 723 #define SRST_HRESETN_VEPU_BIU 0x00200002 724 #define SRST_PRESETN_VEPU_BIU 0x00200003 725 #define SRST_PRESETN_CRU_VEPU 0x00200004 726 #define SRST_PRESETN_VEPU_GRF 0x00200005 727 #define SRST_PRESETN_GPIO3 0x00200007 728 #define SRST_DBRESETN_GPIO3 0x00200008 729 #define SRST_PRESETN_IOC_VCCIO3 0x00200009 730 #define SRST_PRESETN_SARADC0 0x0020000A 731 #define SRST_RESETN_SARADC0 0x0020000B 732 #define SRST_RESETN_SARADC0_PHY 0x0020000C 733 #define SRST_HRESETN_SDMMC1 0x0020000D 734 735 // VEPUCRU_SOFTRST_CON01(Offset:0xA04) 736 #define SRST_PRESETN_VEPU_PVTPLL 0x00200010 737 #define SRST_HRESETN_VEPU 0x00200011 738 #define SRST_ARESETN_VEPU 0x00200012 739 #define SRST_RESETN_CORE_VEPU 0x00200013 740 741 // ======================= NPUCRU module definition bank=10 ======================= 742 // NPUCRU_SOFTRST_CON00(Offset:0xA00) 743 #define SRST_RESETN_REF_PVTPLL_NPU 0x00240000 744 #define SRST_ARESETN_NPU_BIU 0x00240002 745 #define SRST_HRESETN_NPU_BIU 0x00240003 746 #define SRST_PRESETN_NPU_BIU 0x00240004 747 #define SRST_PRESETN_CRU_NPU 0x00240005 748 #define SRST_PRESETN_NPU_GRF 0x00240006 749 #define SRST_PRESETN_NPU_PVTPLL 0x00240008 750 #define SRST_HRESETN_RKNN 0x00240009 751 #define SRST_ARESETN_RKNN 0x0024000A 752 753 // ======================= VDOCRU module definition bank=11 ======================= 754 // VDOCRU_SOFTRST_CON00(Offset:0xA00) 755 #define SRST_ARESETN_RKVDEC_BIU 0x00280000 756 #define SRST_ARESETN_VDO_BIU 0x00280001 757 #define SRST_HRESETN_VDO_BIU 0x00280003 758 #define SRST_PRESETN_VDO_BIU 0x00280004 759 #define SRST_PRESETN_CRU_VDO 0x00280005 760 #define SRST_PRESETN_VDO_GRF 0x00280006 761 #define SRST_ARESETN_RKVDEC 0x00280007 762 #define SRST_HRESETN_RKVDEC 0x00280008 763 #define SRST_RESETN_HEVC_CA_RKVDEC 0x00280009 764 #define SRST_ARESETN_VOP 0x0028000A 765 #define SRST_HRESETN_VOP 0x0028000B 766 #define SRST_DRESETN_VOP 0x0028000C 767 #define SRST_ARESETN_OOC 0x0028000D 768 #define SRST_HRESETN_OOC 0x0028000E 769 #define SRST_DRESETN_OOC 0x0028000F 770 771 // VDOCRU_SOFTRST_CON01(Offset:0xA04) 772 #define SRST_HRESETN_RKJPEG 0x00280013 773 #define SRST_ARESETN_RKJPEG 0x00280014 774 #define SRST_ARESETN_RKMMU_DECOM 0x00280015 775 #define SRST_HRESETN_RKMMU_DECOM 0x00280016 776 #define SRST_DRESETN_DECOM 0x00280018 777 #define SRST_ARESETN_DECOM 0x00280019 778 #define SRST_PRESETN_DECOM 0x0028001A 779 #define SRST_PRESETN_MIPI_DSI 0x0028001C 780 #define SRST_PRESETN_DSIPHY 0x0028001D 781 782 // ======================= VCPCRU module definition bank=12 ======================= 783 // VCPCRU_SOFTRST_CON00(Offset:0xA00) 784 #define SRST_RESETN_REF_PVTPLL_VCP 0x002C0000 785 #define SRST_ARESETN_VCP_BIU 0x002C0001 786 #define SRST_HRESETN_VCP_BIU 0x002C0002 787 #define SRST_PRESETN_VCP_BIU 0x002C0003 788 #define SRST_PRESETN_CRU_VCP 0x002C0004 789 #define SRST_PRESETN_VCP_GRF 0x002C0005 790 #define SRST_PRESETN_VCP_PVTPLL 0x002C0007 791 #define SRST_ARESETN_AISP_BIU 0x002C0008 792 #define SRST_HRESETN_AISP_BIU 0x002C0009 793 #define SRST_ARESETN_AISPMEM_BIU 0x002C000A 794 #define SRST_RESETN_CORE_AISP 0x002C000D 795 #define SRST_ARESETN_AISPMEM 0x002C000E 796 797 // VCPCRU_SOFTRST_CON01(Offset:0xA04) 798 #define SRST_HRESETN_FEC 0x002C0010 799 #define SRST_ARESETN_FEC 0x002C0011 800 #define SRST_RESETN_CORE_FEC 0x002C0012 801 #define SRST_HRESETN_AVSP 0x002C0013 802 #define SRST_ARESETN_AVSP 0x002C0014 803 804 #define CLK_NR_SRST (SRST_ARESETN_AVSP + 1) 805 806 #endif 807