1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Broadcom PCIE 4 * Software-specific definitions shared between device and host side 5 * Explains the shared area between host and dongle 6 * 7 * Copyright (C) 1999-2017, Broadcom Corporation 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id: bcmpcie.h 678914 2017-01-11 15:34:26Z $ 31 */ 32 33 34 #ifndef _bcmpcie_h_ 35 #define _bcmpcie_h_ 36 37 #include <bcmutils.h> 38 39 #define ADDR_64(x) (x.addr) 40 #define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr)) 41 #define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr)) 42 43 typedef struct { 44 uint32 low_addr; 45 uint32 high_addr; 46 } sh_addr_t; 47 48 49 /* May be overridden by 43xxxxx-roml.mk */ 50 #if !defined(BCMPCIE_MAX_TX_FLOWS) 51 #define BCMPCIE_MAX_TX_FLOWS 40 52 #endif /* ! BCMPCIE_MAX_TX_FLOWS */ 53 54 #define PCIE_SHARED_VERSION_7 0x00007 55 #define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */ 56 #define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */ 57 /** 58 * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that 59 * is located in device memory. 60 */ 61 #define PCIE_SHARED_VERSION PCIE_SHARED_VERSION_7 62 #define PCIE_SHARED_VERSION_MASK 0x000FF 63 #define PCIE_SHARED_ASSERT_BUILT 0x00100 64 #define PCIE_SHARED_ASSERT 0x00200 65 #define PCIE_SHARED_TRAP 0x00400 66 #define PCIE_SHARED_IN_BRPT 0x00800 67 #define PCIE_SHARED_SET_BRPT 0x01000 68 #define PCIE_SHARED_PENDING_BRPT 0x02000 69 /* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */ 70 #define PCIE_SHARED_EVT_SEQNUM 0x08000 71 #define PCIE_SHARED_DMA_INDEX 0x10000 72 73 /* WAR: D11 txstatus through unused status field of PCIe completion header */ 74 #define PCIE_SHARED_D2H_D11_TX_STATUS 0x40000000 /* using flags2 in shared area */ 75 #define PCIE_SHARED_H2D_D11_TX_STATUS 0x80000000 /* using flags2 in shared area */ 76 77 /** 78 * There are host types where a device interrupt can 'race ahead' of data written by the device into 79 * host memory. The dongle can avoid this condition using a variety of techniques (read barrier, 80 * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately 81 * these techniques have drawbacks on router platforms. For these platforms, it was decided to not 82 * avoid the condition, but to detect the condition instead and act on it. 83 * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM 84 */ 85 #define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000 86 #define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000 87 #define PCIE_SHARED_D2H_SYNC_MODE_MASK \ 88 (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM) 89 #define PCIE_SHARED_IDLE_FLOW_RING 0x80000 90 #define PCIE_SHARED_2BYTE_INDICES 0x100000 91 92 #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 /* using flags2 in shared area */ 93 94 /* dongle supports fatal buf log collection */ 95 #define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000 96 97 /* Implicit DMA with corerev 19 and after */ 98 #define PCIE_SHARED_IDMA 0x400000 99 100 /* MSI support */ 101 #define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000 102 103 /* IFRM with corerev 19 and after */ 104 #define PCIE_SHARED_IFRM 0x1000000 105 106 /** 107 * From Rev6 and above, suspend/resume can be done using two handshake methods. 108 * 1. Using ctrl post/ctrl cmpl messages (Default rev6) 109 * 2. Using Mailbox data (old method as used in rev5) 110 * This shared flag indicates whether to overide rev6 default method and use mailbox for 111 * suspend/resume. 112 */ 113 #define PCIE_SHARED_USE_MAILBOX 0x2000000 114 115 /* Firmware compiled for mfgbuild purposes */ 116 #define PCIE_SHARED_MFGBUILD_FW 0x4000000 117 118 /* Firmware could use DB0 value as host timestamp */ 119 #define PCIE_SHARED_TIMESTAMP_DB0 0x8000000 120 /* Firmware could use Hostready (IPC rev7) */ 121 #define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000 122 123 /* When set, Firmwar does not support OOB Device Wake based DS protocol */ 124 #define PCIE_SHARED_NO_OOB_DW 0x20000000 125 126 /* When set, Firmwar supports Inband DS protocol */ 127 #define PCIE_SHARED_INBAND_DS 0x40000000 128 129 /* Implicit DMA WAR for 4347B0 PCIe memory retention */ 130 #define PCIE_SHARED_IDMA_RETENTION_DS 0x80000000 131 132 #define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09 133 #define PCIE_SHARED_H2D_MAGIC 0x12345678 134 135 /** 136 * Message rings convey messages between host and device. They are unidirectional, and are located 137 * in host memory. 138 * 139 * This is the minimal set of message rings, known as 'common message rings': 140 */ 141 #define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0 142 #define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1 143 #define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2 144 #define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3 145 #define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4 146 #define BCMPCIE_COMMON_MSGRING_MAX_ID 4 147 148 #define BCMPCIE_H2D_COMMON_MSGRINGS 2 149 #define BCMPCIE_D2H_COMMON_MSGRINGS 3 150 #define BCMPCIE_COMMON_MSGRINGS 5 151 152 #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \ 153 (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows)) 154 155 /* different ring types */ 156 #define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1 157 #define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2 158 #define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3 159 #define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4 160 #define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5 161 162 #define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1 163 #define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2 164 #define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3 165 #define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4 166 #define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5 167 168 /** 169 * H2D and D2H, WR and RD index, are maintained in the following arrays: 170 * - Array of all H2D WR Indices 171 * - Array of all H2D RD Indices 172 * - Array of all D2H WR Indices 173 * - Array of all D2H RD Indices 174 * 175 * The offset of the WR or RD indexes (for common rings) in these arrays are 176 * listed below. Arrays ARE NOT indexed by a ring's id. 177 * 178 * D2H common rings WR and RD index start from 0, even though their ringids 179 * start from BCMPCIE_H2D_COMMON_MSGRINGS 180 */ 181 182 #define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id) 183 184 enum h2dring_idx { 185 /* H2D common rings */ 186 BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX = 187 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT), 188 BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX = 189 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT), 190 191 /* First TxPost's WR or RD index starts after all H2D common rings */ 192 BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START = 193 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS) 194 }; 195 196 #define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \ 197 ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS) 198 199 enum d2hring_idx { 200 /* D2H Common Rings */ 201 BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX = 202 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE), 203 BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX = 204 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE), 205 BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX = 206 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE) 207 }; 208 209 /** 210 * Macros for managing arrays of RD WR indices: 211 * rw_index_sz: 212 * - in dongle, rw_index_sz is known at compile time 213 * - in host/DHD, rw_index_sz is derived from advertized pci_shared flags 214 * 215 * ring_idx: See h2dring_idx and d2hring_idx 216 */ 217 218 /** Offset of a RD or WR index in H2D or D2H indices array */ 219 #define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \ 220 ((rw_index_sz) * (ring_idx)) 221 222 /** Fetch the address of RD or WR index in H2D or D2H indices array */ 223 #define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \ 224 (void *)((uint32)(indices_array_base) + \ 225 BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx))) 226 227 /** H2D DMA Indices array size: given max flow rings */ 228 #define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \ 229 ((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows)) 230 231 /** D2H DMA Indices array size */ 232 #define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \ 233 ((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS) 234 235 /** 236 * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used 237 * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated 238 * both in host as well as device memory. 239 */ 240 typedef struct ring_mem { 241 uint16 idx; /* ring id */ 242 uint8 type; 243 uint8 rsvd; 244 uint16 max_item; /* Max number of items in flow ring */ 245 uint16 len_items; /* Items are fixed size. Length in bytes of one item */ 246 sh_addr_t base_addr; /* 64 bits address, either in host or device memory */ 247 } ring_mem_t; 248 249 250 /** 251 * Per flow ring, information is maintained in device memory, eg at what address the ringmem and 252 * ringstate are located. The flow ring itself can be instantiated in either host or device memory. 253 * 254 * Perhaps this type should be renamed to make clear that it resides in device memory only. 255 */ 256 typedef struct ring_info { 257 uint32 ringmem_ptr; /* ring mem location in dongle memory */ 258 259 /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not 260 * by a ringid. 261 */ 262 263 /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */ 264 uint32 h2d_w_idx_ptr; /* Array of all H2D ring's WR indices */ 265 uint32 h2d_r_idx_ptr; /* Array of all H2D ring's RD indices */ 266 uint32 d2h_w_idx_ptr; /* Array of all D2H ring's WR indices */ 267 uint32 d2h_r_idx_ptr; /* Array of all D2H ring's RD indices */ 268 269 /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host. 270 * Host may directly fetch WR and RD indices from these host-side arrays. 271 * 272 * 64bit ptr to arrays of WR or RD indices for all rings in host memory. 273 */ 274 sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */ 275 sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */ 276 sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */ 277 sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */ 278 279 uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */ 280 uint16 max_submission_queues; /* maximum number of H2D rings: common + flow */ 281 uint16 max_completion_rings; /* maximum number of H2D rings: common + flow */ 282 uint16 max_vdevs; /* max number of virtual interfaces supported */ 283 284 sh_addr_t ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */ 285 } ring_info_t; 286 287 /** 288 * A structure located in TCM that is shared between host and device, primarily used during 289 * initialization. 290 */ 291 typedef struct { 292 /** shared area version captured at flags 7:0 */ 293 uint32 flags; 294 295 uint32 trap_addr; 296 uint32 assert_exp_addr; 297 uint32 assert_file_addr; 298 uint32 assert_line; 299 uint32 console_addr; /**< Address of hnd_cons_t */ 300 301 uint32 msgtrace_addr; 302 303 uint32 fwid; 304 305 /* Used for debug/flow control */ 306 uint16 total_lfrag_pkt_cnt; 307 uint16 max_host_rxbufs; /* rsvd in spec */ 308 309 uint32 dma_rxoffset; /* rsvd in spec */ 310 311 /** these will be used for sleep request/ack, d3 req/ack */ 312 uint32 h2d_mb_data_ptr; 313 uint32 d2h_mb_data_ptr; 314 315 /* information pertinent to host IPC/msgbuf channels */ 316 /** location in the TCM memory which has the ring_info */ 317 uint32 rings_info_ptr; 318 319 /** block of host memory for the scratch buffer */ 320 uint32 host_dma_scratch_buffer_len; 321 sh_addr_t host_dma_scratch_buffer; 322 323 /** block of host memory for the dongle to push the status into */ 324 uint32 device_rings_stsblk_len; 325 sh_addr_t device_rings_stsblk; 326 327 uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */ 328 329 /* rev6 compatible changes */ 330 uint32 flags2; 331 uint32 host_cap; 332 333 /* location in the host address space to write trap indication. 334 * At this point for the current rev of the spec, firmware will 335 * support only indications to 32 bit host addresses. 336 */ 337 sh_addr_t host_trap_addr; 338 339 /* location for host fatal error log buffer start address */ 340 uint32 device_fatal_logbuf_start; 341 342 /* location in host memory for offloaded modules */ 343 sh_addr_t hoffload_addr; 344 } pciedev_shared_t; 345 346 extern pciedev_shared_t pciedev_shared; 347 348 /* host capabilities */ 349 #define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF 350 #define HOSTCAP_H2D_VALID_PHASE 0x00000100 351 #define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200 352 #define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400 353 #define HOSTCAP_DB0_TIMESTAMP 0x00000800 354 #define HOSTCAP_DS_NO_OOB_DW 0x00001000 355 #define HOSTCAP_DS_INBAND_DW 0x00002000 356 #define HOSTCAP_H2D_IDMA 0x00004000 357 #define HOSTCAP_H2D_IFRM 0x00008000 358 #define HOSTCAP_H2D_DAR 0x00010000 359 #define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000 360 #define HOSTCAP_TXSTATUS_METADATA 0x00040000 361 362 /** 363 * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware 364 * support. 365 */ 366 367 /* H2D mail box Data */ 368 #define H2D_HOST_D3_INFORM 0x00000001 369 #define H2D_HOST_DS_ACK 0x00000002 370 #define H2D_HOST_DS_NAK 0x00000004 371 #define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */ 372 #define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */ 373 #define H2D_HOST_D0_INFORM_IN_USE 0x00000008 374 #define H2D_HOST_D0_INFORM 0x00000010 375 #define H2D_HOST_IDMA_INITED 0x00000080 376 #define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM 377 #define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK 378 #define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK 379 #define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE 380 #define H2DMB_D0_INFORM H2D_HOST_D0_INFORM 381 #define H2DMB_DS_ACTIVE 0x00000020 382 #define H2DMB_DS_DEVICE_WAKE 0x00000040 383 #define H2DMB_FW_TRAP H2D_FW_TRAP 384 #define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT 385 #define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE 386 #define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE 387 388 /* D2H mail box Data */ 389 #define D2H_DEV_D3_ACK 0x00000001 390 #define D2H_DEV_DS_ENTER_REQ 0x00000002 391 #define D2H_DEV_DS_EXIT_NOTE 0x00000004 392 #define D2H_DEV_FWHALT 0x10000000 393 #define D2H_DEV_EXT_TRAP_DATA 0x20000000 394 #define D2H_DEV_IDMA_INITED 0x00000010 395 #define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */ 396 #define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK 397 #define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ 398 #define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE 399 #define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008 400 #define D2HMB_FWHALT D2H_DEV_FWHALT 401 #define D2H_DEV_MB_MASK (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \ 402 D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED | D2H_DEV_FWHALT | \ 403 D2H_FWTRAP_MASK | D2H_DEV_EXT_TRAP_DATA) 404 #define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK)) 405 406 407 /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */ 408 #define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1)) 409 #define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w))) 410 #define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1) 411 412 /* Function can be used to notify host of FW halt */ 413 #define READ_AVAIL_SPACE(w, r, d) \ 414 ((w >= r) ? (w - r) : (d - r)) 415 416 #define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w)) 417 #define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1) 418 #define CHECK_WRITE_SPACE(r, w, d) \ 419 ((r) > (w)) ? ((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? ((d) - (w) - 1) : ((d) - (w)) 420 #define CHECK_NOWRITE_SPACE(r, w, d) \ 421 (((r) == (w) + 1) || (((r) == 0) && ((w) == ((d) - 1)))) 422 423 424 #define WRT_PEND(x) ((x)->wr_pending) 425 #define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */ 426 #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a)) 427 428 #define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */ 429 #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a)) 430 431 #define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size) 432 433 #define RING_READ_PTR(x) ((x)->ringstate->r_offset) 434 #define RING_WRITE_PTR(x) ((x)->ringstate->w_offset) 435 #define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr) 436 #define RING_MAX_ITEM(x) ((x)->ringmem->max_item) 437 #define RING_LEN_ITEMS(x) ((x)->ringmem->len_items) 438 #define HOST_RING_BASE(x) ((x)->dma_buf.va) 439 #define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \ 440 ((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x)))) 441 #endif /* _bcmpcie_h_ */ 442