1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 16 17 #ifndef __PHYDMPREDEFINE_H__ 18 #define __PHYDMPREDEFINE_H__ 19 20 /* 1 ============================================================ 21 * 1 Definition 22 * 1 ============================================================ */ 23 24 #define PHYDM_CODE_BASE "PHYDM_V021" 25 #define PHYDM_RELEASE_DATE "20170801" 26 27 /*PHYDM API status*/ 28 #define PHYDM_SET_FAIL 0 29 #define PHYDM_SET_SUCCESS 1 30 #define PHYDM_SET_NO_NEED 3 31 32 /*PHYDM Set/Revert*/ 33 #define PHYDM_SET 1 34 #define PHYDM_REVERT 2 35 36 /* Max path of IC */ 37 /*N-IC*/ 38 #define MAX_PATH_NUM_8188E 1 39 #define MAX_PATH_NUM_8188F 1 40 #define MAX_PATH_NUM_8710B 1 41 #define MAX_PATH_NUM_8723B 1 42 #define MAX_PATH_NUM_8723D 1 43 #define MAX_PATH_NUM_8703B 1 44 #define MAX_PATH_NUM_8192E 2 45 #define MAX_PATH_NUM_8197F 2 46 #define MAX_PATH_NUM_8198F 4 47 /*AC-IC*/ 48 #define MAX_PATH_NUM_8821A 1 49 #define MAX_PATH_NUM_8821C 1 50 #define MAX_PATH_NUM_8812A 2 51 #define MAX_PATH_NUM_8822B 2 52 #define MAX_PATH_NUM_8814A 4 53 #define MAX_PATH_NUM_8814B 4 54 55 /* Max RF path */ 56 #define ODM_RF_PATH_MAX 2 57 #define ODM_RF_PATH_MAX_JAGUAR 4 58 #define PHYDM_MAX_RF_PATH 4 59 60 /* number of entry */ 61 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 62 #ifdef DM_ODM_CE_MAC80211 63 /* defined in wifi.h (32+1) */ 64 #else 65 #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/ 66 #endif 67 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 68 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) 69 #define ASSOCIATE_ENTRY_NUM NUM_STAT 70 #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1) 71 #else 72 #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) 73 #endif 74 75 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) 76 #define RX_SMOOTH_FACTOR 20 77 #endif 78 79 /* -----MGN rate--------------------------------- */ 80 81 enum ODM_MGN_RATE { 82 ODM_MGN_1M = 0x02, 83 ODM_MGN_2M = 0x04, 84 ODM_MGN_5_5M = 0x0B, 85 ODM_MGN_6M = 0x0C, 86 ODM_MGN_9M = 0x12, 87 ODM_MGN_11M = 0x16, 88 ODM_MGN_12M = 0x18, 89 ODM_MGN_18M = 0x24, 90 ODM_MGN_24M = 0x30, 91 ODM_MGN_36M = 0x48, 92 ODM_MGN_48M = 0x60, 93 ODM_MGN_54M = 0x6C, 94 ODM_MGN_MCS32 = 0x7F, 95 ODM_MGN_MCS0 = 0x80, 96 ODM_MGN_MCS1, 97 ODM_MGN_MCS2, 98 ODM_MGN_MCS3, 99 ODM_MGN_MCS4, 100 ODM_MGN_MCS5, 101 ODM_MGN_MCS6, 102 ODM_MGN_MCS7 = 0x87, 103 ODM_MGN_MCS8, 104 ODM_MGN_MCS9, 105 ODM_MGN_MCS10, 106 ODM_MGN_MCS11, 107 ODM_MGN_MCS12, 108 ODM_MGN_MCS13, 109 ODM_MGN_MCS14, 110 ODM_MGN_MCS15, 111 ODM_MGN_MCS16 = 0x90, 112 ODM_MGN_MCS17, 113 ODM_MGN_MCS18, 114 ODM_MGN_MCS19, 115 ODM_MGN_MCS20, 116 ODM_MGN_MCS21, 117 ODM_MGN_MCS22, 118 ODM_MGN_MCS23, 119 ODM_MGN_MCS24 = 0x98, 120 ODM_MGN_MCS25, 121 ODM_MGN_MCS26, 122 ODM_MGN_MCS27, 123 ODM_MGN_MCS28, 124 ODM_MGN_MCS29, 125 ODM_MGN_MCS30, 126 ODM_MGN_MCS31, 127 ODM_MGN_VHT1SS_MCS0 = 0xa0, 128 ODM_MGN_VHT1SS_MCS1, 129 ODM_MGN_VHT1SS_MCS2, 130 ODM_MGN_VHT1SS_MCS3, 131 ODM_MGN_VHT1SS_MCS4, 132 ODM_MGN_VHT1SS_MCS5, 133 ODM_MGN_VHT1SS_MCS6, 134 ODM_MGN_VHT1SS_MCS7, 135 ODM_MGN_VHT1SS_MCS8, 136 ODM_MGN_VHT1SS_MCS9, 137 ODM_MGN_VHT2SS_MCS0 = 0xaa, 138 ODM_MGN_VHT2SS_MCS1 = 0xab, 139 ODM_MGN_VHT2SS_MCS2, 140 ODM_MGN_VHT2SS_MCS3, 141 ODM_MGN_VHT2SS_MCS4, 142 ODM_MGN_VHT2SS_MCS5 = 0xaf, 143 ODM_MGN_VHT2SS_MCS6 = 0xb0, 144 ODM_MGN_VHT2SS_MCS7, 145 ODM_MGN_VHT2SS_MCS8, 146 ODM_MGN_VHT2SS_MCS9 = 0xb3, 147 ODM_MGN_VHT3SS_MCS0 = 0xb4, 148 ODM_MGN_VHT3SS_MCS1, 149 ODM_MGN_VHT3SS_MCS2, 150 ODM_MGN_VHT3SS_MCS3, 151 ODM_MGN_VHT3SS_MCS4, 152 ODM_MGN_VHT3SS_MCS5, 153 ODM_MGN_VHT3SS_MCS6, 154 ODM_MGN_VHT3SS_MCS7 = 0xbb, 155 ODM_MGN_VHT3SS_MCS8 = 0xbc, 156 ODM_MGN_VHT3SS_MCS9 = 0xbd, 157 ODM_MGN_VHT4SS_MCS0 = 0xbe, 158 ODM_MGN_VHT4SS_MCS1, 159 ODM_MGN_VHT4SS_MCS2, 160 ODM_MGN_VHT4SS_MCS3, 161 ODM_MGN_VHT4SS_MCS4, 162 ODM_MGN_VHT4SS_MCS5, 163 ODM_MGN_VHT4SS_MCS6, 164 ODM_MGN_VHT4SS_MCS7, 165 ODM_MGN_VHT4SS_MCS8, 166 ODM_MGN_VHT4SS_MCS9 = 0xc7, 167 ODM_MGN_UNKNOWN 168 }; 169 170 #define ODM_MGN_MCS0_SG 0xc0 171 #define ODM_MGN_MCS1_SG 0xc1 172 #define ODM_MGN_MCS2_SG 0xc2 173 #define ODM_MGN_MCS3_SG 0xc3 174 #define ODM_MGN_MCS4_SG 0xc4 175 #define ODM_MGN_MCS5_SG 0xc5 176 #define ODM_MGN_MCS6_SG 0xc6 177 #define ODM_MGN_MCS7_SG 0xc7 178 #define ODM_MGN_MCS8_SG 0xc8 179 #define ODM_MGN_MCS9_SG 0xc9 180 #define ODM_MGN_MCS10_SG 0xca 181 #define ODM_MGN_MCS11_SG 0xcb 182 #define ODM_MGN_MCS12_SG 0xcc 183 #define ODM_MGN_MCS13_SG 0xcd 184 #define ODM_MGN_MCS14_SG 0xce 185 #define ODM_MGN_MCS15_SG 0xcf 186 187 /* -----DESC rate--------------------------------- */ 188 189 #define ODM_RATEMCS15_SG 0x1c 190 #define ODM_RATEMCS32 0x20 191 192 193 enum phydm_ctrl_info_rate { 194 ODM_RATE1M = 0x00, 195 ODM_RATE2M = 0x01, 196 ODM_RATE5_5M = 0x02, 197 ODM_RATE11M = 0x03, 198 /* OFDM Rates, TxHT = 0 */ 199 ODM_RATE6M = 0x04, 200 ODM_RATE9M = 0x05, 201 ODM_RATE12M = 0x06, 202 ODM_RATE18M = 0x07, 203 ODM_RATE24M = 0x08, 204 ODM_RATE36M = 0x09, 205 ODM_RATE48M = 0x0A, 206 ODM_RATE54M = 0x0B, 207 /* MCS Rates, TxHT = 1 */ 208 ODM_RATEMCS0 = 0x0C, 209 ODM_RATEMCS1 = 0x0D, 210 ODM_RATEMCS2 = 0x0E, 211 ODM_RATEMCS3 = 0x0F, 212 ODM_RATEMCS4 = 0x10, 213 ODM_RATEMCS5 = 0x11, 214 ODM_RATEMCS6 = 0x12, 215 ODM_RATEMCS7 = 0x13, 216 ODM_RATEMCS8 = 0x14, 217 ODM_RATEMCS9 = 0x15, 218 ODM_RATEMCS10 = 0x16, 219 ODM_RATEMCS11 = 0x17, 220 ODM_RATEMCS12 = 0x18, 221 ODM_RATEMCS13 = 0x19, 222 ODM_RATEMCS14 = 0x1A, 223 ODM_RATEMCS15 = 0x1B, 224 ODM_RATEMCS16 = 0x1C, 225 ODM_RATEMCS17 = 0x1D, 226 ODM_RATEMCS18 = 0x1E, 227 ODM_RATEMCS19 = 0x1F, 228 ODM_RATEMCS20 = 0x20, 229 ODM_RATEMCS21 = 0x21, 230 ODM_RATEMCS22 = 0x22, 231 ODM_RATEMCS23 = 0x23, 232 ODM_RATEMCS24 = 0x24, 233 ODM_RATEMCS25 = 0x25, 234 ODM_RATEMCS26 = 0x26, 235 ODM_RATEMCS27 = 0x27, 236 ODM_RATEMCS28 = 0x28, 237 ODM_RATEMCS29 = 0x29, 238 ODM_RATEMCS30 = 0x2A, 239 ODM_RATEMCS31 = 0x2B, 240 ODM_RATEVHTSS1MCS0 = 0x2C, 241 ODM_RATEVHTSS1MCS1 = 0x2D, 242 ODM_RATEVHTSS1MCS2 = 0x2E, 243 ODM_RATEVHTSS1MCS3 = 0x2F, 244 ODM_RATEVHTSS1MCS4 = 0x30, 245 ODM_RATEVHTSS1MCS5 = 0x31, 246 ODM_RATEVHTSS1MCS6 = 0x32, 247 ODM_RATEVHTSS1MCS7 = 0x33, 248 ODM_RATEVHTSS1MCS8 = 0x34, 249 ODM_RATEVHTSS1MCS9 = 0x35, 250 ODM_RATEVHTSS2MCS0 = 0x36, 251 ODM_RATEVHTSS2MCS1 = 0x37, 252 ODM_RATEVHTSS2MCS2 = 0x38, 253 ODM_RATEVHTSS2MCS3 = 0x39, 254 ODM_RATEVHTSS2MCS4 = 0x3A, 255 ODM_RATEVHTSS2MCS5 = 0x3B, 256 ODM_RATEVHTSS2MCS6 = 0x3C, 257 ODM_RATEVHTSS2MCS7 = 0x3D, 258 ODM_RATEVHTSS2MCS8 = 0x3E, 259 ODM_RATEVHTSS2MCS9 = 0x3F, 260 ODM_RATEVHTSS3MCS0 = 0x40, 261 ODM_RATEVHTSS3MCS1 = 0x41, 262 ODM_RATEVHTSS3MCS2 = 0x42, 263 ODM_RATEVHTSS3MCS3 = 0x43, 264 ODM_RATEVHTSS3MCS4 = 0x44, 265 ODM_RATEVHTSS3MCS5 = 0x45, 266 ODM_RATEVHTSS3MCS6 = 0x46, 267 ODM_RATEVHTSS3MCS7 = 0x47, 268 ODM_RATEVHTSS3MCS8 = 0x48, 269 ODM_RATEVHTSS3MCS9 = 0x49, 270 ODM_RATEVHTSS4MCS0 = 0x4A, 271 ODM_RATEVHTSS4MCS1 = 0x4B, 272 ODM_RATEVHTSS4MCS2 = 0x4C, 273 ODM_RATEVHTSS4MCS3 = 0x4D, 274 ODM_RATEVHTSS4MCS4 = 0x4E, 275 ODM_RATEVHTSS4MCS5 = 0x4F, 276 ODM_RATEVHTSS4MCS6 = 0x50, 277 ODM_RATEVHTSS4MCS7 = 0x51, 278 ODM_RATEVHTSS4MCS8 = 0x52, 279 ODM_RATEVHTSS4MCS9 = 0x53, 280 }; 281 282 #define CCK_RATE_NUM 4 283 #define OFDM_RATE_NUM 8 284 285 #define LEGACY_RATE_NUM 12 286 287 #define HT_RATE_NUM 32 288 #define VHT_RATE_NUM 40 289 290 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 291 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) 292 #else 293 #if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) 294 #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1) 295 #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) 296 #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1) 297 #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) 298 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1) 299 #elif (RTL8812A_SUPPORT == 1) 300 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1) 301 #elif (RTL8814A_SUPPORT == 1) 302 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1) 303 #else 304 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) 305 #endif 306 #endif 307 308 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 309 #define CONFIG_SFW_SUPPORTED 310 #endif 311 312 /* 1 ============================================================ 313 * 1 enumeration 314 * 1 ============================================================ */ 315 316 317 /* ODM_CMNINFO_INTERFACE */ 318 enum odm_interface_e { 319 ODM_ITRF_PCIE = 0x1, 320 ODM_ITRF_USB = 0x2, 321 ODM_ITRF_SDIO = 0x4, 322 ODM_ITRF_ALL = 0x7, 323 }; 324 325 326 enum phydm_ic_e { 327 ODM_RTL8188E = BIT(0), 328 ODM_RTL8812 = BIT(1), 329 ODM_RTL8821 = BIT(2), 330 ODM_RTL8192E = BIT(3), 331 ODM_RTL8723B = BIT(4), 332 ODM_RTL8814A = BIT(5), 333 ODM_RTL8881A = BIT(6), 334 ODM_RTL8822B = BIT(7), 335 ODM_RTL8703B = BIT(8), 336 ODM_RTL8195A = BIT(9), 337 ODM_RTL8188F = BIT(10), 338 ODM_RTL8723D = BIT(11), 339 ODM_RTL8197F = BIT(12), 340 ODM_RTL8821C = BIT(13), 341 ODM_RTL8814B = BIT(14), 342 ODM_RTL8198F = BIT(15), 343 ODM_RTL8710B = BIT(16), 344 ODM_RTL8192F = BIT(17), 345 ODM_RTL8822C = BIT(18) 346 }; 347 348 /*========[Run time IC flag] ===============================================================================]*/ 349 350 #define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A | ODM_RTL8710B) 351 #define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F) 352 #define ODM_IC_N_3SS 0 353 #define ODM_IC_N_4SS (ODM_RTL8198F) 354 355 #define ODM_IC_AC_1SS (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C) 356 #define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8822C) 357 #define ODM_IC_AC_3SS 0 358 #define ODM_IC_AC_4SS (ODM_RTL8814A | ODM_RTL8814B) 359 360 /*====the following macro DO NOT need to update when add a new IC======= */ 361 #define ODM_IC_1SS (ODM_IC_N_1SS | ODM_IC_AC_1SS) 362 #define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS) 363 #define ODM_IC_3SS (ODM_IC_N_3SS | ODM_IC_AC_3SS) 364 #define ODM_IC_4SS (ODM_IC_N_4SS | ODM_IC_AC_4SS) 365 366 #define PHYDM_IC_ABOVE_1SS (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) 367 #define PHYDM_IC_ABOVE_2SS (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) 368 #define PHYDM_IC_ABOVE_3SS (ODM_IC_3SS | ODM_IC_4SS) 369 #define PHYDM_IC_ABOVE_4SS ODM_IC_4SS 370 371 #define ODM_IC_11N_SERIES (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS | ODM_IC_N_4SS) 372 #define ODM_IC_11AC_SERIES (ODM_IC_AC_1SS | ODM_IC_AC_2SS | ODM_IC_AC_3SS | ODM_IC_AC_4SS) 373 /*====================================================*/ 374 375 #define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) 376 #define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) 377 378 #define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) 379 380 #define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) 381 #define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) 382 #define ODM_IC_GAIN_IDX_EDCCA (ODM_IC_11N_GAIN_IDX_EDCCA | ODM_IC_11AC_GAIN_IDX_EDCCA) 383 384 #define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B) 385 386 #define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F) 387 #define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) 388 389 #define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) 390 #define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B) 391 #define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B) 392 393 394 /*========[Compile time IC flag] ===============================================================================]*/ 395 /*========[AC/N Support] ===========================*/ 396 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 397 398 #ifdef RTK_AC_SUPPORT 399 #define ODM_IC_11AC_SERIES_SUPPORT 1 400 #else 401 #define ODM_IC_11AC_SERIES_SUPPORT 0 402 #endif 403 404 #define ODM_IC_11N_SERIES_SUPPORT 1 405 406 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 407 408 #define ODM_IC_11AC_SERIES_SUPPORT 1 409 #define ODM_IC_11N_SERIES_SUPPORT 1 410 411 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) 412 413 #define ODM_IC_11AC_SERIES_SUPPORT 1 414 #define ODM_IC_11N_SERIES_SUPPORT 1 415 416 #else /*ODM_CE*/ 417 418 #if ((RTL8188E_SUPPORT == 1) || \ 419 (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ 420 (RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) 421 #define ODM_IC_11N_SERIES_SUPPORT 1 422 #define ODM_IC_11AC_SERIES_SUPPORT 0 423 #else 424 #define ODM_IC_11N_SERIES_SUPPORT 0 425 #define ODM_IC_11AC_SERIES_SUPPORT 1 426 #endif 427 #endif 428 429 /*===IC SS Compile Flag, prepare for code size reduction==============*/ 430 #if ((RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) ||\ 431 (RTL8723D_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\ 432 (RTL8195A_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) 433 434 #define PHYDM_COMPILE_IC_1SS 435 #endif 436 437 #if ((RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) 438 #define PHYDM_COMPILE_IC_2SS 439 #endif 440 441 /*#define PHYDM_COMPILE_IC_3SS*/ 442 443 #if ((RTL8814B_SUPPORT == 1) || (RTL8814A_SUPPORT == 1)) 444 #define PHYDM_COMPILE_IC_4SS 445 #endif 446 447 /*==[ABOVE N-SS COMPILE FLAG]=============================*/ 448 #if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) 449 #define PHYDM_COMPILE_ABOVE_1SS 450 #endif 451 452 #if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) 453 #define PHYDM_COMPILE_ABOVE_2SS 454 #endif 455 456 #if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) 457 #define PHYDM_COMPILE_ABOVE_3SS 458 #endif 459 460 #if (defined(PHYDM_COMPILE_IC_4SS)) 461 #define PHYDM_COMPILE_ABOVE_4SS 462 #endif 463 464 /*========[New Phy-Status Support] =========================================================================]*/ 465 #if (RTL8824B_SUPPORT == 1) 466 #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 2 467 #elif ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1) ) 468 #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 469 #else 470 #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 471 #endif 472 473 /*==================================================================================================]*/ 474 475 #if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) 476 #define PHYDM_COMMON_API_SUPPORT 477 #endif 478 479 /* ODM_CMNINFO_CUT_VER */ 480 enum odm_cut_version_e { 481 ODM_CUT_A = 0, 482 ODM_CUT_B = 1, 483 ODM_CUT_C = 2, 484 ODM_CUT_D = 3, 485 ODM_CUT_E = 4, 486 ODM_CUT_F = 5, 487 ODM_CUT_G = 6, 488 ODM_CUT_H = 7, 489 ODM_CUT_I = 8, 490 ODM_CUT_J = 9, 491 ODM_CUT_K = 10, 492 ODM_CUT_TEST = 15, 493 }; 494 495 /* ODM_CMNINFO_FAB_VER */ 496 enum odm_fab_e { 497 ODM_TSMC = 0, 498 ODM_UMC = 1, 499 }; 500 501 /* ODM_CMNINFO_OP_MODE */ 502 enum odm_operation_mode_e { 503 ODM_NO_LINK = BIT(0), 504 ODM_LINK = BIT(1), 505 ODM_SCAN = BIT(2), 506 ODM_POWERSAVE = BIT(3), 507 ODM_AP_MODE = BIT(4), 508 ODM_CLIENT_MODE = BIT(5), 509 ODM_AD_HOC = BIT(6), 510 ODM_WIFI_DIRECT = BIT(7), 511 ODM_WIFI_DISPLAY = BIT(8), 512 }; 513 514 /* ODM_CMNINFO_WM_MODE */ 515 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 516 enum odm_wireless_mode_e { 517 ODM_WM_UNKNOW = 0x0, 518 ODM_WM_B = BIT(0), 519 ODM_WM_G = BIT(1), 520 ODM_WM_A = BIT(2), 521 ODM_WM_N24G = BIT(3), 522 ODM_WM_N5G = BIT(4), 523 ODM_WM_AUTO = BIT(5), 524 ODM_WM_AC = BIT(6), 525 }; 526 #else 527 enum odm_wireless_mode_e { 528 ODM_WM_UNKNOWN = 0x00,/*0x0*/ 529 ODM_WM_A = BIT(0), /* 0x1*/ 530 ODM_WM_B = BIT(1), /* 0x2*/ 531 ODM_WM_G = BIT(2),/* 0x4*/ 532 ODM_WM_AUTO = BIT(3),/* 0x8*/ 533 ODM_WM_N24G = BIT(4),/* 0x10*/ 534 ODM_WM_N5G = BIT(5),/* 0x20*/ 535 ODM_WM_AC_5G = BIT(6),/* 0x40*/ 536 ODM_WM_AC_24G = BIT(7),/* 0x80*/ 537 ODM_WM_AC_ONLY = BIT(8),/* 0x100*/ 538 ODM_WM_MAX = BIT(11)/* 0x800*/ 539 540 }; 541 #endif 542 543 /* ODM_CMNINFO_BAND */ 544 enum odm_band_type_e { 545 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 546 ODM_BAND_2_4G = BIT(0), 547 ODM_BAND_5G = BIT(1), 548 #else 549 ODM_BAND_2_4G = 0, 550 ODM_BAND_5G, 551 ODM_BAND_ON_BOTH, 552 ODM_BANDMAX 553 #endif 554 }; 555 556 557 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 558 enum phydm_sec_chnl_offset_e { 559 560 PHYDM_DONT_CARE = 0, 561 PHYDM_BELOW = 1, 562 PHYDM_ABOVE = 2 563 }; 564 565 /* ODM_CMNINFO_SEC_MODE */ 566 enum odm_security_e { 567 ODM_SEC_OPEN = 0, 568 ODM_SEC_WEP40 = 1, 569 ODM_SEC_TKIP = 2, 570 ODM_SEC_RESERVE = 3, 571 ODM_SEC_AESCCMP = 4, 572 ODM_SEC_WEP104 = 5, 573 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 574 ODM_SEC_SMS4 = 7, 575 }; 576 577 /* ODM_CMNINFO_CHNL */ 578 579 /* ODM_CMNINFO_BOARD_TYPE */ 580 enum odm_board_type_e { 581 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ 582 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */ 583 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ 584 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ 585 ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ 586 ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ 587 ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ 588 ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ 589 ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ 590 }; 591 592 enum odm_package_type_e { 593 ODM_PACKAGE_DEFAULT = 0, 594 ODM_PACKAGE_QFN68 = BIT(0), 595 ODM_PACKAGE_TFBGA90 = BIT(1), 596 ODM_PACKAGE_TFBGA79 = BIT(2), 597 }; 598 599 enum odm_type_gpa_e { 600 TYPE_GPA0 = 0x0000, 601 TYPE_GPA1 = 0x0055, 602 TYPE_GPA2 = 0x00AA, 603 TYPE_GPA3 = 0x00FF, 604 TYPE_GPA4 = 0x5500, 605 TYPE_GPA5 = 0x5555, 606 TYPE_GPA6 = 0x55AA, 607 TYPE_GPA7 = 0x55FF, 608 TYPE_GPA8 = 0xAA00, 609 TYPE_GPA9 = 0xAA55, 610 TYPE_GPA10 = 0xAAAA, 611 TYPE_GPA11 = 0xAAFF, 612 TYPE_GPA12 = 0xFF00, 613 TYPE_GPA13 = 0xFF55, 614 TYPE_GPA14 = 0xFFAA, 615 TYPE_GPA15 = 0xFFFF, 616 }; 617 618 enum odm_type_apa_e { 619 TYPE_APA0 = 0x0000, 620 TYPE_APA1 = 0x0055, 621 TYPE_APA2 = 0x00AA, 622 TYPE_APA3 = 0x00FF, 623 TYPE_APA4 = 0x5500, 624 TYPE_APA5 = 0x5555, 625 TYPE_APA6 = 0x55AA, 626 TYPE_APA7 = 0x55FF, 627 TYPE_APA8 = 0xAA00, 628 TYPE_APA9 = 0xAA55, 629 TYPE_APA10 = 0xAAAA, 630 TYPE_APA11 = 0xAAFF, 631 TYPE_APA12 = 0xFF00, 632 TYPE_APA13 = 0xFF55, 633 TYPE_APA14 = 0xFFAA, 634 TYPE_APA15 = 0xFFFF, 635 }; 636 637 enum odm_type_glna_e { 638 TYPE_GLNA0 = 0x0000, 639 TYPE_GLNA1 = 0x0055, 640 TYPE_GLNA2 = 0x00AA, 641 TYPE_GLNA3 = 0x00FF, 642 TYPE_GLNA4 = 0x5500, 643 TYPE_GLNA5 = 0x5555, 644 TYPE_GLNA6 = 0x55AA, 645 TYPE_GLNA7 = 0x55FF, 646 TYPE_GLNA8 = 0xAA00, 647 TYPE_GLNA9 = 0xAA55, 648 TYPE_GLNA10 = 0xAAAA, 649 TYPE_GLNA11 = 0xAAFF, 650 TYPE_GLNA12 = 0xFF00, 651 TYPE_GLNA13 = 0xFF55, 652 TYPE_GLNA14 = 0xFFAA, 653 TYPE_GLNA15 = 0xFFFF, 654 }; 655 656 enum odm_type_alna_e { 657 TYPE_ALNA0 = 0x0000, 658 TYPE_ALNA1 = 0x0055, 659 TYPE_ALNA2 = 0x00AA, 660 TYPE_ALNA3 = 0x00FF, 661 TYPE_ALNA4 = 0x5500, 662 TYPE_ALNA5 = 0x5555, 663 TYPE_ALNA6 = 0x55AA, 664 TYPE_ALNA7 = 0x55FF, 665 TYPE_ALNA8 = 0xAA00, 666 TYPE_ALNA9 = 0xAA55, 667 TYPE_ALNA10 = 0xAAAA, 668 TYPE_ALNA11 = 0xAAFF, 669 TYPE_ALNA12 = 0xFF00, 670 TYPE_ALNA13 = 0xFF55, 671 TYPE_ALNA14 = 0xFFAA, 672 TYPE_ALNA15 = 0xFFFF, 673 }; 674 675 #define PAUSE_FAIL 0 676 #define PAUSE_SUCCESS 1 677 678 enum odm_parameter_init_e { 679 ODM_PRE_SETTING = 0, 680 ODM_POST_SETTING = 1, 681 ODM_INIT_FW_SETTING 682 }; 683 684 685 enum phydm_pause_type { 686 PHYDM_PAUSE = 1, /*Pause & Set new value*/ 687 PHYDM_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/ 688 PHYDM_RESUME = 3 689 }; 690 691 enum phydm_pause_level { 692 PHYDM_PAUSE_RELEASE = -1, 693 PHYDM_PAUSE_LEVEL_0 = 0, /* Low Priority function */ 694 PHYDM_PAUSE_LEVEL_1 = 1, /* Middle Priority function */ 695 PHYDM_PAUSE_LEVEL_2 = 2, /* High priority function (ex: Check hang function) */ 696 PHYDM_PAUSE_LEVEL_3 = 3, /* Debug function (the highest priority) */ 697 PHYDM_PAUSE_MAX_NUM = 4 698 }; 699 700 701 #endif 702