1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 22 #ifndef __HALDMOUTSRC_H__ 23 #define __HALDMOUTSRC_H__ 24 25 //============================================================ 26 // include files 27 //============================================================ 28 #include "phydm_pre_define.h" 29 #include "phydm_dig.h" 30 #include "phydm_edcaturbocheck.h" 31 #include "phydm_pathdiv.h" 32 #include "phydm_antdiv.h" 33 #include "phydm_antdect.h" 34 #include "phydm_dynamicbbpowersaving.h" 35 #include "phydm_rainfo.h" 36 #include "phydm_dynamictxpower.h" 37 #include "phydm_cfotracking.h" 38 #include "phydm_acs.h" 39 #include "phydm_adaptivity.h" 40 #include "phydm_iqk.h" 41 #include "phydm_dfs.h" 42 #include "phydm_ccx.h" 43 #include "txbf/phydm_hal_txbf_api.h" 44 45 #include "phydm_adc_sampling.h" 46 47 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 48 #include "phydm_beamforming.h" 49 #endif 50 51 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 52 #include "halphyrf_ap.h" 53 #endif 54 55 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 56 #include "phydm_noisemonitor.h" 57 #include "halphyrf_ce.h" 58 #endif 59 60 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 61 #include "halphyrf_win.h" 62 #include "phydm_noisemonitor.h" 63 #endif 64 65 //============================================================ 66 // Definition 67 //============================================================ 68 // 69 // 2011/09/22 MH Define all team supprt ability. 70 // 71 72 /* Traffic load decision */ 73 #define TRAFFIC_ULTRA_LOW 1 74 #define TRAFFIC_LOW 2 75 #define TRAFFIC_MID 3 76 #define TRAFFIC_HIGH 4 77 78 #define NONE 0 79 80 /*NBI API------------------------------------*/ 81 #define NBI_ENABLE 1 82 #define NBI_DISABLE 2 83 84 #define NBI_TABLE_SIZE_128 27 85 #define NBI_TABLE_SIZE_256 59 86 87 #define NUM_START_CH_80M 7 88 #define NUM_START_CH_40M 14 89 90 #define CH_OFFSET_40M 2 91 #define CH_OFFSET_80M 6 92 93 /*CSI MASK API------------------------------------*/ 94 #define CSI_MASK_ENABLE 1 95 #define CSI_MASK_DISABLE 2 96 97 /*------------------------------------------------*/ 98 99 #define FFT_128_TYPE 1 100 #define FFT_256_TYPE 2 101 102 #define SET_SUCCESS 1 103 #define SET_ERROR 2 104 #define SET_NO_NEED 3 105 106 #define FREQ_POSITIVE 1 107 #define FREQ_NEGATIVE 2 108 109 110 111 //============================================================ 112 // structure and define 113 //============================================================ 114 115 // 116 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. 117 // We need to remove to other position??? 118 // 119 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 120 typedef struct rtl8192cd_priv { 121 u1Byte temp; 122 123 }rtl8192cd_priv, *prtl8192cd_priv; 124 #endif 125 126 127 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 128 typedef struct _ADAPTER{ 129 u1Byte temp; 130 #ifdef AP_BUILD_WORKAROUND 131 HAL_DATA_TYPE* temp2; 132 prtl8192cd_priv priv; 133 #endif 134 }ADAPTER, *PADAPTER; 135 #endif 136 137 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 138 139 typedef struct _WLAN_STA{ 140 u1Byte temp; 141 } WLAN_STA, *PRT_WLAN_STA; 142 143 #endif 144 145 typedef struct _Dynamic_Primary_CCA{ 146 u1Byte PriCCA_flag; 147 u1Byte intf_flag; 148 u1Byte intf_type; 149 u1Byte DupRTS_flag; 150 u1Byte Monitor_flag; 151 u1Byte CH_offset; 152 u1Byte MF_state; 153 }Pri_CCA_T, *pPri_CCA_T; 154 155 156 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 157 #ifdef ADSL_AP_BUILD_WORKAROUND 158 #define MAX_TOLERANCE 5 159 #define IQK_DELAY_TIME 1 /*ms*/ 160 #endif 161 #endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ 162 163 #define DM_Type_ByFW 0 164 #define DM_Type_ByDriver 1 165 166 // 167 // Declare for common info 168 // 169 170 #define IQK_THRESHOLD 8 171 #define DPK_THRESHOLD 4 172 173 174 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 175 __PACK typedef struct _ODM_Phy_Status_Info_ 176 { 177 u1Byte RxPWDBAll; 178 u1Byte SignalQuality; /* in 0-100 index. */ 179 u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ 180 s1Byte RxMIMOSignalQuality[4]; /* EVM */ 181 s1Byte RxSNR[4]; /* per-path's SNR */ 182 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 183 u1Byte RxCount:2; /* RX path counter---*/ 184 u1Byte BandWidth:2; 185 u1Byte rxsc:4; /* sub-channel---*/ 186 #else 187 u1Byte BandWidth; 188 #endif 189 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 190 u1Byte channel; /* channel number---*/ 191 BOOLEAN bMuPacket; /* is MU packet or not---*/ 192 BOOLEAN bBeamformed; /* BF packet---*/ 193 #endif 194 } __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; 195 196 typedef struct _ODM_Phy_Status_Info_Append_ 197 { 198 u1Byte MAC_CRC32; 199 200 }ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; 201 202 #else 203 204 typedef struct _ODM_Phy_Status_Info_ 205 { 206 // 207 // Be care, if you want to add any element please insert between 208 // RxPWDBAll & SignalStrength. 209 // 210 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 211 u4Byte RxPWDBAll; 212 #else 213 u1Byte RxPWDBAll; 214 #endif 215 u1Byte SignalQuality; /* in 0-100 index. */ 216 s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ 217 u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ 218 u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ 219 s2Byte Cfo_short[4]; /* per-path's Cfo_short */ 220 s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ 221 s1Byte RxPower; /* in dBm Translate from PWdB */ 222 s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ 223 u1Byte BTRxRSSIPercentage; 224 u1Byte SignalStrength; /* in 0-100 index. */ 225 s1Byte RxPwr[4]; /* per-path's pwdb */ 226 s1Byte RxSNR[4]; /* per-path's SNR */ 227 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 228 u1Byte RxCount:2; /* RX path counter---*/ 229 u1Byte BandWidth:2; 230 u1Byte rxsc:4; /* sub-channel---*/ 231 #else 232 u1Byte BandWidth; 233 #endif 234 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 235 u1Byte btCoexPwrAdjust; 236 #endif 237 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 238 u1Byte channel; /* channel number---*/ 239 BOOLEAN bMuPacket; /* is MU packet or not---*/ 240 BOOLEAN bBeamformed; /* BF packet---*/ 241 #endif 242 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T; 243 #endif 244 245 typedef struct _ODM_Per_Pkt_Info_ 246 { 247 //u1Byte Rate; 248 u1Byte DataRate; 249 u1Byte StationID; 250 BOOLEAN bPacketMatchBSSID; 251 BOOLEAN bPacketToSelf; 252 BOOLEAN bPacketBeacon; 253 BOOLEAN bToSelf; 254 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; 255 256 257 typedef struct _ODM_Phy_Dbg_Info_ 258 { 259 //ODM Write,debug info 260 s1Byte RxSNRdB[4]; 261 u4Byte NumQryPhyStatus; 262 u4Byte NumQryPhyStatusCCK; 263 u4Byte NumQryPhyStatusOFDM; 264 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 265 u4Byte NumQryMuPkt; 266 u4Byte NumQryBfPkt; 267 u4Byte NumQryMuVhtPkt[40]; 268 u4Byte NumQryVhtPkt[40]; 269 #endif 270 u1Byte NumQryBeaconPkt; 271 //Others 272 s4Byte RxEVM[4]; 273 274 }ODM_PHY_DBG_INFO_T; 275 276 277 typedef struct _ODM_Mac_Status_Info_ 278 { 279 u1Byte test; 280 281 }ODM_MAC_INFO; 282 283 // 284 // 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T 285 // Please declare below ODM relative info in your STA info structure. 286 // 287 #if 1 288 typedef struct _ODM_STA_INFO{ 289 // Driver Write 290 BOOLEAN bUsed; // record the sta status link or not? 291 //u1Byte WirelessMode; // 292 u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E 293 294 // ODM Write 295 //1 PHY_STATUS_INFO 296 u1Byte RSSI_Path[4]; // 297 u1Byte RSSI_Ave; 298 u1Byte RXEVM[4]; 299 u1Byte RXSNR[4]; 300 301 // ODM Write 302 //1 TX_INFO (may changed by IC) 303 //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. 304 #if 0 305 u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit 306 u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit 307 u1Byte ANTSEL_C; //only in Jagar: 4bit 308 u1Byte ANTSEL_D; //only in Jagar: 4bit 309 u1Byte TX_ANTL; //not in Jagar: 2bit 310 u1Byte TX_ANT_HT; //not in Jagar: 2bit 311 u1Byte TX_ANT_CCK; //not in Jagar: 2bit 312 u1Byte TXAGC_A; //not in Jagar: 4bit 313 u1Byte TXAGC_B; //not in Jagar: 4bit 314 u1Byte TXPWR_OFFSET; //only in Jagar: 3bit 315 u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK 316 #endif 317 318 // 319 // Please use compile flag to disabe the strcutrue for other IC except 88E. 320 // Move To lower layer. 321 // 322 // ODM Write Wilson will handle this part(said by Luke.Lee) 323 //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. 324 #if 0 325 //1 For 88E RA (don't redefine the naming) 326 u1Byte rate_id; 327 u1Byte rate_SGI; 328 u1Byte rssi_sta_ra; 329 u1Byte SGI_enable; 330 u1Byte Decision_rate; 331 u1Byte Pre_rate; 332 u1Byte Active; 333 334 // Driver write Wilson handle. 335 //1 TX_RPT (don't redefine the naming) 336 u2Byte RTY[4]; // ??? 337 u2Byte TOTAL; // ??? 338 u2Byte DROP; // ??? 339 // 340 // Please use compile flag to disabe the strcutrue for other IC except 88E. 341 // 342 #endif 343 344 }ODM_STA_INFO_T, *PODM_STA_INFO_T; 345 #endif 346 347 // 348 // 2011/10/20 MH Define Common info enum for all team. 349 // 350 typedef enum _ODM_Common_Info_Definition 351 { 352 //-------------REMOVED CASE-----------// 353 //ODM_CMNINFO_CCK_HP, 354 //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? 355 //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E 356 //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E 357 //-------------REMOVED CASE-----------// 358 359 // 360 // Fixed value: 361 // 362 363 //-----------HOOK BEFORE REG INIT-----------// 364 ODM_CMNINFO_PLATFORM = 0, 365 ODM_CMNINFO_ABILITY, // ODM_ABILITY_E 366 ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E 367 ODM_CMNINFO_MP_TEST_CHIP, 368 ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E 369 ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E 370 ODM_CMNINFO_FAB_VER, // ODM_FAB_E 371 ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? 372 ODM_CMNINFO_RFE_TYPE, 373 ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E 374 ODM_CMNINFO_PACKAGE_TYPE, 375 ODM_CMNINFO_EXT_LNA, // TRUE 376 ODM_CMNINFO_5G_EXT_LNA, 377 ODM_CMNINFO_EXT_PA, 378 ODM_CMNINFO_5G_EXT_PA, 379 ODM_CMNINFO_GPA, 380 ODM_CMNINFO_APA, 381 ODM_CMNINFO_GLNA, 382 ODM_CMNINFO_ALNA, 383 ODM_CMNINFO_EXT_TRSW, 384 ODM_CMNINFO_EXT_LNA_GAIN, 385 ODM_CMNINFO_PATCH_ID, //CUSTOMER ID 386 ODM_CMNINFO_BINHCT_TEST, 387 ODM_CMNINFO_BWIFI_TEST, 388 ODM_CMNINFO_SMART_CONCURRENT, 389 ODM_CMNINFO_CONFIG_BB_RF, 390 ODM_CMNINFO_DOMAIN_CODE_2G, 391 ODM_CMNINFO_DOMAIN_CODE_5G, 392 ODM_CMNINFO_IQKFWOFFLOAD, 393 ODM_CMNINFO_IQKPAOFF, 394 ODM_CMNINFO_HUBUSBMODE, 395 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 396 ODM_CMNINFO_TX_TP, 397 ODM_CMNINFO_RX_TP, 398 ODM_CMNINFO_SOUNDING_SEQ, 399 ODM_CMNINFO_REGRFKFREEENABLE, 400 ODM_CMNINFO_RFKFREEENABLE, 401 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 402 /*-----------HOOK BEFORE REG INIT-----------*/ 403 404 405 // 406 // Dynamic value: 407 // 408 //--------- POINTER REFERENCE-----------// 409 ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E 410 ODM_CMNINFO_TX_UNI, 411 ODM_CMNINFO_RX_UNI, 412 ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E 413 ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E 414 ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E 415 ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E 416 ODM_CMNINFO_BW, // ODM_BW_E 417 ODM_CMNINFO_CHNL, 418 ODM_CMNINFO_FORCED_RATE, 419 420 ODM_CMNINFO_DMSP_GET_VALUE, 421 ODM_CMNINFO_BUDDY_ADAPTOR, 422 ODM_CMNINFO_DMSP_IS_MASTER, 423 ODM_CMNINFO_SCAN, 424 ODM_CMNINFO_POWER_SAVING, 425 ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E 426 ODM_CMNINFO_DRV_STOP, 427 ODM_CMNINFO_PNP_IN, 428 ODM_CMNINFO_INIT_ON, 429 ODM_CMNINFO_ANT_TEST, 430 ODM_CMNINFO_NET_CLOSED, 431 //ODM_CMNINFO_RTSTA_AID, // For win driver only? 432 ODM_CMNINFO_FORCED_IGI_LB, 433 ODM_CMNINFO_P2P_LINK, 434 ODM_CMNINFO_FCS_MODE, 435 ODM_CMNINFO_IS1ANTENNA, 436 ODM_CMNINFO_RFDEFAULTPATH, 437 ODM_CMNINFO_DFS_MASTER_ENABLE, 438 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 439 //--------- POINTER REFERENCE-----------// 440 441 //------------CALL BY VALUE-------------// 442 ODM_CMNINFO_WIFI_DIRECT, 443 ODM_CMNINFO_WIFI_DISPLAY, 444 ODM_CMNINFO_LINK_IN_PROGRESS, 445 ODM_CMNINFO_LINK, 446 ODM_CMNINFO_STATION_STATE, 447 ODM_CMNINFO_RSSI_MIN, 448 ODM_CMNINFO_DBG_COMP, /* u4SByte*/ 449 ODM_CMNINFO_DBG_LEVEL, /* u4Byte*/ 450 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u1Byte*/ 451 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u1Byte*/ 452 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u1Byte*/ 453 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 454 ODM_CMNINFO_BE_FIX_TX_ANT, 455 ODM_CMNINFO_BT_ENABLED, 456 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 457 ODM_CMNINFO_BT_HS_RSSI, 458 ODM_CMNINFO_BT_OPERATION, 459 ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not 460 ODM_CMNINFO_BT_DIG, 461 ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil 462 ODM_CMNINFO_BT_DISABLE_EDCA, 463 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 464 #ifdef UNIVERSAL_REPEATER 465 ODM_CMNINFO_VXD_LINK, 466 #endif 467 #endif 468 ODM_CMNINFO_AP_TOTAL_NUM, 469 ODM_CMNINFO_POWER_TRAINING, 470 ODM_CMNINFO_DFS_REGION_DOMAIN, 471 //------------CALL BY VALUE-------------// 472 473 // 474 // Dynamic ptr array hook itms. 475 // 476 ODM_CMNINFO_STA_STATUS, 477 ODM_CMNINFO_PHY_STATUS, 478 ODM_CMNINFO_MAC_STATUS, 479 480 ODM_CMNINFO_MAX, 481 482 483 }ODM_CMNINFO_E; 484 485 typedef enum _PHYDM_API_Definition { 486 487 PHYDM_API_NBI = 1, 488 PHYDM_API_CSI_MASK, 489 490 491 } PHYDM_API_E; 492 493 494 // 495 // 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY 496 // 497 typedef enum _ODM_Support_Ability_Definition 498 { 499 // 500 // BB ODM section BIT 0-19 501 // 502 ODM_BB_DIG = BIT0, 503 ODM_BB_RA_MASK = BIT1, 504 ODM_BB_DYNAMIC_TXPWR = BIT2, 505 ODM_BB_FA_CNT = BIT3, 506 ODM_BB_RSSI_MONITOR = BIT4, 507 ODM_BB_CCK_PD = BIT5, 508 ODM_BB_ANT_DIV = BIT6, 509 ODM_BB_PWR_TRAIN = BIT8, 510 ODM_BB_RATE_ADAPTIVE = BIT9, 511 ODM_BB_PATH_DIV = BIT10, 512 ODM_BB_ADAPTIVITY = BIT13, 513 ODM_BB_CFO_TRACKING = BIT14, 514 ODM_BB_NHM_CNT = BIT15, 515 ODM_BB_PRIMARY_CCA = BIT16, 516 ODM_BB_TXBF = BIT17, 517 ODM_BB_DYNAMIC_ARFR = BIT18, 518 519 // 520 // MAC DM section BIT 20-23 521 // 522 ODM_MAC_EDCA_TURBO = BIT20, 523 ODM_MAC_EARLY_MODE = BIT21, 524 525 // 526 // RF ODM section BIT 24-31 527 // 528 ODM_RF_TX_PWR_TRACK = BIT24, 529 ODM_RF_RX_GAIN_TRACK = BIT25, 530 ODM_RF_CALIBRATION = BIT26, 531 532 }ODM_ABILITY_E; 533 534 535 // ODM_CMNINFO_ONE_PATH_CCA 536 typedef enum tag_CCA_Path 537 { 538 ODM_CCA_2R = 0, 539 ODM_CCA_1R_A = 1, 540 ODM_CCA_1R_B = 2, 541 }ODM_CCA_PATH_E; 542 543 typedef enum CCA_PATHDIV_EN { 544 CCA_PATHDIV_DISABLE = 0, 545 CCA_PATHDIV_ENABLE = 1, 546 547 } CCA_PATHDIV_EN_E; 548 549 550 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ 551 PHY_REG_PG_RELATIVE_VALUE = 0, 552 PHY_REG_PG_EXACT_VALUE = 1 553 } PHY_REG_PG_TYPE; 554 555 // 556 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. 557 // 558 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) 559 #if (RT_PLATFORM != PLATFORM_LINUX) 560 typedef 561 #endif 562 563 struct DM_Out_Source_Dynamic_Mechanism_Structure 564 #else// for AP,ADSL,CE Team 565 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure 566 #endif 567 { 568 // Add for different team use temporarily 569 // 570 PADAPTER Adapter; // For CE/NIC team 571 prtl8192cd_priv priv; // For AP/ADSL team 572 // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. 573 BOOLEAN odm_ready; 574 575 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 576 rtl8192cd_priv fake_priv; 577 #endif 578 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 579 // ADSL_AP_BUILD_WORKAROUND 580 ADAPTER fake_adapter; 581 #endif 582 583 PHY_REG_PG_TYPE PhyRegPgValueType; 584 u1Byte PhyRegPgVersion; 585 586 u4Byte DebugComponents; 587 u4Byte DebugLevel; 588 589 u4Byte NumQryPhyStatusAll; //CCK + OFDM 590 u4Byte LastNumQryPhyStatusAll; 591 u4Byte RxPWDBAve; 592 BOOLEAN MPDIG_2G; //off MPDIG 593 u1Byte Times_2G; 594 BOOLEAN bInitHwInfoByRfe; 595 596 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// 597 BOOLEAN bCckHighPower; 598 u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE 599 u1Byte ControlChannel; 600 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// 601 602 //--------REMOVED COMMON INFO----------// 603 //u1Byte PseudoMacPhyMode; 604 //BOOLEAN *BTCoexist; 605 //BOOLEAN PseudoBtCoexist; 606 //u1Byte OPMode; 607 //BOOLEAN bAPMode; 608 //BOOLEAN bClientMode; 609 //BOOLEAN bAdHocMode; 610 //BOOLEAN bSlaveOfDMSP; 611 //--------REMOVED COMMON INFO----------// 612 613 614 //1 COMMON INFORMATION 615 616 // 617 // Init Value 618 // 619 //-----------HOOK BEFORE REG INIT-----------// 620 // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 621 u1Byte SupportPlatform; 622 // ODM Platform info WIN/AP/CE = 1/2/3 623 u1Byte Normalrxpath; 624 // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K 625 u4Byte SupportAbility; 626 // ODM PCIE/USB/SDIO = 1/2/3 627 u1Byte SupportInterface; 628 // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... 629 u4Byte SupportICType; 630 // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... 631 u1Byte CutVersion; 632 // Fab Version TSMC/UMC = 0/1 633 u1Byte FabVersion; 634 // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... 635 u1Byte RFType; 636 u1Byte RFEType; 637 // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... 638 u1Byte BoardType; 639 u1Byte PackageType; 640 u2Byte TypeGLNA; 641 u2Byte TypeGPA; 642 u2Byte TypeALNA; 643 u2Byte TypeAPA; 644 // with external LNA NO/Yes = 0/1 645 u1Byte ExtLNA; // 2G 646 u1Byte ExtLNA5G; //5G 647 // with external PA NO/Yes = 0/1 648 u1Byte ExtPA; // 2G 649 u1Byte ExtPA5G; //5G 650 // with external TRSW NO/Yes = 0/1 651 u1Byte ExtTRSW; 652 u1Byte ExtLNAGain; // 2G 653 u1Byte PatchID; //Customer ID 654 BOOLEAN bInHctTest; 655 u1Byte WIFITest; 656 657 BOOLEAN bDualMacSmartConcurrent; 658 u4Byte BK_SupportAbility; 659 u1Byte AntDivType; 660 u1Byte with_extenal_ant_switch; 661 BOOLEAN ConfigBBRF; 662 u1Byte odm_Regulation2_4G; 663 u1Byte odm_Regulation5G; 664 u1Byte IQKFWOffload; 665 BOOLEAN cck_new_agc; 666 //-----------HOOK BEFORE REG INIT-----------// 667 668 // 669 // Dynamic Value 670 // 671 //--------- POINTER REFERENCE-----------// 672 673 u1Byte u1Byte_temp; 674 BOOLEAN BOOLEAN_temp; 675 PADAPTER PADAPTER_temp; 676 677 // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 678 u1Byte *pMacPhyMode; 679 //TX Unicast byte count 680 u8Byte *pNumTxBytesUnicast; 681 //RX Unicast byte count 682 u8Byte *pNumRxBytesUnicast; 683 // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 684 u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E 685 // Frequence band 2.4G/5G = 0/1 686 u1Byte *pBandType; 687 // Secondary channel offset don't_care/below/above = 0/1/2 688 u1Byte *pSecChOffset; 689 // Security mode Open/WEP/AES/TKIP = 0/1/2/3 690 u1Byte *pSecurity; 691 // BW info 20M/40M/80M = 0/1/2 692 u1Byte *pBandWidth; 693 // Central channel location Ch1/Ch2/.... 694 u1Byte *pChannel; //central channel number 695 BOOLEAN DPK_Done; 696 // Common info for 92D DMSP 697 698 BOOLEAN *pbGetValueFromOtherMac; 699 PADAPTER *pBuddyAdapter; 700 BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave 701 // Common info for Status 702 BOOLEAN *pbScanInProcess; 703 BOOLEAN *pbPowerSaving; 704 // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. 705 u1Byte *pOnePathCCA; 706 //pMgntInfo->AntennaTest 707 u1Byte *pAntennaTest; 708 BOOLEAN *pbNet_closed; 709 //u1Byte *pAidMap; 710 u1Byte *pu1ForcedIgiLb; 711 BOOLEAN *pIsFcsModeEnable; 712 /*--------- For 8723B IQK-----------*/ 713 BOOLEAN *pIs1Antenna; 714 u1Byte *pRFDefaultPath; 715 // 0:S1, 1:S0 716 717 //--------- POINTER REFERENCE-----------// 718 pu2Byte pForcedDataRate; 719 pu1Byte HubUsbMode; 720 BOOLEAN *pbFwDwRsvdPageInProgress; 721 u4Byte *pCurrentTxTP; 722 u4Byte *pCurrentRxTP; 723 u1Byte *pSoundingSeq; 724 //------------CALL BY VALUE-------------// 725 BOOLEAN bLinkInProcess; 726 BOOLEAN bWIFI_Direct; 727 BOOLEAN bWIFI_Display; 728 BOOLEAN bLinked; 729 BOOLEAN bsta_state; 730 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 731 #ifdef UNIVERSAL_REPEATER 732 BOOLEAN VXD_bLinked; 733 #endif 734 #endif // for repeater mode add by YuChen 2014.06.23 735 u1Byte RSSI_Min; 736 u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ 737 BOOLEAN bIsMPChip; 738 BOOLEAN bOneEntryOnly; 739 BOOLEAN mp_mode; 740 u4Byte OneEntry_MACID; 741 u1Byte pre_number_linked_client; 742 u1Byte number_linked_client; 743 u1Byte pre_number_active_client; 744 u1Byte number_active_client; 745 // Common info for BTDM 746 BOOLEAN bBtEnabled; // BT is enabled 747 BOOLEAN bBtConnectProcess; // BT HS is under connection progress. 748 u1Byte btHsRssi; // BT HS mode wifi rssi value. 749 BOOLEAN bBtHsOperation; // BT HS mode is under progress 750 u1Byte btHsDigVal; // use BT rssi to decide the DIG value 751 BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo 752 BOOLEAN bBtBusy; // BT is busy. 753 BOOLEAN bBtLimitedDig; // BT is busy. 754 BOOLEAN bDisablePhyApi; 755 //------------CALL BY VALUE-------------// 756 u1Byte RSSI_A; 757 u1Byte RSSI_B; 758 u1Byte RSSI_C; 759 u1Byte RSSI_D; 760 u8Byte RSSI_TRSW; 761 u8Byte RSSI_TRSW_H; 762 u8Byte RSSI_TRSW_L; 763 u8Byte RSSI_TRSW_iso; 764 u1Byte TXAntStatus; 765 u1Byte RXAntStatus; 766 u1Byte cck_lna_idx; 767 u1Byte cck_vga_idx; 768 u1Byte curr_station_id; 769 u1Byte ofdm_agc_idx[4]; 770 771 u1Byte RxRate; 772 BOOLEAN bNoisyState; 773 u1Byte TxRate; 774 u1Byte LinkedInterval; 775 u1Byte preChannel; 776 u4Byte TxagcOffsetValueA; 777 BOOLEAN IsTxagcOffsetPositiveA; 778 u4Byte TxagcOffsetValueB; 779 BOOLEAN IsTxagcOffsetPositiveB; 780 u4Byte tx_tp; 781 u4Byte rx_tp; 782 u4Byte total_tp; 783 u8Byte curTxOkCnt; 784 u8Byte curRxOkCnt; 785 u8Byte lastTxOkCnt; 786 u8Byte lastRxOkCnt; 787 u4Byte BbSwingOffsetA; 788 BOOLEAN IsBbSwingOffsetPositiveA; 789 u4Byte BbSwingOffsetB; 790 BOOLEAN IsBbSwingOffsetPositiveB; 791 u1Byte IGI_LowerBound; 792 u1Byte IGI_UpperBound; 793 u1Byte antdiv_rssi; 794 u1Byte fat_comb_a; 795 u1Byte fat_comb_b; 796 u1Byte antdiv_intvl; 797 u1Byte AntType; 798 u1Byte pre_AntType; 799 u1Byte antdiv_period; 800 u1Byte evm_antdiv_period; 801 u1Byte antdiv_select; 802 u1Byte path_select; 803 u1Byte antdiv_evm_en; 804 u1Byte bdc_holdstate; 805 u1Byte NdpaPeriod; 806 BOOLEAN H2C_RARpt_connect; 807 BOOLEAN cck_agc_report_type; 808 809 u1Byte dm_dig_max_TH; 810 u1Byte dm_dig_min_TH; 811 u1Byte print_agc; 812 u1Byte TrafficLoad; 813 u1Byte pre_TrafficLoad; 814 815 816 //For Adaptivtiy 817 u2Byte NHM_cnt_0; 818 u2Byte NHM_cnt_1; 819 s1Byte TH_L2H_default; 820 s1Byte TH_EDCCA_HL_diff_default; 821 s1Byte TH_L2H_ini; 822 s1Byte TH_EDCCA_HL_diff; 823 s1Byte TH_L2H_ini_mode2; 824 s1Byte TH_EDCCA_HL_diff_mode2; 825 BOOLEAN Carrier_Sense_enable; 826 u1Byte Adaptivity_IGI_upper; 827 BOOLEAN adaptivity_flag; 828 u1Byte DCbackoff; 829 BOOLEAN Adaptivity_enable; 830 u1Byte APTotalNum; 831 BOOLEAN EDCCA_enable; 832 ADAPTIVITY_STATISTICS Adaptivity; 833 //For Adaptivtiy 834 u1Byte LastUSBHub; 835 u1Byte TxBfDataRate; 836 837 u1Byte nbi_set_result; 838 839 u1Byte c2h_cmd_start; 840 u1Byte fw_debug_trace[60]; 841 u1Byte pre_c2h_seq; 842 BOOLEAN fw_buff_is_enpty; 843 u4Byte data_frame_num; 844 845 /*for noise detection*/ 846 BOOLEAN NoisyDecision; /*b_noisy*/ 847 BOOLEAN pre_b_noisy; 848 u4Byte NoisyDecision_Smooth; 849 850 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 851 ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; 852 #endif 853 // 854 //2 Define STA info. 855 // _ODM_STA_INFO 856 // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? 857 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 858 u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ 859 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 860 s4Byte AccumulatePWDB[ODM_ASSOCIATE_ENTRY_NUM]; 861 #endif 862 863 #if (RATE_ADAPTIVE_SUPPORT == 1) 864 u2Byte CurrminRptTime; 865 ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 866 #endif 867 // 868 // 2012/02/14 MH Add to share 88E ra with other SW team. 869 // We need to colelct all support abilit to a proper area. 870 // 871 BOOLEAN RaSupport88E; 872 873 // Define ........... 874 875 // Latest packet phy info (ODM write) 876 ODM_PHY_DBG_INFO_T PhyDbgInfo; 877 //PHY_INFO_88E PhyInfo; 878 879 // Latest packet phy info (ODM write) 880 ODM_MAC_INFO *pMacInfo; 881 //MAC_INFO_88E MacInfo; 882 883 // Different Team independt structure?? 884 885 // 886 //TX_RTP_CMN TX_retrpo; 887 //TX_RTP_88E TX_retrpo; 888 //TX_RTP_8195 TX_retrpo; 889 890 // 891 //ODM Structure 892 // 893 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 894 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 895 BDC_T DM_BdcTable; 896 #endif 897 898 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 899 SAT_T dm_sat_table; 900 #endif 901 902 #endif 903 FAT_T DM_FatTable; 904 DIG_T DM_DigTable; 905 906 PS_T DM_PSTable; 907 Pri_CCA_T DM_PriCCA; 908 RA_T DM_RA_Table; 909 FALSE_ALARM_STATISTICS FalseAlmCnt; 910 FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 911 SWAT_T DM_SWAT_Table; 912 CFO_TRACKING DM_CfoTrack; 913 ACS DM_ACS; 914 CCX_INFO DM_CCX_INFO; 915 #if (PHYDM_LA_MODE_SUPPORT == 1) 916 RT_ADCSMP adcsmp; 917 #endif 918 919 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) 920 IQK_INFO IQK_info; 921 #endif 922 923 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 924 //Path Div Struct 925 PATHDIV_PARA pathIQK; 926 #endif 927 #if(defined(CONFIG_PATH_DIVERSITY)) 928 PATHDIV_T DM_PathDiv; 929 #endif 930 931 EDCA_T DM_EDCA_Table; 932 u4Byte WMMEDCA_BE; 933 934 // Copy from SD4 structure 935 // 936 // ================================================== 937 // 938 939 //common 940 //u1Byte DM_Type; 941 //u1Byte PSD_Report_RXHP[80]; // Add By Gary 942 //u1Byte PSD_func_flag; // Add By Gary 943 //for DIG 944 //u1Byte bDMInitialGainEnable; 945 //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. 946 947 BOOLEAN *pbDriverStopped; 948 BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; 949 BOOLEAN *pinit_adpt_in_progress; 950 951 //PSD 952 BOOLEAN bUserAssignLevel; 953 u1Byte RSSI_BT; /*come from BT*/ 954 BOOLEAN bPSDinProcess; 955 BOOLEAN bPSDactive; 956 BOOLEAN bDMInitialGainEnable; 957 958 //MPT DIG 959 RT_TIMER MPT_DIGTimer; 960 961 //for rate adaptive, in fact, 88c/92c fw will handle this 962 u1Byte bUseRAMask; 963 964 ODM_RATE_ADAPTIVE RateAdaptive; 965 #if (defined(CONFIG_ANT_DETECTION)) 966 ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool*/ 967 #endif 968 ODM_RF_CAL_T RFCalibrateInfo; 969 u4Byte nIQK_Cnt; 970 u4Byte nIQK_OK_Cnt; 971 u4Byte nIQK_Fail_Cnt; 972 973 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 974 // 975 // Power Training 976 // 977 u1Byte ForcePowerTrainingState; 978 BOOLEAN bChangeState; 979 u4Byte PT_score; 980 u8Byte OFDM_RX_Cnt; 981 u8Byte CCK_RX_Cnt; 982 #endif 983 BOOLEAN bDisablePowerTraining; 984 u1Byte DynamicTxHighPowerLvl; 985 u1Byte LastDTPLvl; 986 u4Byte tx_agc_ofdm_18_6; 987 u1Byte rx_pkt_type; 988 989 // 990 // ODM system resource. 991 // 992 993 // ODM relative time. 994 RT_TIMER PathDivSwitchTimer; 995 //2011.09.27 add for Path Diversity 996 RT_TIMER CCKPathDiversityTimer; 997 RT_TIMER FastAntTrainingTimer; 998 #ifdef ODM_EVM_ENHANCE_ANTDIV 999 RT_TIMER EVM_FastAntTrainingTimer; 1000 #endif 1001 RT_TIMER sbdcnt_timer; 1002 1003 // ODM relative workitem. 1004 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1005 #if USE_WORKITEM 1006 RT_WORK_ITEM PathDivSwitchWorkitem; 1007 RT_WORK_ITEM CCKPathDiversityWorkitem; 1008 RT_WORK_ITEM FastAntTrainingWorkitem; 1009 RT_WORK_ITEM MPT_DIGWorkitem; 1010 RT_WORK_ITEM RaRptWorkitem; 1011 RT_WORK_ITEM sbdcnt_workitem; 1012 #endif 1013 #endif 1014 1015 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1016 #if (BEAMFORMING_SUPPORT == 1) 1017 RT_BEAMFORMING_INFO BeamformingInfo; 1018 #endif 1019 #endif 1020 1021 #ifdef CONFIG_PHYDM_DFS_MASTER 1022 u1Byte DFS_RegionDomain; 1023 pu1Byte dfs_master_enabled; 1024 1025 /*====== phydm_radar_detect_with_dbg_parm start ======*/ 1026 u1Byte radar_detect_dbg_parm_en; 1027 u4Byte radar_detect_reg_918; 1028 u4Byte radar_detect_reg_91c; 1029 u4Byte radar_detect_reg_920; 1030 u4Byte radar_detect_reg_924; 1031 /*====== phydm_radar_detect_with_dbg_parm end ======*/ 1032 #endif 1033 1034 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) 1035 1036 #if (RT_PLATFORM != PLATFORM_LINUX) 1037 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure 1038 #else 1039 }; 1040 #endif 1041 1042 #else// for AP,ADSL,CE Team 1043 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure 1044 #endif 1045 1046 1047 typedef enum _PHYDM_STRUCTURE_TYPE{ 1048 PHYDM_FALSEALMCNT, 1049 PHYDM_CFOTRACK, 1050 PHYDM_ADAPTIVITY, 1051 PHYDM_ROMINFO, 1052 1053 }PHYDM_STRUCTURE_TYPE; 1054 1055 1056 1057 typedef enum _ODM_RF_CONTENT{ 1058 odm_radioa_txt = 0x1000, 1059 odm_radiob_txt = 0x1001, 1060 odm_radioc_txt = 0x1002, 1061 odm_radiod_txt = 0x1003 1062 } ODM_RF_CONTENT; 1063 1064 typedef enum _ODM_BB_Config_Type{ 1065 CONFIG_BB_PHY_REG, 1066 CONFIG_BB_AGC_TAB, 1067 CONFIG_BB_AGC_TAB_2G, 1068 CONFIG_BB_AGC_TAB_5G, 1069 CONFIG_BB_PHY_REG_PG, 1070 CONFIG_BB_PHY_REG_MP, 1071 CONFIG_BB_AGC_TAB_DIFF, 1072 } ODM_BB_Config_Type, *PODM_BB_Config_Type; 1073 1074 typedef enum _ODM_RF_Config_Type{ 1075 CONFIG_RF_RADIO, 1076 CONFIG_RF_TXPWR_LMT, 1077 } ODM_RF_Config_Type, *PODM_RF_Config_Type; 1078 1079 typedef enum _ODM_FW_Config_Type{ 1080 CONFIG_FW_NIC, 1081 CONFIG_FW_NIC_2, 1082 CONFIG_FW_AP, 1083 CONFIG_FW_AP_2, 1084 CONFIG_FW_MP, 1085 CONFIG_FW_WoWLAN, 1086 CONFIG_FW_WoWLAN_2, 1087 CONFIG_FW_AP_WoWLAN, 1088 CONFIG_FW_BT, 1089 } ODM_FW_Config_Type; 1090 1091 // Status code 1092 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1093 typedef enum _RT_STATUS{ 1094 RT_STATUS_SUCCESS, 1095 RT_STATUS_FAILURE, 1096 RT_STATUS_PENDING, 1097 RT_STATUS_RESOURCE, 1098 RT_STATUS_INVALID_CONTEXT, 1099 RT_STATUS_INVALID_PARAMETER, 1100 RT_STATUS_NOT_SUPPORT, 1101 RT_STATUS_OS_API_FAILED, 1102 }RT_STATUS,*PRT_STATUS; 1103 #endif // end of RT_STATUS definition 1104 1105 #ifdef REMOVE_PACK 1106 #pragma pack() 1107 #endif 1108 1109 //3=========================================================== 1110 //3 AGC RX High Power Mode 1111 //3=========================================================== 1112 #define LNA_Low_Gain_1 0x64 1113 #define LNA_Low_Gain_2 0x5A 1114 #define LNA_Low_Gain_3 0x58 1115 1116 #define FA_RXHP_TH1 5000 1117 #define FA_RXHP_TH2 1500 1118 #define FA_RXHP_TH3 800 1119 #define FA_RXHP_TH4 600 1120 #define FA_RXHP_TH5 500 1121 1122 typedef enum tag_1R_CCA_Type_Definition 1123 { 1124 CCA_1R =0, 1125 CCA_2R = 1, 1126 CCA_MAX = 2, 1127 }DM_1R_CCA_E; 1128 1129 typedef enum tag_RF_Type_Definition 1130 { 1131 RF_Save =0, 1132 RF_Normal = 1, 1133 RF_MAX = 2, 1134 }DM_RF_E; 1135 1136 // 1137 // check Sta pointer valid or not 1138 // 1139 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 1140 #define IS_STA_VALID(pSta) (pSta && pSta->expire_to) 1141 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1142 #define IS_STA_VALID(pSta) (pSta && pSta->bUsed) 1143 #else 1144 #define IS_STA_VALID(pSta) (pSta) 1145 #endif 1146 1147 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP)) 1148 1149 BOOLEAN 1150 ODM_CheckPowerStatus( 1151 IN PADAPTER Adapter 1152 ); 1153 1154 #endif 1155 1156 1157 1158 u4Byte odm_ConvertTo_dB(u4Byte Value); 1159 1160 u4Byte odm_ConvertTo_linear(u4Byte Value); 1161 1162 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) 1163 1164 u4Byte 1165 GetPSDData( 1166 PDM_ODM_T pDM_Odm, 1167 unsigned int point, 1168 u1Byte initial_gain_psd); 1169 1170 #endif 1171 1172 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1173 VOID 1174 ODM_DMWatchdog_LPS( 1175 IN PDM_ODM_T pDM_Odm 1176 ); 1177 #endif 1178 1179 1180 s4Byte 1181 ODM_PWdB_Conversion( 1182 IN s4Byte X, 1183 IN u4Byte TotalBit, 1184 IN u4Byte DecimalBit 1185 ); 1186 1187 s4Byte 1188 ODM_SignConversion( 1189 IN s4Byte value, 1190 IN u4Byte TotalBit 1191 ); 1192 1193 void 1194 phydm_seq_sorting( 1195 IN PVOID pDM_VOID, 1196 IN OUT u4Byte *p_value, 1197 IN OUT u4Byte *rank_idx, 1198 IN OUT u4Byte *p_idx_out, 1199 IN u1Byte seq_length 1200 ); 1201 1202 VOID 1203 ODM_DMInit( 1204 IN PDM_ODM_T pDM_Odm 1205 ); 1206 1207 VOID 1208 ODM_DMReset( 1209 IN PDM_ODM_T pDM_Odm 1210 ); 1211 1212 VOID 1213 phydm_support_ability_debug( 1214 IN PVOID pDM_VOID, 1215 IN u4Byte *const dm_value, 1216 IN u4Byte *_used, 1217 OUT char *output, 1218 IN u4Byte *_out_len 1219 ); 1220 1221 VOID 1222 phydm_config_trx_path( 1223 IN PVOID pDM_VOID, 1224 IN u4Byte *const dm_value, 1225 IN u4Byte *_used, 1226 OUT char *output, 1227 IN u4Byte *_out_len 1228 ); 1229 1230 VOID 1231 ODM_DMWatchdog( 1232 IN PDM_ODM_T pDM_Odm // For common use in the future 1233 ); 1234 1235 VOID 1236 ODM_CmnInfoInit( 1237 IN PDM_ODM_T pDM_Odm, 1238 IN ODM_CMNINFO_E CmnInfo, 1239 IN u4Byte Value 1240 ); 1241 1242 VOID 1243 ODM_CmnInfoHook( 1244 IN PDM_ODM_T pDM_Odm, 1245 IN ODM_CMNINFO_E CmnInfo, 1246 IN PVOID pValue 1247 ); 1248 1249 VOID 1250 ODM_CmnInfoPtrArrayHook( 1251 IN PDM_ODM_T pDM_Odm, 1252 IN ODM_CMNINFO_E CmnInfo, 1253 IN u2Byte Index, 1254 IN PVOID pValue 1255 ); 1256 1257 VOID 1258 ODM_CmnInfoUpdate( 1259 IN PDM_ODM_T pDM_Odm, 1260 IN u4Byte CmnInfo, 1261 IN u8Byte Value 1262 ); 1263 1264 #if(DM_ODM_SUPPORT_TYPE==ODM_AP) 1265 VOID 1266 ODM_InitAllThreads( 1267 IN PDM_ODM_T pDM_Odm 1268 ); 1269 1270 VOID 1271 ODM_StopAllThreads( 1272 IN PDM_ODM_T pDM_Odm 1273 ); 1274 #endif 1275 1276 VOID 1277 ODM_InitAllTimers( 1278 IN PDM_ODM_T pDM_Odm 1279 ); 1280 1281 VOID 1282 ODM_CancelAllTimers( 1283 IN PDM_ODM_T pDM_Odm 1284 ); 1285 1286 VOID 1287 ODM_ReleaseAllTimers( 1288 IN PDM_ODM_T pDM_Odm 1289 ); 1290 1291 1292 1293 1294 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1295 VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); 1296 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); 1297 1298 1299 1300 u8Byte 1301 PlatformDivision64( 1302 IN u8Byte x, 1303 IN u8Byte y 1304 ); 1305 1306 //==================================================== 1307 //3 PathDiV End 1308 //==================================================== 1309 1310 1311 #define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh 1312 1313 typedef enum tag_DIG_Connect_Definition 1314 { 1315 DIG_STA_DISCONNECT = 0, 1316 DIG_STA_CONNECT = 1, 1317 DIG_STA_BEFORE_CONNECT = 2, 1318 DIG_MultiSTA_DISCONNECT = 3, 1319 DIG_MultiSTA_CONNECT = 4, 1320 DIG_CONNECT_MAX 1321 }DM_DIG_CONNECT_E; 1322 1323 1324 // 1325 // 2012/01/12 MH Check afapter status. Temp fix BSOD. 1326 // 1327 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\ 1328 if (pDM_Odm->Adapter == NULL)\ 1329 {\ 1330 return;\ 1331 }\ 1332 1333 #endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1334 1335 VOID 1336 ODM_AsocEntry_Init( 1337 IN PDM_ODM_T pDM_Odm 1338 ); 1339 1340 1341 PVOID 1342 PhyDM_Get_Structure( 1343 IN PDM_ODM_T pDM_Odm, 1344 IN u1Byte Structure_Type 1345 ); 1346 1347 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) 1348 /*===========================================================*/ 1349 /* The following is for compile only*/ 1350 /*===========================================================*/ 1351 1352 #define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE 1353 #define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE 1354 #define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE 1355 #define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE 1356 #define RF_T_METER_92D 0x42 1357 1358 1359 #define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) 1360 1361 #define rConfig_ram64x16 0xb2c 1362 1363 #define TARGET_CHNL_NUM_2G_5G 59 1364 1365 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1366 u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); 1367 #endif 1368 1369 //=========================================================== 1370 #endif 1371 1372 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1373 void odm_dtc(PDM_ODM_T pDM_Odm); 1374 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ 1375 1376 1377 VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); 1378 1379 1380 #endif 1381 1382 VOID 1383 phydm_set_ext_switch( 1384 IN PVOID pDM_VOID, 1385 IN u4Byte *const dm_value, 1386 IN u4Byte *_used, 1387 OUT char *output, 1388 IN u4Byte *_out_len 1389 ); 1390 1391 VOID 1392 phydm_api_debug( 1393 IN PVOID pDM_VOID, 1394 IN u4Byte function_map, 1395 IN u4Byte *const dm_value, 1396 IN u4Byte *_used, 1397 OUT char *output, 1398 IN u4Byte *_out_len 1399 ); 1400 1401 u1Byte 1402 phydm_nbi_setting( 1403 IN PVOID pDM_VOID, 1404 IN u4Byte enable, 1405 IN u4Byte channel, 1406 IN u4Byte bw, 1407 IN u4Byte f_interference, 1408 IN u4Byte Second_ch 1409 ); 1410 1411