1 /* 2 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef XPU_TARGET_INFO_H 8 #define XPU_TARGET_INFO_H 9 10 #include <xpu3.h> 11 12 #include <kodiak_def.h> 13 14 #define ACC_XPU_ERR_INT_REG_NUM 2 15 #define ACC_XPU_ERR_NUM_PER_REG 32 16 17 #define XPU_ADDR_TYPE(hwiosym) HWIO_##hwiosym##_ADDR 18 19 #define HWIO_OCIMEM_MPU_XPU3_GCR0_ADDR 0x061c000 20 #define HWIO_BOOT_ROM_XPU3_GCR0_ADDR 0x03fe000 21 #define HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ADDR 0x01e00000 22 #define HWIO_SNOC_AGGRE1_MS_MPU_XPU3_GCR0_ADDR 0x016b0000 23 #define HWIO_SNOC_AGGRE2_MS_MPU_XPU3_GCR0_ADDR 0x016a8000 24 #define HWIO_LLCC0_LLCC_XPU3_GCR0_ADDR 0x0922e000 25 #define HWIO_LLCC1_LLCC_XPU3_GCR0_ADDR 0x092ae000 26 #define HWIO_MODEM_MS_MPU_XPU3_GCR0_ADDR 0x091fe000 27 #define HWIO_LLCC_BROADCAST_LLCC_XPU3_GCR0_ADDR 0x0962e000 28 #define HWIO_SNOC_NAV_MS_MPU_XPU3_GCR0_ADDR 0x016a0000 29 #define HWIO_AOSS_MPU_XPU3_GCR0_ADDR 0x01522000 30 #define HWIO_SEC_CTRL_APU_XPU3_GCR0_ADDR 0x0078e000 31 #define HWIO_MDSP_MS_MPU_XPU3_GCR0_ADDR 0x091fc000 32 #define HWIO_AOSS_CNOC_MPU_XPU3_GCR0_ADDR 0x0eff0000 33 #define HWIO_QHM_SHRM_MPU_XPU3_GCR0_ADDR 0x090c2000 34 #define HWIO_PKA_WRAPPER_XPU3_GCR0_ADDR 0x000f0000 35 #define HWIO_IPC_XPU3_GCR0_ADDR 0x004fe000 36 #define HWIO_QHS_NON_BROADCAST_MPU_XPU3_GCR0_ADDR 0x090c4000 37 #define HWIO_CNOC_GEMNOC_MPU_XPU3_GCR0_ADDR 0x0152c000 38 #define HWIO_CNOC2_SS_MPU_XPU3_GCR0_ADDR 0x01530000 39 #define HWIO_WPSS_MPU_XPU3_GCR0_ADDR 0x08b14000 40 41 #define TCSR_TCSR_REGS_REG_BASE (QTI_CORE_TOP_CSR_BASE + 0x000c0000) 42 43 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR \ 44 (TCSR_TCSR_REGS_REG_BASE + 0x00002000) 45 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_RMSK 0xffffffff 46 47 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR \ 48 (TCSR_TCSR_REGS_REG_BASE + 0x00002004) 49 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RMSK 0xffffffff 50 51 #define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR \ 52 (TCSR_TCSR_REGS_REG_BASE + 0x00004000) 53 #define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_RMSK 0xffffffff 54 55 #define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR \ 56 (TCSR_TCSR_REGS_REG_BASE + 0x00004004) 57 #define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RMSK 0xffffffff 58 59 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR \ 60 (TCSR_TCSR_REGS_REG_BASE + 0x00002040) 61 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK 0xffffffff 62 63 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR \ 64 (TCSR_TCSR_REGS_REG_BASE + 0x00002044) 65 #define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RMSK 0xffffffff 66 67 #define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR \ 68 (TCSR_TCSR_REGS_REG_BASE + 0x00004040) 69 #define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_RMSK 0xffffffff 70 71 #define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR \ 72 (TCSR_TCSR_REGS_REG_BASE + 0x00004044) 73 #define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RMSK 0xffffffff 74 75 #define NUM_MODEM_MPU_PARTITIONS 7 76 #define NUM_MSS_NAV_MPU_PARTITIONS 8 77 78 extern struct xpu_err_pos_to_hal_map 79 xpu_err_pos_to_hal_map[ACC_XPU_ERR_INT_REG_NUM][ACC_XPU_ERR_NUM_PER_REG]; 80 81 extern const struct xpu_intr_reg_dtls 82 xpu_non_sec_intr_status_reg[ACC_XPU_ERR_INT_REG_NUM]; 83 84 extern const struct xpu_intr_reg_dtls 85 xpu_sec_intr_status_reg[ACC_XPU_ERR_INT_REG_NUM]; 86 87 extern const struct xpu_intr_reg_dtls 88 xpu_non_sec_intr_en_reg[ACC_XPU_ERR_INT_REG_NUM]; 89 90 extern const struct xpu_intr_reg_dtls 91 xpu_sec_intr_en_reg[ACC_XPU_ERR_INT_REG_NUM]; 92 93 extern struct xpu_instance msm_xpu_cfg[]; 94 extern const uint32_t msm_xpu_cfg_count; 95 96 extern struct mpu_ranges msm_mpu_ranges[]; 97 extern const uint32_t msm_mpu_ranges_count; 98 99 extern struct xpu_base_addr_info g_xpu_base_addr_array[]; 100 extern uint32_t g_xpu_base_addr_array_count; 101 102 void xpu_configure_tz(void); 103 104 #endif /* XPU_TARGET_INFO_H */ 105