1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NRD_PAS_DEF3_H 8 #define NRD_PAS_DEF3_H 9 10 #ifndef __ASSEMBLER__ 11 #include <stddef.h> 12 #include <lib/gpt_rme/gpt_rme.h> 13 #endif 14 15 #include <nrd_css_def3.h> 16 17 /***************************************************************************** 18 * PAS regions used to initialize the Granule Protection Table (GPT) 19 ****************************************************************************/ 20 21 /* 22 * ===================================================================== 23 * Base Addr |Size |L? GPT |PAS |Content | 24 * ===================================================================== 25 * 0x00000000 |256MB |L0 GPT |ANY |SHARED RAM | 26 * 0x0FFFFFFF | | | |AP EXPANSION | 27 * --------------------------------------------------------------------- 28 * 0x20000000 |64MB |L1 GPT |ROOT |SYSTEM NCI | 29 * 0x23FFFFFF | | | | | 30 * --------------------------------------------------------------------- 31 * 0x28000000 |16MB |L1 GPT |SECURE |DEBUG NIC | 32 * 0x28FFFFFF | | | | | 33 * --------------------------------------------------------------------- 34 * 0x2A400000 |64KB |L1 GPT |NS |NS UART | 35 * 0x2A40FFFF | | | | | 36 * --------------------------------------------------------------------- 37 * 0x2A410000 |64KB |L1 GPT |SECURE |SECURE UART | 38 * 0x2A41FFFF | | | | | 39 * --------------------------------------------------------------------- 40 * 0x2A420000 |64KB |L1 GPT |REALM |REALM UART | 41 * 0x2A42FFFF | | | | | 42 * --------------------------------------------------------------------- 43 * 0x2A430000 |64KB |L1 GPT |SECURE |GENERIC REFCLK | 44 * 0x2A43FFFF | | | | | 45 * --------------------------------------------------------------------- 46 * 0x2A440000 |128KB |L1 GPT |NS |AP NS WDOG | 47 * 0x2A45FFFF | | | | | 48 * --------------------------------------------------------------------- 49 * 0x2A460000 |128KB |L1 GPT |ROOT |AP ROOT WDOG | 50 * 0x2A47FFFF | | | | | 51 * --------------------------------------------------------------------- 52 * 0x2A480000 |128KB |L1 GPT |SECURE |AP SECURE WDOG | 53 * 0x2A49FFFF | | | | | 54 * --------------------------------------------------------------------- 55 * 0x2A4A0000 |64KB |L1 GPT |NS |SID | 56 * 0x2A4AFFFF | | | | | 57 * --------------------------------------------------------------------- 58 * 0x2A4B0000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR | 59 * 0x2A4BFFFF | | | |RECORD BLOCK - AP | 60 * --------------------------------------------------------------------- 61 * 0x2A4C0000 |64KB |L1 GPT |NS |NS SRAM ERROR | 62 * 0x2A4CFFFF | | | |RECORD BLOCK - AP | 63 * --------------------------------------------------------------------- 64 * 0x2A4D0000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR | 65 * 0x2A4DFFFF | | | |RECORD BLOCK - AP | 66 * --------------------------------------------------------------------- 67 * 0x2A4E0000 |64KB |L1 GPT |REALM |REALM SRAM ERROR | 68 * 0x2A4EFFFF | | | |RECORD BLOCK - AP | 69 * --------------------------------------------------------------------- 70 * 0x2A4F0000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR | 71 * 0x2A4FFFFF | | | |RECORD BLOCK - SCP | 72 * --------------------------------------------------------------------- 73 * 0x2A500000 |64KB |L1 GPT |NS |NS SRAM ERROR | 74 * 0x2A50FFFF | | | |RECORD BLOCK - SCP | 75 * --------------------------------------------------------------------- 76 * 0x2A510000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR | 77 * 0x2A51FFFF | | | |RECORD BLOCK - SCP | 78 * --------------------------------------------------------------------- 79 * 0x2A520000 |64KB |L1 GPT |REALM |REALM SRAM ERROR | 80 * 0x2A52FFFF | | | |RECORD BLOCK - SCP | 81 * --------------------------------------------------------------------- 82 * 0x2A530000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR | 83 * 0x2A53FFFF | | | |RECORD BLOCK - MCP | 84 * --------------------------------------------------------------------- 85 * 0x2A540000 |64KB |L1 GPT |NS |NS SRAM ERROR | 86 * 0x2A54FFFF | | | |RECORD BLOCK - MCP | 87 * --------------------------------------------------------------------- 88 * 0x2A550000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR | 89 * 0x2A55FFFF | | | |RECORD BLOCK - MCP | 90 * --------------------------------------------------------------------- 91 * 0x2A560000 |64KB |L1 GPT |REALM |REALM SRAM ERROR | 92 * 0x2A56FFFF | | | |RECORD BLOCK - MCP | 93 * --------------------------------------------------------------------- 94 * 0x2A570000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR | 95 * 0x2A57FFFF | | | |RECORD BLOCK - RSE | 96 * --------------------------------------------------------------------- 97 * 0x2A580000 |64KB |L1 GPT |NS |NS SRAM ERROR | 98 * 0x2A58FFFF | | | |RECORD BLOCK - RSE | 99 * --------------------------------------------------------------------- 100 * 0x2A590000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR | 101 * 0x2A59FFFF | | | |RECORD BLOCK - RSE | 102 * --------------------------------------------------------------------- 103 * 0x2A5A0000 |64KB |L1 GPT |REALM |REALM SRAM ERROR | 104 * 0x2A5AFFFF | | | |RECORD BLOCK - RSE | 105 * --------------------------------------------------------------------- 106 * 0x2A5B0000 |64KB |L1 GPT |SECURE |RSE SECURE SRAM ERROR | 107 * 0x2A5BFFFF | | | |RECORD BLOCK - RSM | 108 * --------------------------------------------------------------------- 109 * 0x2A5C0000 |64KB |L1 GPT |NS |RSE NS SRAM ERROR | 110 * 0x2A5CFFFF | | | |RECORD BLOCK - RSM | 111 * --------------------------------------------------------------------- 112 * 0x2A5D0000 |64KB |L1 GPT |SECURE |SCP SECURE SRAM ERROR | 113 * 0x2A5DFFFF | | | |RECORD BLOCK - RSM | 114 * --------------------------------------------------------------------- 115 * 0x2A5E0000 |64KB |L1 GPT |NS |SCP NS SRAM ERROR | 116 * 0x2A5EFFFF | | | |RECORD BLOCK - RSM | 117 * --------------------------------------------------------------------- 118 * 0x2A5F0000 |64KB |L1 GPT |SECURE |MCP SECURE SRAM ERROR | 119 * 0x2A5FFFFF | | | |RECORD BLOCK - RSM | 120 * --------------------------------------------------------------------- 121 * 0x2A600000 |64KB |L1 GPT |NS |MCP NS SRAM ERROR | 122 * 0x2A60FFFF | | | |RECORD BLOCK - RSM | 123 * --------------------------------------------------------------------- 124 * 0x2A800000 |128KB |L1 GPT |NS |CNTCTL REFCLK | 125 * 0x2A81FFFF | | | |READ FRAME | 126 * --------------------------------------------------------------------- 127 * 0x2A820000 |64KB |L1 GPT |SECURE |SECURE TIMER CTL | 128 * 0x2A82FFFF | | | |BASE FRAME | 129 * --------------------------------------------------------------------- 130 * 0x2A830000 |64KB |L1 GPT |NS |NS TIMER CTL | 131 * 0x2A83FFFF | | | |BASE FRAME | 132 * --------------------------------------------------------------------- 133 * 0x2A900000 |128KB |L1 GPT |NS |AP-SCP NS | 134 * 0x2A91FFFF | | | |MHU | 135 * --------------------------------------------------------------------- 136 * 0x2A920000 |128KB |L1 GPT |SECURE |AP-SCP SECURE | 137 * 0x2A93FFFF | | | |MHU | 138 * --------------------------------------------------------------------- 139 * 0x2A940000 |128KB |L1 GPT |ROOT |AP-SCP ROOT | 140 * 0x2A95FFFF | | | |MHU | 141 * --------------------------------------------------------------------- 142 * 0x2AA00000 |128KB |L1 GPT |NS |AP-MCP NS | 143 * 0x2AA1FFFF | | | |MHU | 144 * --------------------------------------------------------------------- 145 * 0x2AA20000 |128KB |L1 GPT |SECURE |AP-MCP SECURE | 146 * 0x2AA3FFFF | | | |MHU | 147 * --------------------------------------------------------------------- 148 * 0x2AA40000 |128KB |L1 GPT |ROOT |AP-MCP ROOT | 149 * 0x2AA5FFFF | | | |MHU | 150 * --------------------------------------------------------------------- 151 * 0x2AB00000 |128KB |L1 GPT |NS |AP-MCP NS | 152 * 0x2AB1FFFF | | | |MHU | 153 * --------------------------------------------------------------------- 154 * 0x2AB20000 |128KB |L1 GPT |SECURE |AP-RSE SECURE | 155 * 0x2AB3FFFF | | | |MHU | 156 * --------------------------------------------------------------------- 157 * 0x2AB40000 |128KB |L1 GPT |ROOT |AP-RSE ROOT | 158 * 0x2AB5FFFF | | | |MHU | 159 * --------------------------------------------------------------------- 160 * 0x2AB60000 |128KB |L1 GPT |REALM |AP-RSE REALM | 161 * 0x2AB7FFFF | | | |MHU | 162 * --------------------------------------------------------------------- 163 * 0x2AC00000 |1152KB |L1 GPT |ROOT |SCP MCP RSE | 164 * 0x2ACEFFFF | | | |CROSS CHIP MHU | 165 * --------------------------------------------------------------------- 166 * 0x2B100000 |192KB |L1 GPT |SECURE |SYNCNT | 167 * 0x2B12FFFF | | | |MSTUPDTVAL_ADDR | 168 * --------------------------------------------------------------------- 169 * 0x2CF00000 |~33MB |L1 GPT |NS |STM SYSTEM ITS | 170 * 0x2EFFFFFF | | | | | 171 * --------------------------------------------------------------------- 172 * 0x2F000000 |4MB |L1 GPT |ANY |SHARED SRAM | 173 * 0x2F3FFFFF | | | | | 174 * --------------------------------------------------------------------- 175 * 0x30000000 |128MB |L1 GPT |ANY |GIC CLAYTON | 176 * 0x37FFFFFF | | | | | 177 * --------------------------------------------------------------------- 178 * 0x80000000 |2GB - |L1 GPT |NS |NS DRAM | 179 * 0xF3FFFFFF |192MB | | | | 180 * --------------------------------------------------------------------| 181 * 0xF4000000 |9692KB |L1 GPT |SECURE |BL32 | 182 * 0xFB200000 | | | | | 183 * --------------------------------------------------------------------- 184 * 0x80000000 |26MB |L1 GPT |REALM |RMM | 185 * 0x37FFFFFF | | | |TF-A SHARED | 186 * --------------------------------------------------------------------- 187 * 0x80000000 |2MB |L1 GPT |ROOT |L1GPT | 188 * 0x37FFFFFF | | | | | 189 * --------------------------------------------------------------------- 190 * 0x100080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 3 | 191 * 0x1000FFFFFFFF | | | | | 192 * --------------------------------------------------------------------- 193 * 0x200080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 2 | 194 * 0x2000FFFFFFFF | | | | | 195 * --------------------------------------------------------------------- 196 * 0x300080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 1 | 197 * 0x3000FFFFFFFF | | | | | 198 * --------------------------------------------------------------------- 199 * 0x100000000 |1GB |L1 GPT |ANY |CMN | 200 * 0x13FFFFFFF | | | | | 201 * --------------------------------------------------------------------- 202 * 0x200000000 |1GB |L1 GPT |ANY |LCP PERIPHERALS | 203 * 0x23FFFFFFF | | | |DDR | 204 * --------------------------------------------------------------------- 205 * 0x240000000 |1GB |L1 GPT |ANY |DDR IO | 206 * 0x27FFFFFFF | | | | | 207 * --------------------------------------------------------------------- 208 * 0x280000000 |1.5GB |L1 GPT |ANY |SMMU & NCI IO | 209 * 0x2DFFFFFFF | | | | | 210 * --------------------------------------------------------------------- 211 * 0x300000000 |128MB |L1 GPT |ROOT |GPC SMMU | 212 * 0x308000000 | | | | | 213 * --------------------------------------------------------------------- 214 * 0x8080000000 |6GB |L1 GPT |ANY |DRAM 2 CHIP 0 | 215 * 0x81FFFFFFFF | | | | | 216 * --------------------------------------------------------------------- 217 * 0x108080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 1 | 218 * 0x1081FFFFFFFF | | | | | 219 * --------------------------------------------------------------------- 220 * 0x208080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 2 | 221 * 0x2081FFFFFFFF | | | | | 222 * --------------------------------------------------------------------- 223 * 0x308080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 3 | 224 * 0x3081FFFFFFFF | | | | | 225 * ===================================================================== 226 */ 227 228 /******************************************************************************* 229 * Multichip config 230 ******************************************************************************/ 231 232 #define NRD_MC_BASE(base, n) (NRD_REMOTE_CHIP_MEM_OFFSET(n) + base) 233 234 /******************************************************************************* 235 * PAS mappings 236 ******************************************************************************/ 237 238 #define NRD_PAS_SHARED_SRAM \ 239 GPT_MAP_REGION_GRANULE( \ 240 NRD_CSS_SHARED_SRAM_BASE, \ 241 NRD_CSS_SHARED_SRAM_SIZE, \ 242 GPT_GPI_ANY) 243 244 #define NRD_PAS_SYSTEM_NCI \ 245 GPT_MAP_REGION_GRANULE( \ 246 NRD_CSS_SYSTEM_NCI_BASE, \ 247 NRD_CSS_SYSTEM_NCI_SIZE, \ 248 GPT_GPI_ROOT) 249 250 #define NRD_PAS_DEBUG_NIC \ 251 GPT_MAP_REGION_GRANULE( \ 252 NRD_CSS_DEBUG_NIC_BASE, \ 253 NRD_CSS_DEBUG_NIC_SIZE, \ 254 GPT_GPI_SECURE) 255 256 #define NRD_PAS_NS_UART \ 257 GPT_MAP_REGION_GRANULE( \ 258 NRD_CSS_NS_UART_BASE, \ 259 NRD_CSS_NS_UART_SIZE, \ 260 GPT_GPI_NS) 261 262 #define NRD_PAS_REALM_UART \ 263 GPT_MAP_REGION_GRANULE( \ 264 NRD_CSS_REALM_UART_BASE, \ 265 NRD_CSS_REALM_UART_SIZE, \ 266 GPT_GPI_REALM) 267 268 #define NRD_PAS_AP_NS_WDOG \ 269 GPT_MAP_REGION_GRANULE( \ 270 NRD_CSS_AP_NS_WDOG_BASE, \ 271 NRD_CSS_AP_NS_WDOG_SIZE, \ 272 GPT_GPI_NS) 273 274 #define NRD_PAS_AP_ROOT_WDOG \ 275 GPT_MAP_REGION_GRANULE( \ 276 NRD_CSS_AP_ROOT_WDOG_BASE, \ 277 NRD_CSS_AP_ROOT_WDOG_SIZE, \ 278 GPT_GPI_ROOT) 279 280 #define NRD_PAS_AP_SECURE_WDOG \ 281 GPT_MAP_REGION_GRANULE( \ 282 NRD_CSS_AP_SECURE_WDOG_BASE, \ 283 NRD_CSS_AP_SECURE_WDOG_SIZE, \ 284 GPT_GPI_SECURE) 285 286 #define NRD_PAS_SECURE_SRAM_ERB_AP \ 287 GPT_MAP_REGION_GRANULE( \ 288 NRD_CSS_SECURE_SRAM_ERB_AP_BASE, \ 289 NRD_CSS_SECURE_SRAM_ERB_AP_SIZE, \ 290 GPT_GPI_SECURE) 291 292 #define NRD_PAS_NS_SRAM_ERB_AP \ 293 GPT_MAP_REGION_GRANULE( \ 294 NRD_CSS_NS_SRAM_ERB_AP_BASE, \ 295 NRD_CSS_NS_SRAM_ERB_AP_SIZE, \ 296 GPT_GPI_NS) 297 298 #define NRD_PAS_ROOT_SRAM_ERB_AP \ 299 GPT_MAP_REGION_GRANULE( \ 300 NRD_CSS_ROOT_SRAM_ERB_AP_BASE, \ 301 NRD_CSS_ROOT_SRAM_ERB_AP_SIZE, \ 302 GPT_GPI_ROOT) 303 304 #define NRD_PAS_REALM_SRAM_ERB_AP \ 305 GPT_MAP_REGION_GRANULE( \ 306 NRD_CSS_REALM_SRAM_ERB_AP_BASE, \ 307 NRD_CSS_REALM_SRAM_ERB_AP_SIZE, \ 308 GPT_GPI_REALM) 309 310 #define NRD_PAS_SECURE_SRAM_ERB_SCP \ 311 GPT_MAP_REGION_GRANULE( \ 312 NRD_CSS_SECURE_SRAM_ERB_SCP_BASE, \ 313 NRD_CSS_SECURE_SRAM_ERB_SCP_SIZE, \ 314 GPT_GPI_SECURE) 315 316 #define NRD_PAS_NS_SRAM_ERB_SCP \ 317 GPT_MAP_REGION_GRANULE( \ 318 NRD_CSS_NS_SRAM_ERB_SCP_BASE, \ 319 NRD_CSS_NS_SRAM_ERB_SCP_SIZE, \ 320 GPT_GPI_NS) 321 322 #define NRD_PAS_ROOT_SRAM_ERB_SCP \ 323 GPT_MAP_REGION_GRANULE( \ 324 NRD_CSS_ROOT_SRAM_ERB_SCP_BASE, \ 325 NRD_CSS_ROOT_SRAM_ERB_SCP_SIZE, \ 326 GPT_GPI_ROOT) 327 328 #define NRD_PAS_REALM_SRAM_ERB_SCP \ 329 GPT_MAP_REGION_GRANULE( \ 330 NRD_CSS_REALM_SRAM_ERB_SCP_BASE, \ 331 NRD_CSS_REALM_SRAM_ERB_SCP_SIZE, \ 332 GPT_GPI_REALM) 333 334 #define NRD_PAS_SECURE_SRAM_ERB_MCP \ 335 GPT_MAP_REGION_GRANULE( \ 336 NRD_CSS_SECURE_SRAM_ERB_MCP_BASE, \ 337 NRD_CSS_SECURE_SRAM_ERB_MCP_SIZE, \ 338 GPT_GPI_SECURE) 339 340 #define NRD_PAS_NS_SRAM_ERB_MCP \ 341 GPT_MAP_REGION_GRANULE( \ 342 NRD_CSS_NS_SRAM_ERB_MCP_BASE, \ 343 NRD_CSS_NS_SRAM_ERB_MCP_SIZE, \ 344 GPT_GPI_NS) 345 346 #define NRD_PAS_ROOT_SRAM_ERB_MCP \ 347 GPT_MAP_REGION_GRANULE( \ 348 NRD_CSS_ROOT_SRAM_ERB_MCP_BASE, \ 349 NRD_CSS_ROOT_SRAM_ERB_MCP_SIZE, \ 350 GPT_GPI_ROOT) 351 352 #define NRD_PAS_REALM_SRAM_ERB_MCP \ 353 GPT_MAP_REGION_GRANULE( \ 354 NRD_CSS_REALM_SRAM_ERB_MCP_BASE, \ 355 NRD_CSS_REALM_SRAM_ERB_MCP_SIZE, \ 356 GPT_GPI_REALM) 357 358 #define NRD_PAS_SECURE_SRAM_ERB_RSE \ 359 GPT_MAP_REGION_GRANULE( \ 360 NRD_CSS_SECURE_SRAM_ERB_RSE_BASE, \ 361 NRD_CSS_SECURE_SRAM_ERB_RSE_SIZE, \ 362 GPT_GPI_SECURE) 363 364 #define NRD_PAS_NS_SRAM_ERB_RSE \ 365 GPT_MAP_REGION_GRANULE( \ 366 NRD_CSS_NS_SRAM_ERB_RSE_BASE, \ 367 NRD_CSS_NS_SRAM_ERB_RSE_SIZE, \ 368 GPT_GPI_NS) 369 370 #define NRD_PAS_ROOT_SRAM_ERB_RSE \ 371 GPT_MAP_REGION_GRANULE( \ 372 NRD_CSS_ROOT_SRAM_ERB_RSE_BASE, \ 373 NRD_CSS_ROOT_SRAM_ERB_RSE_SIZE, \ 374 GPT_GPI_ROOT) 375 376 #define NRD_PAS_REALM_SRAM_ERB_RSE \ 377 GPT_MAP_REGION_GRANULE( \ 378 NRD_CSS_REALM_SRAM_ERB_RSE_BASE, \ 379 NRD_CSS_REALM_SRAM_ERB_RSE_SIZE, \ 380 GPT_GPI_REALM) 381 382 #define NRD_PAS_RSE_SECURE_SRAM_ERB_RSM \ 383 GPT_MAP_REGION_GRANULE( \ 384 NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_BASE, \ 385 NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_SIZE, \ 386 GPT_GPI_SECURE) 387 388 #define NRD_PAS_RSE_NS_SRAM_ERB_RSM \ 389 GPT_MAP_REGION_GRANULE( \ 390 NRD_CSS_RSE_NS_SRAM_ERB_RSM_BASE, \ 391 NRD_CSS_RSE_NS_SRAM_ERB_RSM_SIZE, \ 392 GPT_GPI_NS) 393 394 #define NRD_PAS_SCP_SECURE_SRAM_ERB_RSM \ 395 GPT_MAP_REGION_GRANULE( \ 396 NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_BASE, \ 397 NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_SIZE, \ 398 GPT_GPI_SECURE) 399 400 #define NRD_PAS_SCP_NS_SRAM_ERB_RSM \ 401 GPT_MAP_REGION_GRANULE( \ 402 NRD_CSS_SCP_NS_SRAM_ERB_RSM_BASE, \ 403 NRD_CSS_SCP_NS_SRAM_ERB_RSM_SIZE, \ 404 GPT_GPI_NS) 405 406 #define NRD_PAS_MCP_SECURE_SRAM_ERB_RSM \ 407 GPT_MAP_REGION_GRANULE( \ 408 NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_BASE, \ 409 NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_SIZE, \ 410 GPT_GPI_SECURE) 411 412 #define NRD_PAS_MCP_NS_SRAM_ERB_RSM \ 413 GPT_MAP_REGION_GRANULE( \ 414 NRD_CSS_MCP_NS_SRAM_ERB_RSM_BASE, \ 415 NRD_CSS_MCP_NS_SRAM_ERB_RSM_SIZE, \ 416 GPT_GPI_NS) 417 418 #define NRD_PAS_AP_SCP_ROOT_MHU \ 419 GPT_MAP_REGION_GRANULE( \ 420 NRD_CSS_AP_SCP_ROOT_MHU_BASE, \ 421 NRD_CSS_AP_SCP_ROOT_MHU_SIZE, \ 422 GPT_GPI_ROOT) 423 424 #define NRD_PAS_AP_MCP_NS_MHU \ 425 GPT_MAP_REGION_GRANULE( \ 426 NRD_CSS_AP_MCP_NS_MHU_BASE, \ 427 NRD_CSS_AP_MCP_NS_MHU_SIZE, \ 428 GPT_GPI_NS) 429 430 #define NRD_PAS_AP_MCP_SECURE_MHU \ 431 GPT_MAP_REGION_GRANULE( \ 432 NRD_CSS_AP_MCP_SECURE_MHU_BASE, \ 433 NRD_CSS_AP_MCP_SECURE_MHU_SIZE, \ 434 GPT_GPI_SECURE) 435 436 #define NRD_PAS_AP_MCP_ROOT_MHU \ 437 GPT_MAP_REGION_GRANULE( \ 438 NRD_CSS_AP_MCP_ROOT_MHU_BASE, \ 439 NRD_CSS_AP_MCP_ROOT_MHU_SIZE, \ 440 GPT_GPI_ROOT) 441 442 #define NRD_PAS_AP_RSE_NS_MHU \ 443 GPT_MAP_REGION_GRANULE( \ 444 NRD_CSS_AP_RSE_NS_MHU_BASE, \ 445 NRD_CSS_AP_RSE_NS_MHU_SIZE, \ 446 GPT_GPI_NS) 447 448 #define NRD_PAS_AP_RSE_SECURE_MHU \ 449 GPT_MAP_REGION_GRANULE( \ 450 NRD_CSS_AP_RSE_SECURE_MHU_BASE, \ 451 NRD_CSS_AP_RSE_SECURE_MHU_SIZE, \ 452 GPT_GPI_SECURE) 453 454 #define NRD_PAS_AP_RSE_ROOT_MHU \ 455 GPT_MAP_REGION_GRANULE( \ 456 NRD_CSS_AP_RSE_ROOT_MHU_BASE, \ 457 NRD_CSS_AP_RSE_ROOT_MHU_SIZE, \ 458 GPT_GPI_ROOT) 459 460 #define NRD_PAS_AP_RSE_REALM_MHU \ 461 GPT_MAP_REGION_GRANULE( \ 462 NRD_CSS_AP_RSE_REALM_MHU_BASE, \ 463 NRD_CSS_AP_RSE_REALM_MHU_SIZE, \ 464 GPT_GPI_REALM) 465 466 #define NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU \ 467 GPT_MAP_REGION_GRANULE( \ 468 NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_BASE, \ 469 NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_SIZE, \ 470 GPT_GPI_ROOT) 471 472 #define NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR \ 473 GPT_MAP_REGION_GRANULE( \ 474 NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_BASE, \ 475 NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_SIZE, \ 476 GPT_GPI_SECURE) 477 478 #define NRD_PAS_STM_SYSTEM_ITS \ 479 GPT_MAP_REGION_GRANULE( \ 480 NRD_CSS_STM_SYSTEM_ITS_BASE, \ 481 NRD_CSS_STM_SYSTEM_ITS_SIZE, \ 482 GPT_GPI_NS) 483 484 #define NRD_PAS_SCP_MCP_RSE_SHARED_SRAM \ 485 GPT_MAP_REGION_GRANULE( \ 486 NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_BASE, \ 487 NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_SIZE, \ 488 GPT_GPI_ANY) 489 490 #define NRD_PAS_GIC \ 491 GPT_MAP_REGION_GRANULE( \ 492 NRD_CSS_GIC_BASE, \ 493 NRD_CSS_GIC_SIZE, \ 494 GPT_GPI_ANY) 495 496 #define NRD_PAS_NS_DRAM \ 497 GPT_MAP_REGION_GRANULE( \ 498 ARM_NS_DRAM1_BASE, \ 499 ARM_NS_DRAM1_SIZE, \ 500 GPT_GPI_NS) 501 502 #define NRD_PAS_DRAM1_CHIP1 \ 503 GPT_MAP_REGION_GRANULE( \ 504 NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 1), \ 505 ARM_DRAM1_SIZE, \ 506 GPT_GPI_NS) 507 508 #define NRD_PAS_DRAM1_CHIP2 \ 509 GPT_MAP_REGION_GRANULE( \ 510 NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 2), \ 511 ARM_DRAM1_SIZE, \ 512 GPT_GPI_NS) 513 514 #define NRD_PAS_DRAM1_CHIP3 \ 515 GPT_MAP_REGION_GRANULE( \ 516 NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 3), \ 517 ARM_DRAM1_SIZE, \ 518 GPT_GPI_NS) 519 520 #if SPD_spmd && SPMD_SPM_AT_SEL2 521 #define NRD_PAS_BL32 \ 522 GPT_MAP_REGION_GRANULE( \ 523 PLAT_ARM_SPMC_BASE, \ 524 PLAT_ARM_SPMC_SIZE, \ 525 GPT_GPI_SECURE) 526 #endif 527 528 #define NRD_PAS_RMM \ 529 GPT_MAP_REGION_GRANULE( \ 530 ARM_REALM_BASE, \ 531 ARM_REALM_SIZE + \ 532 ARM_EL3_RMM_SHARED_SIZE, \ 533 GPT_GPI_REALM) 534 535 #define NRD_PAS_L1GPT \ 536 GPT_MAP_REGION_GRANULE( \ 537 ARM_L1_GPT_BASE, \ 538 ARM_L1_GPT_SIZE, \ 539 GPT_GPI_ROOT) 540 541 #define NRD_PAS_CMN \ 542 GPT_MAP_REGION_GRANULE( \ 543 NRD_CSS_CMN_BASE, \ 544 NRD_CSS_CMN_SIZE, \ 545 GPT_GPI_ANY) 546 547 #define NRD_PAS_LCP_PERIPHERAL \ 548 GPT_MAP_REGION_GRANULE( \ 549 NRD_CSS_LCP_PERIPHERAL_BASE, \ 550 NRD_CSS_LCP_PERIPHERAL_SIZE, \ 551 GPT_GPI_ANY) 552 553 #define NRD_PAS_DDR_IO \ 554 GPT_MAP_REGION_GRANULE( \ 555 NRD_CSS_DDR_IO_BASE, \ 556 NRD_CSS_DDR_IO_SIZE, \ 557 GPT_GPI_ANY) 558 559 #define NRD_PAS_SMMU_NCI_IO \ 560 GPT_MAP_REGION_GRANULE( \ 561 NRD_CSS_SMMU_NCI_IO_BASE, \ 562 NRD_CSS_SMMU_NCI_IO_SIZE, \ 563 GPT_GPI_ANY) 564 565 #define NRD_PAS_GPC_SMMUV3 \ 566 GPT_MAP_REGION_GRANULE( \ 567 NRD_CSS_GPC_SMMUV3_BASE, \ 568 NRD_CSS_GPC_SMMUV3_SIZE, \ 569 GPT_GPI_ROOT) 570 571 #define NRD_PAS_DRAM2_CHIP0 \ 572 GPT_MAP_REGION_GRANULE( \ 573 NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 0), \ 574 ARM_DRAM2_SIZE, \ 575 GPT_GPI_NS) 576 577 #define NRD_PAS_DRAM2_CHIP1 \ 578 GPT_MAP_REGION_GRANULE( \ 579 NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 1), \ 580 ARM_DRAM2_SIZE, \ 581 GPT_GPI_NS) 582 583 #define NRD_PAS_DRAM2_CHIP2 \ 584 GPT_MAP_REGION_GRANULE( \ 585 NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 2), \ 586 ARM_DRAM2_SIZE, \ 587 GPT_GPI_NS) 588 589 #define NRD_PAS_DRAM2_CHIP3 \ 590 GPT_MAP_REGION_GRANULE( \ 591 NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 3), \ 592 ARM_DRAM2_SIZE, \ 593 GPT_GPI_NS) 594 595 #endif /* NRD_PAS_DEF3_H */ 596