1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * This file contains the CSS specific definitions for the third generation of 7 * platforms. 8 */ 9 10 #ifndef NRD_CSS_DEF3_H 11 #define NRD_CSS_DEF3_H 12 13 /******************************************************************************* 14 * CSS memory map related defines 15 ******************************************************************************/ 16 17 /* Shared RAM */ 18 #define NRD_CSS_SHARED_SRAM_BASE UL(0x00000000) 19 20 /* General Peripherals */ 21 #define NRD_CSS_PERIPH_BASE UL(0x20000000) 22 #define NRD_CSS_PERIPH_SIZE UL(0x20000000) 23 24 /* System NCI */ 25 #define NRD_CSS_SYSTEM_NCI_BASE UL(0x20000000) 26 #define NRD_CSS_SYSTEM_NCI_SIZE UL(0x04000000) 27 28 /* Debug NIC */ 29 #define NRD_CSS_DEBUG_NIC_BASE UL(0x28000000) 30 #define NRD_CSS_DEBUG_NIC_SIZE UL(0x01000000) 31 32 /* NS UART */ 33 #define NRD_CSS_NS_UART_BASE UL(0x2A400000) 34 #define NRD_CSS_NS_UART_SIZE UL(0x00010000) 35 36 /* Secure UART */ 37 #define NRD_CSS_SECURE_UART_BASE UL(0x2A410000) 38 #define NRD_CSS_SECURE_UART_SIZE UL(0x00010000) 39 40 /* Realm UART */ 41 #define NRD_CSS_REALM_UART_BASE UL(0x2A420000) 42 #define NRD_CSS_REALM_UART_SIZE UL(0x00010000) 43 44 /* Generic Refclk */ 45 #define NRD_CSS_GENERIC_REFCLK_BASE UL(0x2A430000) 46 #define NRD_CSS_GENERIC_REFCLK_SIZE UL(0x00010000) 47 48 /* NS Watchdog */ 49 #define NRD_CSS_AP_NS_WDOG_BASE UL(0x2A440000) 50 #define NRD_CSS_AP_NS_WDOG_SIZE UL(0x00020000) 51 52 /* Root Watchdog */ 53 #define NRD_CSS_AP_ROOT_WDOG_BASE UL(0x2A460000) 54 #define NRD_CSS_AP_ROOT_WDOG_SIZE UL(0x00020000) 55 56 /* Secure Watchdog */ 57 #define NRD_CSS_AP_SECURE_WDOG_BASE UL(0x2A480000) 58 #define NRD_CSS_AP_SECURE_WDOG_SIZE UL(0x00020000) 59 60 /* SID */ 61 #define NRD_CSS_SID_BASE UL(0x2A4A0000) 62 #define NRD_CSS_SID_SIZE UL(0x00010000) 63 64 /* SRAM Secure Error Record Block - AP */ 65 #define NRD_CSS_SECURE_SRAM_ERB_AP_BASE UL(0x2A4B0000) 66 #define NRD_CSS_SECURE_SRAM_ERB_AP_SIZE UL(0x00010000) 67 68 /* SRAM NS Error Record Block - AP */ 69 #define NRD_CSS_NS_SRAM_ERB_AP_BASE UL(0x2A4C0000) 70 #define NRD_CSS_NS_SRAM_ERB_AP_SIZE UL(0x00010000) 71 72 /* SRAM Root Error Record Block - AP */ 73 #define NRD_CSS_ROOT_SRAM_ERB_AP_BASE UL(0x2A4D0000) 74 #define NRD_CSS_ROOT_SRAM_ERB_AP_SIZE UL(0x00010000) 75 76 /* SRAM Realm Error Record Block - AP */ 77 #define NRD_CSS_REALM_SRAM_ERB_AP_BASE UL(0x2A4E0000) 78 #define NRD_CSS_REALM_SRAM_ERB_AP_SIZE UL(0x00010000) 79 80 /* SRAM Secure Error Record Block - SCP */ 81 #define NRD_CSS_SECURE_SRAM_ERB_SCP_BASE UL(0x2A4F0000) 82 #define NRD_CSS_SECURE_SRAM_ERB_SCP_SIZE UL(0x00010000) 83 84 /* SRAM NS Error Record Block - SCP */ 85 #define NRD_CSS_NS_SRAM_ERB_SCP_BASE UL(0x2A500000) 86 #define NRD_CSS_NS_SRAM_ERB_SCP_SIZE UL(0x00010000) 87 88 /* SRAM Root Error Record Block - SCP */ 89 #define NRD_CSS_ROOT_SRAM_ERB_SCP_BASE UL(0x2A510000) 90 #define NRD_CSS_ROOT_SRAM_ERB_SCP_SIZE UL(0x00010000) 91 92 /* SRAM Realm Error Record Block - SCP */ 93 #define NRD_CSS_REALM_SRAM_ERB_SCP_BASE UL(0x2A520000) 94 #define NRD_CSS_REALM_SRAM_ERB_SCP_SIZE UL(0x00010000) 95 96 /* SRAM Secure Error Record Block - MCP */ 97 #define NRD_CSS_SECURE_SRAM_ERB_MCP_BASE UL(0x2A530000) 98 #define NRD_CSS_SECURE_SRAM_ERB_MCP_SIZE UL(0x00010000) 99 100 /* SRAM NS Error Record Block - MCP */ 101 #define NRD_CSS_NS_SRAM_ERB_MCP_BASE UL(0x2A540000) 102 #define NRD_CSS_NS_SRAM_ERB_MCP_SIZE UL(0x00010000) 103 104 /* SRAM Root Error Record Block - MCP */ 105 #define NRD_CSS_ROOT_SRAM_ERB_MCP_BASE UL(0x2A550000) 106 #define NRD_CSS_ROOT_SRAM_ERB_MCP_SIZE UL(0x00010000) 107 108 /* SRAM Realm Error Record Block - MCP */ 109 #define NRD_CSS_REALM_SRAM_ERB_MCP_BASE UL(0x2A560000) 110 #define NRD_CSS_REALM_SRAM_ERB_MCP_SIZE UL(0x00010000) 111 112 /* SRAM Secure Error Record Block - RSE */ 113 #define NRD_CSS_SECURE_SRAM_ERB_RSE_BASE UL(0x2A570000) 114 #define NRD_CSS_SECURE_SRAM_ERB_RSE_SIZE UL(0x00010000) 115 116 /* SRAM NS Error Record Block - RSE */ 117 #define NRD_CSS_NS_SRAM_ERB_RSE_BASE UL(0x2A580000) 118 #define NRD_CSS_NS_SRAM_ERB_RSE_SIZE UL(0x00010000) 119 120 /* SRAM Root Error Record Block - RSE */ 121 #define NRD_CSS_ROOT_SRAM_ERB_RSE_BASE UL(0x2A590000) 122 #define NRD_CSS_ROOT_SRAM_ERB_RSE_SIZE UL(0x00010000) 123 124 /* SRAM Realm Error Record Block - RSE */ 125 #define NRD_CSS_REALM_SRAM_ERB_RSE_BASE UL(0x2A5A0000) 126 #define NRD_CSS_REALM_SRAM_ERB_RSE_SIZE UL(0x00010000) 127 128 /* RSE SRAM Secure Error Record Block - RSM */ 129 #define NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5B0000) 130 #define NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000) 131 132 /* RSE SRAM Secure Error Record Block - RSM */ 133 #define NRD_CSS_RSE_NS_SRAM_ERB_RSM_BASE UL(0x2A5C0000) 134 #define NRD_CSS_RSE_NS_SRAM_ERB_RSM_SIZE UL(0x00010000) 135 136 /* SCP SRAM Secure Error Record Block - RSM */ 137 #define NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5D0000) 138 #define NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000) 139 140 /* SCP SRAM NS Error Record Block - RSM */ 141 #define NRD_CSS_SCP_NS_SRAM_ERB_RSM_BASE UL(0x2A5E0000) 142 #define NRD_CSS_SCP_NS_SRAM_ERB_RSM_SIZE UL(0x00010000) 143 144 /* MCP SRAM Secure Error Record Block - RSM */ 145 #define NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5F0000) 146 #define NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000) 147 148 /* MCP SRAM NS Error Record Block - RSM */ 149 #define NRD_CSS_MCP_NS_SRAM_ERB_RSM_BASE UL(0x2A600000) 150 #define NRD_CSS_MCP_NS_SRAM_ERB_RSM_SIZE UL(0x00010000) 151 152 /* CNTCTL Refclk Readframe */ 153 #define NRD_CSS_CNTCTL_REFCLK_READFRAME_BASE UL(0x2A800000) 154 #define NRD_CSS_CNTCTL_REFCLK_READFRAME_SIZE UL(0x00020000) 155 156 /* CNTCTL base */ 157 #define NRD_CSS_SYS_TIMCTL_BASE UL(0x2A810000) 158 159 /* Secure Timer */ 160 #define NRD_CSS_SECURE_TIMER_CTL_BASE UL(0x2A820000) 161 #define NRD_CSS_SECURE_TIMER_CTL_SIZE UL(0x00010000) 162 163 /* NS Timer */ 164 #define NRD_CSS_NS_TIMER_CTL_BASE UL(0x2A830000) 165 #define NRD_CSS_NS_TIMER_CTL_SIZE UL(0x00010000) 166 167 /* AP - SCP NS MHU */ 168 #define NRD_CSS_AP_SCP_NS_MHU_BASE UL(0x2A900000) 169 #define NRD_CSS_AP_SCP_NS_MHU_SIZE UL(0x00020000) 170 171 /* AP - SCP Secure MHU */ 172 #define NRD_CSS_AP_SCP_SECURE_MHU_BASE UL(0x2A920000) 173 #define NRD_CSS_AP_SCP_SECURE_MHU_SIZE UL(0x00020000) 174 175 /* AP - SCP Root MHU */ 176 #define NRD_CSS_AP_SCP_ROOT_MHU_BASE UL(0x2A940000) 177 #define NRD_CSS_AP_SCP_ROOT_MHU_SIZE UL(0x00020000) 178 179 /* AP - MCP NS MHU */ 180 #define NRD_CSS_AP_MCP_NS_MHU_BASE UL(0x2AA00000) 181 #define NRD_CSS_AP_MCP_NS_MHU_SIZE UL(0x00020000) 182 183 /* AP - MCP Secure MHU */ 184 #define NRD_CSS_AP_MCP_SECURE_MHU_BASE UL(0x2AA20000) 185 #define NRD_CSS_AP_MCP_SECURE_MHU_SIZE UL(0x00020000) 186 187 /* AP - MCP Root MHU */ 188 #define NRD_CSS_AP_MCP_ROOT_MHU_BASE UL(0x2AA40000) 189 #define NRD_CSS_AP_MCP_ROOT_MHU_SIZE UL(0x00020000) 190 191 /* AP - RSE NS MHU */ 192 #define NRD_CSS_AP_RSE_NS_MHU_BASE UL(0x2AB00000) 193 #define NRD_CSS_AP_RSE_NS_MHU_SIZE UL(0x00020000) 194 195 /* AP - RSE Secure MHU */ 196 #define NRD_CSS_AP_RSE_SECURE_MHU_BASE UL(0x2AB20000) 197 #define NRD_CSS_AP_RSE_SECURE_MHU_SIZE UL(0x00020000) 198 199 /* AP - RSE Root MHU */ 200 #define NRD_CSS_AP_RSE_ROOT_MHU_BASE UL(0x2AB40000) 201 #define NRD_CSS_AP_RSE_ROOT_MHU_SIZE UL(0x00020000) 202 203 /* AP - RSE Realm MHU */ 204 #define NRD_CSS_AP_RSE_REALM_MHU_BASE UL(0x2AB60000) 205 #define NRD_CSS_AP_RSE_REALM_MHU_SIZE UL(0x00020000) 206 207 /* SCP - MCP - RSE Cross chip MHU */ 208 #define NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_BASE UL(0x2AC00000) 209 #define NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_SIZE UL(0x00120000) 210 211 /* Synchronization Master Tupdate */ 212 #define NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_BASE UL(0x2B100000) 213 #define NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_SIZE UL(0x00030000) 214 215 /* AP - RSE NS MHU */ 216 #define NRD_CSS_STM_SYSTEM_ITS_BASE UL(0x2CF00000) 217 #define NRD_CSS_STM_SYSTEM_ITS_SIZE UL(0x02100000) 218 219 /* SCP - MCP - RSE Shared SRAM */ 220 #define NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_BASE UL(0x2F000000) 221 #define NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_SIZE UL(0x00400000) 222 223 /* GIC base */ 224 #define NRD_CSS_GIC_BASE UL(0x30000000) 225 #define NRD_CSS_GIC_SIZE UL(0x08000000) 226 227 /* CMN */ 228 #define NRD_CSS_CMN_BASE ULL(0x100000000) 229 #define NRD_CSS_CMN_SIZE UL(0x40000000) 230 231 /* LCP Peripherals */ 232 #define NRD_CSS_LCP_PERIPHERAL_BASE ULL(0x200000000) 233 #define NRD_CSS_LCP_PERIPHERAL_SIZE UL(0x40000000) 234 235 /* DDR IO */ 236 #define NRD_CSS_DDR_IO_BASE ULL(0x240000000) 237 #define NRD_CSS_DDR_IO_SIZE UL(0x40000000) 238 239 /* SMMU & NCI IO */ 240 #define NRD_CSS_SMMU_NCI_IO_BASE ULL(0x280000000) 241 #define NRD_CSS_SMMU_NCI_IO_SIZE UL(0x60000000) 242 243 /* GPC SMMU */ 244 #define NRD_CSS_GPC_SMMUV3_BASE UL(0x300000000) 245 #define NRD_CSS_GPC_SMMUV3_SIZE UL(0x8000000) 246 247 /* DRAM1 */ 248 #define NRD_CSS_DRAM1_BASE UL(0x80000000) 249 250 /* DRAM2 */ 251 #define NRD_CSS_DRAM2_BASE ULL(0x8080000000) 252 253 /******************************************************************************* 254 * MHUv3 related definitions 255 ******************************************************************************/ 256 257 #define MHU_V3_MBX_FRAME_OFFSET UL(0x10000) 258 259 /* MHUv3 Postbox and Mailbox register frame base */ 260 #define AP_RSE_ROOT_MHU_V3_PBX NRD_CSS_AP_RSE_ROOT_MHU_BASE 261 #define AP_RSE_ROOT_MHU_V3_MBX NRD_CSS_AP_RSE_ROOT_MHU_BASE + \ 262 MHU_V3_MBX_FRAME_OFFSET 263 264 #define AP_RSE_SECURE_MHU_V3_PBX NRD_CSS_AP_RSE_SECURE_MHU_BASE 265 #define AP_RSE_SECURE_MHU_V3_MBX NRD_CSS_AP_RSE_SECURE_MHU_BASE + \ 266 MHU_V3_MBX_FRAME_OFFSET 267 268 #endif /* NRD_CSS_DEF3_H */ 269