xref: /rk3399_ARM-atf/include/lib/cpus/aarch64/neoverse_v3.h (revision a35d6c5dcc7d869b1f9b4d6b741b959ec8e182ca)
1 /*
2  * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef NEOVERSE_V3_H
8 #define NEOVERSE_V3_H
9 
10 
11 #define NEOVERSE_V3_VNAE_MIDR				U(0x410FD830)
12 #define NEOVERSE_V3_MIDR				U(0x410FD840)
13 
14 /*******************************************************************************
15  * CPU Extended Control register specific definitions.
16  ******************************************************************************/
17 #define NEOVERSE_V3_CPUECTLR_EL1				S3_0_C15_C1_4
18 
19 /*******************************************************************************
20  * CPU Power Control register specific definitions
21  ******************************************************************************/
22 #define NEOVERSE_V3_CPUPWRCTLR_EL1				S3_0_C15_C2_7
23 #define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
24 #define NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT	        U(4)
25 #define NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH	        U(3)
26 #define NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT	        U(7)
27 #define NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH	        U(3)
28 
29 /*******************************************************************************
30  * CPU Auxiliary control register definitions
31  ******************************************************************************/
32 #define NEOVERSE_V3_CPUACTLR2_EL1				S3_0_C15_C1_1
33 #define NEOVERSE_V3_CPUACTLR4_EL1				S3_0_C15_C1_3
34 #define NEOVERSE_V3_CPUACTLR6_EL1				S3_0_C15_C8_1
35 
36 /*******************************************************************************
37  * CPU instruction patching register definitions
38  ******************************************************************************/
39 #define NEOVERSE_V3_CPUPSELR_EL3				S3_6_C15_C8_0
40 #define NEOVERSE_V3_CPUPCR_EL3					S3_6_C15_C8_1
41 #define NEOVERSE_V3_CPUPOR_EL3					S3_6_C15_C8_2
42 #define NEOVERSE_V3_CPUPMR_EL3					S3_6_C15_C8_3
43 
44 #ifndef __ASSEMBLER__
45 long check_erratum_neoverse_v3_3701767(long cpu_rev);
46 #endif /* __ASSEMBLER__ */
47 
48 #endif /* NEOVERSE_V3_H */
49