1 /* 2 * Copyright 2019-2021, 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef S32G2_NCORE_H 8 #define S32G2_NCORE_H 9 10 #include <stdbool.h> 11 12 #define NCORE_BASE_ADDR UL(0x50400000) 13 14 #define A53_CLUSTER0_CAIU U(0) 15 #define A53_CLUSTER1_CAIU U(1) 16 17 /** 18 * Directory Unit Registers 19 * 20 * The directory provides a point of serialization for establishing transaction 21 * ordering and sequences coherence operations and memory accesses. 22 */ 23 #define NCORE_DIRU(N) (NCORE_BASE_ADDR + UL(0x80000) + ((N) * UL(0x1000))) 24 25 /* DIRU Snoop Filtering Enable */ 26 #define NCORE_DIRUSFE(N) (NCORE_DIRU(N) + UL(0x10)) 27 #define NCORE_DIRUSFE_SFEN(SF) BIT_32(SF) 28 29 /* DIRU Caching Agent Snoop Enable */ 30 #define NCORE_DIRUCASE(N) (NCORE_DIRU(N) + UL(0x40)) 31 #define NCORE_DIRUCASE_CASNPEN(CAIU) BIT_32(CAIU) 32 33 /* DIRU Snoop Filter Maintenance Control */ 34 #define NCORE_DIRUSFMC(N) (NCORE_DIRU(N) + UL(0x80)) 35 #define NCORE_DIRUSFMC_SFID(SF) ((SF) << 16U) 36 #define NCORE_DIRUSFMC_SFMNTOP_ALL U(0x0) 37 38 /* DIRU Snoop Filter Maintenance Activity */ 39 #define NCORE_DIRUSFMA(N) (NCORE_DIRU(N) + UL(0x84)) 40 #define NCORE_DIRUSFMA_MNTOPACTV BIT_32(0) 41 42 /** 43 * Coherent Agent Interface Unit Registers 44 * 45 * CAI provides a means for a fully-coherent agent to be connected to the Ncore. 46 * The CAI behaves as a fully-coherent slave. 47 */ 48 #define NCORE_CAIU(N) (NCORE_BASE_ADDR + ((N) * UL(0x1000))) 49 #define NCORE_CAIU0_BASE_ADDR NCORE_BASE_ADDR 50 51 /* CAIU Transaction Control */ 52 #define NCORE_CAIUTC_OFF UL(0x0) 53 #define NCORE_CAIUTC_ISOLEN_SHIFT U(1) 54 #define NCORE_CAIUTC_ISOLEN_MASK BIT_32(NCORE_CAIUTC_ISOLEN_SHIFT) 55 56 #define NCORE_CAIUTC(N) (NCORE_CAIU(N) + NCORE_CAIUTC_OFF) 57 58 /* CAIU Identification */ 59 #define NCORE_CAIUID(n) (NCORE_CAIU(n) + UL(0xFFC)) 60 #define NCORE_CAIUID_TYPE GENMASK_32(U(19), U(16)) 61 #define NCORE_CAIUID_TYPE_ACE_DVM U(0x0) 62 63 /** 64 * Coherent Subsystem Registers 65 */ 66 #define NCORE_CSR (NCORE_BASE_ADDR + UL(0xFF000)) 67 68 /* Coherent Subsystem ACE DVM Snoop Enable */ 69 #define NCORE_CSADSE (NCORE_CSR + UL(0x40)) 70 #define NCORE_CSADSE_DVMSNPEN(CAIU) BIT_32(CAIU) 71 72 /* Coherent Subsystem Identification */ 73 #define NCORE_CSID (NCORE_CSR + UL(0xFFC)) 74 #define NCORE_CSID_NUMSFS_SHIFT U(18) 75 #define NCORE_CSID_NUMSFS_MASK GENMASK_32(U(22), NCORE_CSID_NUMSFS_SHIFT) 76 #define NCORE_CSID_NUMSFS(CSIDR) (((CSIDR) & NCORE_CSID_NUMSFS_MASK) \ 77 >> NCORE_CSID_NUMSFS_SHIFT) 78 79 /* Coherent Subsystem Unit Identification */ 80 #define NCORE_CSUID (NCORE_CSR + UL(0xFF8)) 81 #define NCORE_CSUID_NUMCMIUS_SHIFT U(24) 82 #define NCORE_CSUID_NUMCMIUS_MASK GENMASK_32(U(29), NCORE_CSUID_NUMCMIUS_SHIFT) 83 #define NCORE_CSUID_NUMCMIUS(CSUIDR) (((CSUIDR) & NCORE_CSUID_NUMCMIUS_MASK) \ 84 >> NCORE_CSUID_NUMCMIUS_SHIFT) 85 #define NCORE_CSUID_NUMDIRUS_SHIFT U(16) 86 #define NCORE_CSUID_NUMDIRUS_MASK GENMASK_32(U(21), NCORE_CSUID_NUMDIRUS_SHIFT) 87 #define NCORE_CSUID_NUMDIRUS(CSUIDR) (((CSUIDR) & NCORE_CSUID_NUMDIRUS_MASK) \ 88 >> NCORE_CSUID_NUMDIRUS_SHIFT) 89 #define NCORE_CSUID_NUMNCBUS_SHIFT U(8) 90 #define NCORE_CSUID_NUMNCBUS_MASK GENMASK_32(U(13), NCORE_CSUID_NUMNCBUS_SHIFT) 91 #define NCORE_CSUID_NUMNCBUS(CSUIDR) (((CSUIDR) & NCORE_CSUID_NUMNCBUS_MASK) \ 92 >> NCORE_CSUID_NUMNCBUS_SHIFT) 93 94 #ifndef __ASSEMBLER__ 95 void ncore_caiu_online(uint32_t caiu); 96 void ncore_caiu_offline(uint32_t caiu); 97 void ncore_init(void); 98 bool ncore_is_caiu_online(uint32_t caiu); 99 void ncore_disable_caiu_isolation(uint32_t caiu); 100 #endif /* __ASSEMBLER__ */ 101 102 #endif /* S32G2_NCORE_H */ 103