xref: /rockchip-linux_mpp/inc/mpp_sys_cfg.h (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3  * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4  */
5 
6 #ifndef __MPP_SYS_CFG_H__
7 #define __MPP_SYS_CFG_H__
8 
9 #include "mpp_frame.h"
10 #include "mpp_list.h"
11 
12 typedef enum MppSysDecBufCkhCfgChange_e {
13     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_ENABLE           = (1 << 0),
14     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_TYPE             = (1 << 1),
15     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FMT_CODEC        = (1 << 2),
16     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FMT_FBC          = (1 << 3),
17     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FMT_HDR          = (1 << 4),
18     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_WIDTH            = (1 << 5),
19     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_HEIGHT           = (1 << 6),
20     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_TOP         = (1 << 7),
21     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_BOTTOM      = (1 << 8),
22     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_LEFT        = (1 << 9),
23     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_RIGHT       = (1 << 10),
24     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FLAG_METADATA    = (1 << 11),
25     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FLAG_THUMBNAIL   = (1 << 12),
26     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_H_STRIDE_BYTE    = (1 << 13),
27     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_V_STRIDE         = (1 << 14),
28 
29     MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_ALL              = (0xFFFFFFFF),
30 } MppSysDecBufCkhChange;
31 
32 typedef struct MppSysBaseCfg_t {
33     RK_U64 change;
34 
35     RK_U32 enable;
36 
37     /* input args start */
38     MppCodingType type;
39     MppFrameFormat fmt_codec;
40     RK_U32 fmt_fbc;
41     RK_U32 fmt_hdr;
42 
43     /* video codec width and height */
44     RK_U32 width;
45     RK_U32 height;
46 
47     /* display crop info */
48     RK_U32 crop_top;
49     RK_U32 crop_bottom;
50     RK_U32 crop_left;
51     RK_U32 crop_right;
52 
53     /* bit mask for metadata and thumbnail config */
54     RK_U32 has_metadata;
55     RK_U32 has_thumbnail;
56 
57     /* extra protocol config */
58     /* H.265 ctu size, VP9/Av1 super block size */
59     RK_U32 unit_size;
60 
61     /* output args start */
62     /* system support capability */
63     RK_U32 cap_fbc;
64     RK_U32 cap_tile;
65 
66     /* 2 horizontal stride for 2 planes like Y/UV */
67     RK_U32 h_stride_by_pixel;
68     RK_U32 h_stride_by_byte;
69     RK_U32 v_stride;
70     RK_U32 buf_total_size;
71 
72     /* fbc display offset config for some fbc version */
73     RK_U32 offset_y;
74     RK_U32 size_total;
75     RK_U32 size_fbc_hdr;
76     RK_U32 size_fbc_bdy;
77 
78     /* extra buffer size */
79     RK_U32 size_metadata;
80     RK_U32 size_thumbnail;
81 } MppSysDecBufChkCfg;
82 
83 typedef struct MppSysCfgSet_t {
84     RK_U32 change;
85     MppSysDecBufChkCfg dec_buf_chk;
86 } MppSysCfgSet;
87 
88 #ifdef __cplusplus
89 extern "C" {
90 #endif
91 
92 MPP_RET mpp_sys_dec_buf_chk_proc(MppSysDecBufChkCfg *cfg);
93 
94 #ifdef __cplusplus
95 }
96 #endif
97 
98 #endif /* __MPP_SYS_CFG_H__ */
99